Re: [PATCH 1/2] drm/amdgpu/gfx10: add wraparound gpu counter check for APUs as well

[Luben Tuikov <luben.tuikov@amd.com>]

Seems reasonable.

Series is Acked-by: Luben Tuikov <luben.tuikov@amd.com>

Regards,
Luben

On 2021-11-18 14:54, Alex Deucher wrote:
> Apply the same check we do for dGPUs for APUs as well.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index e7dfeb466a0e..dbe7442fb25c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7707,8 +7707,19 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>  	switch (adev->ip_versions[GC_HWIP][0]) {
>  	case IP_VERSION(10, 3, 1):
>  	case IP_VERSION(10, 3, 3):
> -		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
> -			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
> +		preempt_disable();
> +		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
> +		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
> +		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
> +		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
> +		 * roughly every 42 seconds.
> +		 */
> +		if (hi_check != clock_hi) {
> +			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
> +			clock_hi = hi_check;
> +		}
> +		preempt_enable();
> +		clock = clock_lo | (clock_hi << 32ULL);
>  		break;
>  	default:
>  		preempt_disable();