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[2001:4c4e:24cb:f700:23e8:3719:bda9:8268]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6402a6be2eesm4237020a12.16.2025.10.29.04.26.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 04:26:28 -0700 (PDT) Message-ID: Subject: Re: [PATCH 03/14] drm/amdgpu/gmc6: Add GART space for VCPU BO From: Timur =?ISO-8859-1?Q?Krist=F3f?= To: Christian =?ISO-8859-1?Q?K=F6nig?= , amd-gfx@lists.freedesktop.org, Alex Deucher , Alexandre Demers , Rodrigo Siqueira Date: Wed, 29 Oct 2025 12:26:28 +0100 In-Reply-To: <2ba47f43-36ed-4805-8d59-fdf37f38deac@amd.com> References: <20251028220628.8371-1-timur.kristof@gmail.com> <20251028220628.8371-4-timur.kristof@gmail.com> <2ba47f43-36ed-4805-8d59-fdf37f38deac@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Wed, 2025-10-29 at 11:05 +0100, Christian K=C3=B6nig wrote: > On 10/28/25 23:06, Timur Krist=C3=B3f wrote: > > Add an extra 16M (4096 pages) to the GART before GTT. > > This space is going to be used for the VCE VCPU BO. > >=20 > > Split this into a separate patch to make it easier to bisect, > > in case there are any errors in the future. > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > > =C2=A0drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 5 ++++- > > =C2=A01 file changed, 4 insertions(+), 1 deletion(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > > b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > > index 499dfd78092d..bfeb60cfbf62 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > > @@ -214,6 +214,9 @@ static void gmc_v6_0_vram_gtt_location(struct > > amdgpu_device *adev, > > =C2=A0 amdgpu_gmc_set_agp_default(adev, mc); > > =C2=A0 amdgpu_gmc_vram_location(adev, mc, base); > > =C2=A0 amdgpu_gmc_gart_location(adev, mc, > > AMDGPU_GART_PLACEMENT_LOW); > > + > > + /* Add space for VCE's VCPU BO so that VCE1 can access it. > > */ > > + mc->num_gart_pages_before_gtt +=3D 4096; >=20 > 4096*4KiB=3D16MiB. Do we really need so much? Is it enough to have just enough space for the VCPU BO? In that case, I think we can use just 512 KiB (rounded up) if I understand the VCPU BO size correctly. That would be 128 pages. >=20 > > =C2=A0} > > =C2=A0 > > =C2=A0static void gmc_v6_0_mc_program(struct amdgpu_device *adev) > > @@ -338,7 +341,7 @@ static int gmc_v6_0_mc_init(struct > > amdgpu_device *adev) > > =C2=A0 case CHIP_TAHITI:=C2=A0=C2=A0 /* UVD, VCE do not support > > GPUVM */ > > =C2=A0 case CHIP_PITCAIRN: /* UVD, VCE do not support > > GPUVM */ > > =C2=A0 case CHIP_OLAND:=C2=A0=C2=A0=C2=A0 /* UVD, VCE do not support > > GPUVM */ > > - adev->gmc.gart_size =3D 1024ULL << 20; > > + adev->gmc.gart_size =3D 1040ULL << 20; >=20 > Ideally that should be a power of two. >=20 > We can in theory increase it in units of 2MiB without wasting memory, > but I'm not 100% sure if that is actually tested everywhere. >=20 > Regards, > Christian. >=20 > > =C2=A0 break; > > =C2=A0 } > > =C2=A0 } else {