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Wed, 4 Mar 2026 03:07:15 +0000 Message-ID: Date: Wed, 4 Mar 2026 08:37:10 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/amdgpu/gfx12.1: add support for disable_kq To: Alex Deucher , amd-gfx@lists.freedesktop.org References: <20260128195327.2158888-1-alexander.deucher@amd.com> Content-Language: en-US From: "Lazar, Lijo" In-Reply-To: <20260128195327.2158888-1-alexander.deucher@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MA5P287CA0144.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:1d7::16) To SA0PR12MB7091.namprd12.prod.outlook.com (2603:10b6:806:2d5::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA0PR12MB7091:EE_|DS0PR12MB8502:EE_ X-MS-Office365-Filtering-Correlation-Id: 9867d9d5-59d4-4444-5b72-08de799b2336 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info: Pz/YS89wNIO2h2y6ZWJRXfSms3QGrGCLBztSPmb5iizlr3Qs4TDTj7ziSjHDrUfYof+2J8APB9iN9URU3uTstRrfP0tu59Lipc6jjbNLljKboY4dZg0C+fw/3DPcNiptSpvE39ZmJdbOOPtWQEebSx+dJDAkP4hUy0ZUfBsTkVOoHX/NUMul5S6mDJE1PVGS0yg9raBazIXIzPY/qV12F+OzLd2dtrFmi3C+6rOveHJUJDGdhxLXMrzNIierg94DI8Xi/pChWTH3O8YQPLLnTz3WcN5i423xICUoXWv2eKQ7lKNMap1OQtsha6/oqJtMnJ819D2e68+9bOzNMtONy3f/r7zCZ1iSOrmZ6MeghrrAc8P1NAhv7kBjm+16Bdo2Vn2l4wuENDQVHQJpmLljmxZILBUURwFs/PLuEtDknTT4UKzgjuwsZqhCsKpUcBPTIqV+friszC8otNwDgLIbibjgk/uJQQ7WjznzacstZIPryMirr/IUy0a3O20Ia50UeIPTqudnCHusPuJyMfPowGEaD6Ig5ddI52VzgTDhH+i4IsCjz4ks1FxJPwVBO05afXRM2k8e0gC8IobH4NB5LTe2j1XflpbbuLI5j5kdkERjyedBTY/7prPfc8P5ju8wIvfbYxsAJdGrrhnAA7TjuE0+c3fImL3nkIPwHmcpzilaHOVBqsNakh3ILcv3o1OVZ7HKAIzN+s955QAoi5zFYZTkRQCj5YhQQ4w/62a+Cow= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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For testing, kernel queues can be re-enabled > by setting amdgpu.user_queue=0 > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 109 +++++++++++++++++++------ > 1 file changed, 82 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > index 08ae50a6313f3..f93ee275ce398 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > @@ -1155,11 +1155,13 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) > break; > } > > - /* recalculate compute rings to use based on hardware configuration */ > - num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * > - adev->gfx.mec.num_queue_per_pipe) / 2; > - adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, > - num_compute_rings); > + if (adev->gfx.num_compute_rings) { > + /* recalculate compute rings to use based on hardware configuration */ > + num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * > + adev->gfx.mec.num_queue_per_pipe) / 2; > + adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, > + num_compute_rings); > + } > > num_xcc = NUM_XCC(adev->gfx.xcc_mask); > > @@ -2794,6 +2796,36 @@ static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, > gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); > } > > +static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev, > + bool enable) > +{ > + unsigned int irq_type; > + int m, p, r, x, num_xcc; > + > + if (adev->gfx.disable_kq) { > + num_xcc = NUM_XCC(adev->gfx.xcc_mask); > + for (x = 0; x < num_xcc; x++) { > + for (m = 0; m < adev->gfx.mec.num_mec; ++m) { > + for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { > + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > + + (m * adev->gfx.mec.num_pipe_per_mec) > + + p; if x is not involved in type calculation, I guess iteration over x is not required. Only the handler for the interrupt type needs to be enabled once. > + if (enable) > + r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, > + irq_type); > + else > + r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, > + irq_type); > + if (r) > + return r; > + } > + } > + } > + } > + > + return 0; > +} > + > static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) > { > struct amdgpu_device *adev = ip_block->adev; > @@ -2801,6 +2833,7 @@ static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) > > amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); > amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); > + gfx_v12_1_set_userq_eop_interrupts(adev, false); > > num_xcc = NUM_XCC(adev->gfx.xcc_mask); > for (i = 0; i < num_xcc; i++) { > @@ -2868,10 +2901,26 @@ static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) > { > struct amdgpu_device *adev = ip_block->adev; > > + > + switch (amdgpu_user_queue) { > + case -1: > + default: > + adev->gfx.disable_kq = true; > + adev->gfx.disable_uq = true; > + break; > + case 0: > + adev->gfx.disable_kq = false; > + adev->gfx.disable_uq = true; > + break; > + } > + > adev->gfx.funcs = &gfx_v12_1_gfx_funcs; > > - adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), > - AMDGPU_MAX_COMPUTE_RINGS); > + if (adev->gfx.disable_kq) > + adev->gfx.num_compute_rings = 0; > + else > + adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), > + AMDGPU_MAX_COMPUTE_RINGS); > > gfx_v12_1_set_kiq_pm4_funcs(adev); > gfx_v12_1_set_ring_funcs(adev); > @@ -2898,6 +2947,10 @@ static int gfx_v12_1_late_init(struct amdgpu_ip_block *ip_block) > if (r) > return r; > > + r = gfx_v12_1_set_userq_eop_interrupts(adev, true); > + if (r) > + return r; > + > return 0; > } > > @@ -3719,29 +3772,31 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, > if (xcc_id == -EINVAL) > return; > > - switch (me_id) { > - case 0: > - for (i = 0; i < adev->gfx.num_gfx_rings; i++) { > - ring = &adev->gfx.gfx_ring[i]; > - /* we only enabled 1 gfx queue per pipe for now */ > - if (ring->me == me_id && ring->pipe == pipe_id) > - drm_sched_fault(&ring->sched); > - } > - break; > - case 1: > - case 2: > - for (i = 0; i < adev->gfx.num_compute_rings; i++) { > - ring = &adev->gfx.compute_ring > + if (!adev->gfx.disable_kq) { If no handled here, is this unexpected or handled somewhere else? > + switch (me_id) { > + case 0: > + for (i = 0; i < adev->gfx.num_gfx_rings; i++) { > + ring = &adev->gfx.gfx_ring[i]; > + /* we only enabled 1 gfx queue per pipe for now */ > + if (ring->me == me_id && ring->pipe == pipe_id) > + drm_sched_fault(&ring->sched); > + } Not related to this patch, but this code looks redundant. Thanks, Lijo > + break; > + case 1: > + case 2: > + for (i = 0; i < adev->gfx.num_compute_rings; i++) { > + ring = &adev->gfx.compute_ring > [i + > xcc_id * adev->gfx.num_compute_rings]; > - if (ring->me == me_id && ring->pipe == pipe_id && > - ring->queue == queue_id) > - drm_sched_fault(&ring->sched); > + if (ring->me == me_id && ring->pipe == pipe_id && > + ring->queue == queue_id) > + drm_sched_fault(&ring->sched); > + } > + break; > + default: > + BUG(); > + break; > } > - break; > - default: > - BUG(); > - break; > } > } >