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Fri, 26 Jul 2024 07:05:46 +0000 Message-ID: Date: Fri, 26 Jul 2024 09:05:41 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/radeon/evergreen_cs: fix int overflow errors in cs track offsets To: Nikita Zhandarovich , Alex Deucher , Xinhui Pan , David Airlie , Daniel Vetter Cc: Jerome Glisse , Dave Airlie , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org, stable@vger.kernel.org References: <20240725180950.15820-1-n.zhandarovich@fintech.ru> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20240725180950.15820-1-n.zhandarovich@fintech.ru> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR4P281CA0400.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:cf::20) To PH7PR12MB5685.namprd12.prod.outlook.com (2603:10b6:510:13c::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB5685:EE_|DM4PR12MB5841:EE_ X-MS-Office365-Filtering-Correlation-Id: 885389e4-d85b-4612-46ca-08dcad415f0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|7416014; 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Then IIRC the underlying hw can only handle a 32bit address space so having the offset as long is incorrect to begin with. And finally that is absolutely not material for stable. Regards, Christian. > Signed-off-by: Nikita Zhandarovich > --- > P.S. While I am not certain that track->cb_color_bo_offset[id] > actually ends up taking values high enough to cause an overflow, > nonetheless I thought it prudent to cast it to ulong as well. > > drivers/gpu/drm/radeon/evergreen_cs.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c > index 1fe6e0d883c7..d734d221e2da 100644 > --- a/drivers/gpu/drm/radeon/evergreen_cs.c > +++ b/drivers/gpu/drm/radeon/evergreen_cs.c > @@ -433,7 +433,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i > return r; > } > > - offset = track->cb_color_bo_offset[id] << 8; > + offset = (unsigned long)track->cb_color_bo_offset[id] << 8; > if (offset & (surf.base_align - 1)) { > dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n", > __func__, __LINE__, id, offset, surf.base_align); > @@ -455,7 +455,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i > min = surf.nby - 8; > } > bsize = radeon_bo_size(track->cb_color_bo[id]); > - tmp = track->cb_color_bo_offset[id] << 8; > + tmp = (unsigned long)track->cb_color_bo_offset[id] << 8; > for (nby = surf.nby; nby > min; nby--) { > size = nby * surf.nbx * surf.bpe * surf.nsamples; > if ((tmp + size * mslice) <= bsize) { > @@ -476,10 +476,10 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i > } > } > dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " > - "offset %d, max layer %d, bo size %ld, slice %d)\n", > + "offset %ld, max layer %d, bo size %ld, slice %d)\n", > __func__, __LINE__, id, surf.layer_size, > - track->cb_color_bo_offset[id] << 8, mslice, > - radeon_bo_size(track->cb_color_bo[id]), slice); > + (unsigned long)track->cb_color_bo_offset[id] << 8, > + mslice, radeon_bo_size(track->cb_color_bo[id]), slice); > dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", > __func__, __LINE__, surf.nbx, surf.nby, > surf.mode, surf.bpe, surf.nsamples, > @@ -608,7 +608,7 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) > return r; > } > > - offset = track->db_s_read_offset << 8; > + offset = (unsigned long)track->db_s_read_offset << 8; > if (offset & (surf.base_align - 1)) { > dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", > __func__, __LINE__, offset, surf.base_align); > @@ -627,7 +627,7 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) > return -EINVAL; > } > > - offset = track->db_s_write_offset << 8; > + offset = (unsigned long)track->db_s_write_offset << 8; > if (offset & (surf.base_align - 1)) { > dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", > __func__, __LINE__, offset, surf.base_align); > @@ -706,7 +706,7 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) > return r; > } > > - offset = track->db_z_read_offset << 8; > + offset = (unsigned long)track->db_z_read_offset << 8; > if (offset & (surf.base_align - 1)) { > dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", > __func__, __LINE__, offset, surf.base_align); > @@ -722,7 +722,7 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) > return -EINVAL; > } > > - offset = track->db_z_write_offset << 8; > + offset = (unsigned long)track->db_z_write_offset << 8; > if (offset & (surf.base_align - 1)) { > dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", > __func__, __LINE__, offset, surf.base_align);