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Fri, 7 Jun 2024 13:09:01 +0000 Message-ID: Date: Fri, 7 Jun 2024 14:08:57 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/amdkfd: Extend gfx12 trap handler fix to gfx10/11 To: Jay Cornwall , amd-gfx@lists.freedesktop.org References: <20240605231654.6374-1-jay.cornwall@amd.com> Content-Language: en-US From: Lancelot SIX In-Reply-To: <20240605231654.6374-1-jay.cornwall@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR3P281CA0067.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:4b::14) To CH3PR12MB9079.namprd12.prod.outlook.com (2603:10b6:610:1a1::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR12MB9079:EE_|CY5PR12MB6526:EE_ X-MS-Office365-Filtering-Correlation-Id: 462e9172-65b5-4298-2691-08dc86f2ff74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|376005|1800799015; X-Microsoft-Antispam-Message-Info: =?utf-8?B?WnM4L3lXd3BLTTVyUWlPMVZKaHBzOEdLV0gyRVJRNHhkTnNpcEZQY0VJNUE4?= =?utf-8?B?MDlOazIwUFRtQ1VTN0wraEFVQmEvSHJ3bWpSWFk4UHFrN0ZzMzJPTHc5NmhT?= =?utf-8?B?TGhFYXN4TGsvU0FBS0xIY2ozU0d0bytMWE5MZGhvbW4yYUE1ZjhVenRoYVdE?= =?utf-8?B?VnBWMUdYTW5nWVluRzRHSEpmNlZBTVA5bGtBS3BZWkhua1RDK0VZZG9ZV3FP?= =?utf-8?B?Nnh5TklkbXNtaVhtalJremNnbW1qbGVxRWsydnlPNUJmOXdzL1NVT05wM3dB?= =?utf-8?B?aUlOUFVqQkZMZmFiWjNXLzJPVzR4THhWalpLckRIb3hObXNMc0xzM1ZiK2Fk?= =?utf-8?B?K2VTV04vcGdpRkhscVBTbVdXL2pRTjU2d1cySHJjSTBZd2VKOTdXb2FjL3N5?= =?utf-8?B?emFhaGRUVjRXeWFiMjhMQytndndFeGtJZ2tVQ0ZSR0hkRkFvOUh3L25xek11?= =?utf-8?B?aWpMdWJxcUl5NUVQQlVXc0g0d2JUZWhtUm5PdHVhQytqS2k0OGc3NWI3clQ5?= =?utf-8?B?cDg5d2NoL2JXZG5CbCtNekhBdmNrY2F6RXljL0lQNk41TzBNSHpGQlNhTmoz?= =?utf-8?B?cXBhQjZWTitoVjVuRzZUdVZmN2dPVENkcldicVB3WFNNRXJwakJNdSt2NVZv?= =?utf-8?B?Z3FHRVdVc0lSRzFNaDlZWjZxMzdIMHpJVHc2eFNuRHNwSlJtaHZneUxwcVhj?= =?utf-8?B?UDJtSU5EbWZQQXFnYmtQQTY0YWI3dzRyT0pNMU4yMkhrRnBHWmdOZExTeXJv?= =?utf-8?B?dG9jRSsxOEVDN3c0ajFPSzZiaTRuYlVvVzFmd2twN3JZY2YrVmR1Z0R6MGgx?= =?utf-8?B?dTg3NGltZmt4cTNjN21qZmxmcTlSRHJhODR5bXo5MUhFQlVsT3Qvc2RiZWl2?= =?utf-8?B?NDFDRGtKdmpwM3ZyV2ZLR3krRnBxZCsydzFSaUhCWUcxU1AzUCs2ZE1ZK3dH?= =?utf-8?B?OGs2czVlRWJ4Sm5HKzN2VFBuNjhuVzF0R1M5YVhJNlZMd2xpcUJlNWFxTkhi?= =?utf-8?B?OXM4K25FZ3hUZDRrRC84dWRYMEZBMzErTE1mVTNvbzRuWXgrSjB6NzI3SjVm?= =?utf-8?B?S3JqbXRRak8vM2l3WFJIaG1aNGJLQnJ3cFMrSFg1T2NTS2FKRjR2SDNtRWl2?= =?utf-8?B?UmFXK1lPODRoVk1kb3dyczJIY2dkNm11RUtqaXZjZFRId29mUUE2MXhxS3hV?= =?utf-8?B?Rm9CNEJxS3d2UkJpT0tBaWFmNVhvKytIc2lwci9mSFd3cUxHTGJaZ1AzOTZp?= =?utf-8?B?bElRdlN1ZW1leVpmcjFFcExKTkUvNksvRllZQVl2UjA2Mis1cUExWldaeEVt?= =?utf-8?B?OFdCMnhaQkpTdGZkOTA1Yy95MGJDelllTkF2Rm5NMGJUS2drREl4UmJ2YlRR?= =?utf-8?B?WUdYeUFZRFFqb2x2QktVS1Bsd056RXo3cWQ0cXlvYUVnR09TMnRCU0JUM3Nr?= =?utf-8?B?UllZQ3JRWkJiU09QcVR3RmF3ejQxdEV3cXJKMWgwbXBSWU8yS25GbFE2WWVm?= =?utf-8?B?eCtQM21BM0x5RkFSSjBZRGduUGw1R1lDRFZWY3NwcU9zbVozdjd3ajc1QVVa?= =?utf-8?B?dS9ONGlvU2VYVDhwNHBQdEc2Q0E0dmdoVSt4YzBpZ2NTLzZaNDVlMXJHeWRN?= =?utf-8?B?QVIvSzlZemNxMEc5NnV0RWw0MmMxWUJJUWdoMERTYnZqTnR5QmN3ME9xTVgw?= =?utf-8?B?QUo1OHdHWUZtNU1JanVtRnF5Q3VsV09PS2NVZjU4YmFtU0dtRHVmOUZlRVhU?= =?utf-8?Q?VyTMGydo/CYR4J3+zd3twDoThYbo75DyZWJ1lcf?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Both of these fields can assert while the wavefront is > running the trap handler. > > Signed-off-by: Jay Cornwall > Cc: Lancelot Six Hi Jay, Thanks, that looks good to me (tested on gfx10.3, 11 and 12). For gfx11+ there might be a risk of overriding perf_snapshot, but that seems fine as this is not used, and such sample from cwsr restore would mostly be meaningless anyway. Reviewed-by: Lancelot Six Best, Lancelot. > --- > .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 16 +++++--- > .../amd/amdkfd/cwsr_trap_handler_gfx10.asm | 38 ++++++++++++++----- > 2 files changed, 38 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h > index 665122d1bbbd..02f7ba8c93cd 100644 > --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h > +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h > @@ -1136,7 +1136,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { > 0x705d0000, 0x807c817c, > 0x8070ff70, 0x00000080, > 0xbf0a7b7c, 0xbf85fff8, > - 0xbf82013d, 0xbef4037e, > + 0xbf82013f, 0xbef4037e, > 0x8775ff7f, 0x0000ffff, > 0x8875ff75, 0x00040000, > 0xbef60380, 0xbef703ff, > @@ -1275,7 +1275,8 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { > 0x80788478, 0xbf8c0000, > 0xb9eef815, 0xbefc036f, > 0xbefe0370, 0xbeff0371, > - 0xb9f9f816, 0xb9fbf803, > + 0xb9f9f816, 0xb9fb4803, > + 0x907b8b7b, 0xb9fba2c3, > 0xb9f3f801, 0xb96e3a05, > 0x806e816e, 0xbf0d9972, > 0xbf850002, 0x8f6e896e, > @@ -2544,7 +2545,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { > 0xe0704000, 0x705d0000, > 0x807c817c, 0x8070ff70, > 0x00000080, 0xbf0a7b7c, > - 0xbf85fff8, 0xbf820134, > + 0xbf85fff8, 0xbf820136, > 0xbef4037e, 0x8775ff7f, > 0x0000ffff, 0x8875ff75, > 0x00040000, 0xbef60380, > @@ -2683,7 +2684,8 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { > 0xf0000000, 0x80788478, > 0xbf8c0000, 0xb9eef815, > 0xbefc036f, 0xbefe0370, > - 0xbeff0371, 0xb9fbf803, > + 0xbeff0371, 0xb9fb4803, > + 0x907b8b7b, 0xb9fba2c3, > 0xb9f3f801, 0xb96e3a05, > 0x806e816e, 0xbf0d9972, > 0xbf850002, 0x8f6e896e, > @@ -2981,7 +2983,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { > 0x701d0000, 0x807d817d, > 0x8070ff70, 0x00000080, > 0xbf0a7b7d, 0xbfa2fff8, > - 0xbfa0013f, 0xbef4007e, > + 0xbfa00143, 0xbef4007e, > 0x8b75ff7f, 0x0000ffff, > 0x8c75ff75, 0x00040000, > 0xbef60080, 0xbef700ff, > @@ -3123,7 +3125,9 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { > 0x80788478, 0xbf890000, > 0xb96ef815, 0xbefd006f, > 0xbefe0070, 0xbeff0071, > - 0xb97bf803, 0xb973f801, > + 0xb97b4803, 0x857b8b7b, > + 0xb97b22c3, 0x857b867b, > + 0xb97b7443, 0xb973f801, > 0xb8ee3b05, 0x806e816e, > 0xbf0d9972, 0xbfa20002, > 0x846e896e, 0xbfa00001, > diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm > index ac3702b8e3c4..44772eec9ef4 100644 > --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm > +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm > @@ -119,9 +119,12 @@ var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 > var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 > var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 > var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 > +var SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT = 11 > var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 > #if ASIC_FAMILY >= CHIP_PLUM_BONITO > +var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT = 16 > var SQ_WAVE_TRAPSTS_WAVE_START_MASK = 0x20000 > +var SQ_WAVE_TRAPSTS_WAVE_START_SHIFT = 17 > var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x40000 > var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x100000 > #endif > @@ -137,14 +140,23 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x003F8000 > > var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 > > +var S_TRAPSTS_RESTORE_PART_1_SIZE = SQ_WAVE_TRAPSTS_SAVECTX_SHIFT > +var S_TRAPSTS_RESTORE_PART_2_SHIFT = SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT > + > #if ASIC_FAMILY < CHIP_PLUM_BONITO > var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK > +var S_TRAPSTS_RESTORE_PART_2_SIZE = 32 - S_TRAPSTS_RESTORE_PART_2_SHIFT > +var S_TRAPSTS_RESTORE_PART_3_SHIFT = 0 > +var S_TRAPSTS_RESTORE_PART_3_SIZE = 0 > #else > var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK |\ > SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK |\ > SQ_WAVE_TRAPSTS_WAVE_START_MASK |\ > SQ_WAVE_TRAPSTS_WAVE_END_MASK |\ > SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK > +var S_TRAPSTS_RESTORE_PART_2_SIZE = SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT - SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT > +var S_TRAPSTS_RESTORE_PART_3_SHIFT = SQ_WAVE_TRAPSTS_WAVE_START_SHIFT > +var S_TRAPSTS_RESTORE_PART_3_SIZE = 32 - S_TRAPSTS_RESTORE_PART_3_SHIFT > #endif > var S_TRAPSTS_HWREG = HW_REG_TRAPSTS > var S_TRAPSTS_SAVE_CONTEXT_MASK = SQ_WAVE_TRAPSTS_SAVECTX_MASK > @@ -157,6 +169,7 @@ var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK = 0x20 > var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK = 0x40 > var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT = 6 > var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK = 0x80 > +var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT = 7 > var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK = 0x100 > var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT = 8 > var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK = 0x200 > @@ -173,6 +186,11 @@ var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK |\ > SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK |\ > SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK |\ > SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK > +var S_TRAPSTS_RESTORE_PART_1_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT > +var S_TRAPSTS_RESTORE_PART_2_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT > +var S_TRAPSTS_RESTORE_PART_2_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT > +var S_TRAPSTS_RESTORE_PART_3_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT > +var S_TRAPSTS_RESTORE_PART_3_SIZE = 32 - S_TRAPSTS_RESTORE_PART_3_SHIFT > var BARRIER_STATE_SIGNAL_OFFSET = 16 > var BARRIER_STATE_VALID_OFFSET = 0 > #endif > @@ -1386,17 +1404,17 @@ L_SKIP_BARRIER_RESTORE: > s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask > #endif > > -#if ASIC_FAMILY < CHIP_GFX12 > - s_setreg_b32 hwreg(S_TRAPSTS_HWREG), s_restore_trapsts > -#else > - // EXCP_FLAG_PRIV.SAVE_CONTEXT and HOST_TRAP may have changed. > + // {TRAPSTS/EXCP_FLAG_PRIV}.SAVE_CONTEXT and HOST_TRAP may have changed. > // Only restore the other fields to avoid clobbering them. > - s_setreg_b32 hwreg(S_TRAPSTS_HWREG, 0, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT), s_restore_trapsts > - s_lshr_b32 s_restore_trapsts, s_restore_trapsts, SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT > - s_setreg_b32 hwreg(S_TRAPSTS_HWREG, SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT, 1), s_restore_trapsts > - s_lshr_b32 s_restore_trapsts, s_restore_trapsts, SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT > - s_setreg_b32 hwreg(S_TRAPSTS_HWREG, SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT, 32 - SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT), s_restore_trapsts > -#endif > + s_setreg_b32 hwreg(S_TRAPSTS_HWREG, 0, S_TRAPSTS_RESTORE_PART_1_SIZE), s_restore_trapsts > + s_lshr_b32 s_restore_trapsts, s_restore_trapsts, S_TRAPSTS_RESTORE_PART_2_SHIFT > + s_setreg_b32 hwreg(S_TRAPSTS_HWREG, S_TRAPSTS_RESTORE_PART_2_SHIFT, S_TRAPSTS_RESTORE_PART_2_SIZE), s_restore_trapsts > + > +if S_TRAPSTS_RESTORE_PART_3_SIZE > 0 > + s_lshr_b32 s_restore_trapsts, s_restore_trapsts, S_TRAPSTS_RESTORE_PART_3_SHIFT - S_TRAPSTS_RESTORE_PART_2_SHIFT > + s_setreg_b32 hwreg(S_TRAPSTS_HWREG, S_TRAPSTS_RESTORE_PART_3_SHIFT, S_TRAPSTS_RESTORE_PART_3_SIZE), s_restore_trapsts > +end > + > s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode > > // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic