From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5584CA5FC5 for ; Wed, 30 Sep 2026 13:40:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3275810F407; Wed, 30 Sep 2026 13:40:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="ge1pkB74"; dkim-atps=neutral Received: from tor.source.kernel.org (tor.source.kernel.org [172.105.4.254]) by gabe.freedesktop.org (Postfix) with ESMTPS id C490F10F407 for ; Wed, 30 Sep 2026 13:40:02 +0000 (UTC) Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id A6ED9602BA; Wed, 30 Sep 2026 13:40:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9D61D1F00898; Wed, 30 Sep 2026 13:40:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790775601; bh=xFqLMFXAho7vsZRRn0lFyqFwU98ZhNOqftrzkrRFoC8=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=ge1pkB74bT/Wcn4MCiLS13cv/WWIgkybItc4pJaNSoeQGHLZEp1GeXvnih86sfDmQ gI9SWzwOPFWN0Qe6w0gb4QeVVIABP8/q9zz5LF/N5s2wNyMCKbUZk2Mr+MhdDn/VqM tGQ4SIXuz7q+43B4g1ur4qsSUxHbBispksRWP2psjje2lyn86DeVIRZuJ0RhWKdk2o QiJRGkt6QFH4E5uANg129CAH9FTS75B6BrIAK9e5H1TX0R7iappJqztzv9QedxiPhV ZEFnTpv9B/WTN1s2GIL2Lnm4I5H3idt6CQN4ZW5/qcGgaML3eh21Rg1SjRBWx9NG0+ z/j9HDK2QkQEQ== Message-ID: Date: Wed, 30 Sep 2026 08:39:59 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] iommu/amd: Make PerfOpt compulsory Content-Language: en-US To: Vasant Hegde , Jason Gunthorpe Cc: Alex Deucher , Joerg Roedel , Suravee Suthikulpanit , "open list:RADEON and AMDGPU DRM DRIVERS" , open list , "open list:AMD IOMMU (AMD-VI)" References: <20260929013423.2313648-1-superm1@kernel.org> From: Mario Limonciello In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 9/30/26 04:38, Vasant Hegde wrote: > Mario, > > On 9/29/2026 7:04 AM, Mario Limonciello (AMD) wrote: >> PerfOpt is only a feature usable by integrated GPUs and only in identity >> mode. Instead of leaving a policy knob in amdgpu, just turn it on when >> an integrated GPU is in identity. >> >> This drops quite a bit of compatibility glue. There was a refcounting >> system, exported symbols, and device attach/detach logic. By just setting >> it immediately it's a lot more straightforward. >> >> Suggested-by: Jason Gunthorpe >> Signed-off-by: Mario Limonciello (AMD) >> --- >> v2: >> * Move WARN_ON to amd_iommu_perfopt_clear() >> * Make amd_iommu_perfopt_clear() void >> * Drop unnecessary cleanup/create paths that unset feature >> * Enable the feature in IOMMU if supported (per guidance in IVRS spec) >> * Use existing check_feature() helper instead >> --- > > > .../... > >> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c >> index c9b28e5e582ea..a1adb40d5b79d 100644 >> --- a/drivers/iommu/amd/iommu.c >> +++ b/drivers/iommu/amd/iommu.c >> @@ -2345,6 +2345,35 @@ static void pdom_detach_iommu(struct amd_iommu *iommu, >> spin_unlock_irqrestore(&pdom->lock, flags); >> } >> >> +/* >> + * Program or clear the per-IOMMU PerfOpt enable bit >> + * This allows a privileged internal GPU to be able to bypass IOMMU when >> + * in identity mode. >> + */ >> +int amd_iommu_perfopt_set(struct amd_iommu *iommu, bool enable) > > Please move this to init.c file Thanks, good suggestion. > >> +{ >> + u32 old, val, readback; >> + >> + if (!check_feature(FEATURE_PERF_OPT)) >> + return enable ? -ENODEV : 0; >> + >> + old = readl(iommu->mmio_base + MMIO_PERF_OPT_OFFSET); >> + if (old == U32_MAX) >> + return -EIO; >> + >> + val = enable ? old | PERF_OPT_EN : old & ~PERF_OPT_EN; >> + if (val != old) >> + writel(val, iommu->mmio_base + MMIO_PERF_OPT_OFFSET); >> + readback = readl(iommu->mmio_base + MMIO_PERF_OPT_OFFSET); >> + if (readback == U32_MAX || >> + (readback & PERF_OPT_EN) != (val & PERF_OPT_EN)) { >> + dev_err(iommu->iommu.dev, "Failed to set PerfOpt to %d\n", enable); >> + return -EIO; >> + } >> + > > May be check return value before enabling dev_data->perfopt? I thought about this. Let me know what you think of the approach of clearing the bit in amd_iommu_efr on failures within amd_iommu_perfopt_set(). That would mean that dev_data->perfopt doesn't get enabled later.