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From: "Christian König" <christian.koenig@amd.com>
To: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>,
	Alex Deucher <alexander.deucher@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Fix incorrect max handle limit in userq wait ioctl
Date: Wed, 25 Feb 2026 09:01:19 +0100	[thread overview]
Message-ID: <ee6a71c9-aea9-4bed-b96d-782247db2775@amd.com> (raw)
In-Reply-To: <20260225072050.1640920-1-srinivasan.shanmugam@amd.com>



On 2/25/26 08:20, Srinivasan Shanmugam wrote:
> Clang reports that a comparison in amdgpu_userq_wait_ioctl()
> is always false.
> 
> The field num_syncobj_timeline_handles is defined as __u16.
> A __u16 value can only go up to 65535.
> 
> But AMDGPU_USERQ_MAX_HANDLES was defined as 65536.
> So the check comparing the field with this limit could
> never be true.
> 
> Change the limit to U16_MAX (65535) to match the field type.
> 
> Fixes the below:
> amdgpu_userq_fence.c:642:46: warning: result of comparison of constant 65536 with expression of type '__u16' (aka 'unsigned short') is always false [-Wtautological-constant-out-of-range-compare]

Well that means that we actually don't need this check.

Adjusting the value just works around the problem.

Regards,
Christian.

>             wait_info->num_syncobj_timeline_handles > AMDGPU_USERQ_MAX_HANDLES ||
> 
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
> index 136071172111..e4bca62bcf14 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
> @@ -35,7 +35,7 @@
>  static const struct dma_fence_ops amdgpu_userq_fence_ops;
>  static struct kmem_cache *amdgpu_userq_fence_slab;
>  
> -#define AMDGPU_USERQ_MAX_HANDLES	(1U << 16)
> +#define AMDGPU_USERQ_MAX_HANDLES       U16_MAX
>  
>  int amdgpu_userq_fence_slab_init(void)
>  {


      reply	other threads:[~2026-02-25  8:01 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-25  7:20 [PATCH] drm/amdgpu: Fix incorrect max handle limit in userq wait ioctl Srinivasan Shanmugam
2026-02-25  8:01 ` Christian König [this message]

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