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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id i5-20020adfb645000000b003368c8d120fsm11510679wre.7.2024.01.15.02.26.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Jan 2024 02:26:06 -0800 (PST) Message-ID: Date: Mon, 15 Jan 2024 11:26:03 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] drm/amdgpu: Process fences on IH overflow Content-Language: en-US To: Friedrich Vock , amd-gfx@lists.freedesktop.org References: <20240114130008.868941-1-friedrich.vock@gmx.de> <20240114130008.868941-2-friedrich.vock@gmx.de> From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20240114130008.868941-2-friedrich.vock@gmx.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Joshua Ashton , stable@vger.kernel.org Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 14.01.24 um 14:00 schrieb Friedrich Vock: > If the IH ring buffer overflows, it's possible that fence signal events > were lost. Check each ring for progress to prevent job timeouts/GPU > hangs due to the fences staying unsignaled despite the work being done. That's completely unnecessary and in some cases even harmful. We already have a timeout handler for that and overflows point to severe system problem so they should never occur in a production system. Regards, Christian. > > Cc: Joshua Ashton > Cc: Alex Deucher > Cc: stable@vger.kernel.org > > Signed-off-by: Friedrich Vock > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c > index f3b0aaf3ebc6..2a246db1d3a7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c > @@ -209,6 +209,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) > { > unsigned int count; > u32 wptr; > + int i; > > if (!ih->enabled || adev->shutdown) > return IRQ_NONE; > @@ -227,6 +228,20 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) > ih->rptr &= ih->ptr_mask; > } > > + /* If the ring buffer overflowed, we might have lost some fence > + * signal interrupts. Check if there was any activity so the signal > + * doesn't get lost. > + */ > + if (ih->overflow) { > + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { > + struct amdgpu_ring *ring = adev->rings[i]; > + > + if (!ring || !ring->fence_drv.initialized) > + continue; > + amdgpu_fence_process(ring); > + } > + } > + > amdgpu_ih_set_rptr(adev, ih); > wake_up_all(&ih->wait_process); > > -- > 2.43.0 >