From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: [PATCH] drm/amdgpu: fix bug with IH ring setup Date: Tue, 13 Nov 2018 09:06:45 +0100 Message-ID: References: <1542050408-19731-1-git-send-email-Philip.Yang@amd.com> Reply-To: christian.koenig-5C7GfCeVMHo@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0344888291==" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Deucher, Alexander" , "Yang, Philip" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" This is a multi-part message in MIME format. --===============0344888291== Content-Type: multipart/alternative; boundary="------------EBE3ADD2A30050845FD90744" Content-Language: en-US This is a multi-part message in MIME format. --------------EBE3ADD2A30050845FD90744 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Am 12.11.18 um 20:33 schrieb Deucher, Alexander: > > Reviewed-by: Alex Deucher > > > > ------------------------------------------------------------------------ > *From:* amd-gfx on behalf of > Yang, Philip > *Sent:* Monday, November 12, 2018 2:20 PM > *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > *Cc:* Yang, Philip > *Subject:* [PATCH] drm/amdgpu: fix bug with IH ring setup > The bug limits the IH ring wptr address to 40bit. When the system memory > is bigger than 1TB, the bus address is more than 40bit, this causes the > interrupt cannot be handled and cleared correctly. > > Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28 > Signed-off-by: Philip Yang > --- >  drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- >  1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > index a99f717..a0fda6f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c > @@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device > *adev) >          else >                  wptr_off = adev->wb.gpu_addr + > (adev->irq.ih.wptr_offs * 4); >          WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, > lower_32_bits(wptr_off)); > -       WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, > upper_32_bits(wptr_off) & 0xFF); > +       WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, > upper_32_bits(wptr_off) & 0xFFFF); > >          /* set rptr, wptr to 0 */ >          WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx --------------EBE3ADD2A30050845FD90744 Content-Type: text/html; charset=windows-1252 Content-Transfer-Encoding: 8bit
Reviewed-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>

Am 12.11.18 um 20:33 schrieb Deucher, Alexander:

Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>



From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Yang, Philip <Philip.Yang-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, November 12, 2018 2:20 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Yang, Philip
Subject: [PATCH] drm/amdgpu: fix bug with IH ring setup
 
The bug limits the IH ring wptr address to 40bit. When the system memory
is bigger than 1TB, the bus address is more than 40bit, this causes the
interrupt cannot be handled and cleared correctly.

Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28
Signed-off-by: Philip Yang <Philip.Yang-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index a99f717..a0fda6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
         else
                 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
         WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-       WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+       WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);
 
         /* set rptr, wptr to 0 */
         WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
--
2.7.4

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