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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 09:51:34.2494 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db7a216e-18f0-4aa4-969c-08d9fc323c85 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5445 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "daniel@ffwll.ch" , "Chen, Horace" , "Lazar, Lijo" , "Koenig, Christian" , "Liu, Monk" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --------------xxLZALHhgsUeHxRAOScsGuS1 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Hi Andrey, Most part of the patches are OK, but the code will introduce a ib test fail on the disabled vcn of sienna_cichlid. In SRIOV use case we will disable one vcn on sienna_cichlid, I have attached a patch to fix this issue, please check the attachment. Best Regards, Jingwen Chen On 2/26/22 5:22 AM, Andrey Grodzovsky wrote: > Hey, patches attached - i applied the patches and resolved merge conflicts but weren't able to test as my on board's network card doesn't work with 5.16 kernel (it does with 5.17, maybe it's Kconfig issue and i need to check more). > The patches are on top of 'cababde192b2 Yifan Zhang         2 days ago     drm/amd/pm: fix mode2 reset fail for smu 13.0.5 ' commit. > > Please test and let me know. Maybe by Monday I will be able to resolve the connectivity issue on 5.16. > > Andrey > > On 2022-02-24 22:13, JingWen Chen wrote: >> Hi Andrey, >> >> Sorry for the misleading, I mean the whole patch series. We are depending on this patch series to fix the concurrency issue within SRIOV TDR sequence. >> >> >> >> On 2/25/22 1:26 AM, Andrey Grodzovsky wrote: >>> No problem if so but before I do, >>> >>> >>> JingWen - why you think this patch is needed as a standalone now ? It has no use without the >>> entire feature together with it. Is it some changes you want to do on top of that code ? >>> >>> >>> Andrey >>> >>> >>> On 2022-02-24 12:12, Deucher, Alexander wrote: >>>> [Public] >>>> >>>> >>>> If it applies cleanly, feel free to drop it in.  I'll drop those patches for drm-next since they are already in drm-misc. >>>> >>>> Alex >>>> >>>> ------------------------------------------------------------------------ >>>> *From:* amd-gfx on behalf of Andrey Grodzovsky >>>> *Sent:* Thursday, February 24, 2022 11:24 AM >>>> *To:* Chen, JingWen ; Christian König ; dri-devel@lists.freedesktop.org ; amd-gfx@lists.freedesktop.org >>>> *Cc:* Liu, Monk ; Chen, Horace ; Lazar, Lijo ; Koenig, Christian ; daniel@ffwll.ch >>>> *Subject:* Re: [RFC v4 02/11] drm/amdgpu: Move scheduler init to after XGMI is ready >>>> No because all the patch-set including this patch was landed into >>>> drm-misc-next and will reach amd-staging-drm-next on the next upstream >>>> rebase i guess. >>>> >>>> Andrey >>>> >>>> On 2022-02-24 01:47, JingWen Chen wrote: >>>>> Hi Andrey, >>>>> >>>>> Will you port this patch into amd-staging-drm-next? >>>>> >>>>> on 2/10/22 2:06 AM, Andrey Grodzovsky wrote: >>>>>> All comments are fixed and code pushed. Thanks for everyone >>>>>> who helped reviewing. >>>>>> >>>>>> Andrey >>>>>> >>>>>> On 2022-02-09 02:53, Christian König wrote: >>>>>>> Am 09.02.22 um 01:23 schrieb Andrey Grodzovsky: >>>>>>>> Before we initialize schedulers we must know which reset >>>>>>>> domain are we in - for single device there iis a single >>>>>>>> domain per device and so single wq per device. For XGMI >>>>>>>> the reset domain spans the entire XGMI hive and so the >>>>>>>> reset wq is per hive. >>>>>>>> >>>>>>>> Signed-off-by: Andrey Grodzovsky >>>>>>> One more comment below, with that fixed Reviewed-by: Christian König . >>>>>>> >>>>>>>> --- >>>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 ++++++++++++++++++++++ >>>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 34 ++-------------- >>>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  2 + >>>>>>>>      3 files changed, 51 insertions(+), 30 deletions(-) >>>>>>>> >>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>>>>>>> index 9704b0e1fd82..00123b0013d3 100644 >>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>>>>>>> @@ -2287,6 +2287,47 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) >>>>>>>>          return r; >>>>>>>>      } >>>>>>>>      +static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) >>>>>>>> +{ >>>>>>>> +    long timeout; >>>>>>>> +    int r, i; >>>>>>>> + >>>>>>>> +    for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { >>>>>>>> +        struct amdgpu_ring *ring = adev->rings[i]; >>>>>>>> + >>>>>>>> +        /* No need to setup the GPU scheduler for rings that don't need it */ >>>>>>>> +        if (!ring || ring->no_scheduler) >>>>>>>> +            continue; >>>>>>>> + >>>>>>>> +        switch (ring->funcs->type) { >>>>>>>> +        case AMDGPU_RING_TYPE_GFX: >>>>>>>> +            timeout = adev->gfx_timeout; >>>>>>>> +            break; >>>>>>>> +        case AMDGPU_RING_TYPE_COMPUTE: >>>>>>>> +            timeout = adev->compute_timeout; >>>>>>>> +            break; >>>>>>>> +        case AMDGPU_RING_TYPE_SDMA: >>>>>>>> +            timeout = adev->sdma_timeout; >>>>>>>> +            break; >>>>>>>> +        default: >>>>>>>> +            timeout = adev->video_timeout; >>>>>>>> +            break; >>>>>>>> +        } >>>>>>>> + >>>>>>>> +        r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, >>>>>>>> + ring->num_hw_submission, amdgpu_job_hang_limit, >>>>>>>> +                   timeout, adev->reset_domain.wq, ring->sched_score, ring->name); >>>>>>>> +        if (r) { >>>>>>>> +            DRM_ERROR("Failed to create scheduler on ring %s.\n", >>>>>>>> +                  ring->name); >>>>>>>> +            return r; >>>>>>>> +        } >>>>>>>> +    } >>>>>>>> + >>>>>>>> +    return 0; >>>>>>>> +} >>>>>>>> + >>>>>>>> + >>>>>>>>      /** >>>>>>>>       * amdgpu_device_ip_init - run init for hardware IPs >>>>>>>>       * >>>>>>>> @@ -2419,6 +2460,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) >>>>>>>>              } >>>>>>>>          } >>>>>>>>      +    r = amdgpu_device_init_schedulers(adev); >>>>>>>> +    if (r) >>>>>>>> +        goto init_failed; >>>>>>>> + >>>>>>>>          /* Don't init kfd if whole hive need to be reset during init */ >>>>>>>>          if (!adev->gmc.xgmi.pending_reset) >>>>>>>> amdgpu_amdkfd_device_init(adev); >>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c >>>>>>>> index 45977a72b5dd..fa302540c69a 100644 >>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c >>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c >>>>>>>> @@ -457,8 +457,6 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, >>>>>>>>                        atomic_t *sched_score) >>>>>>>>      { >>>>>>>>          struct amdgpu_device *adev = ring->adev; >>>>>>>> -    long timeout; >>>>>>>> -    int r; >>>>>>>>            if (!adev) >>>>>>>>              return -EINVAL; >>>>>>>> @@ -478,36 +476,12 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, >>>>>>>> spin_lock_init(&ring->fence_drv.lock); >>>>>>>>          ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), >>>>>>>>                           GFP_KERNEL); >>>>>>>> -    if (!ring->fence_drv.fences) >>>>>>>> -        return -ENOMEM; >>>>>>>>      -    /* No need to setup the GPU scheduler for rings that don't need it */ >>>>>>>> -    if (ring->no_scheduler) >>>>>>>> -        return 0; >>>>>>>> +    ring->num_hw_submission = num_hw_submission; >>>>>>>> +    ring->sched_score = sched_score; >>>>>>> Let's move this into the caller and then use ring->num_hw_submission in the fence code as well. >>>>>>> >>>>>>> The maximum number of jobs on the ring is not really fence specific. >>>>>>> >>>>>>> Regards, >>>>>>> Christian. >>>>>>> >>>>>>>>      -    switch (ring->funcs->type) { >>>>>>>> -    case AMDGPU_RING_TYPE_GFX: >>>>>>>> -        timeout = adev->gfx_timeout; >>>>>>>> -        break; >>>>>>>> -    case AMDGPU_RING_TYPE_COMPUTE: >>>>>>>> -        timeout = adev->compute_timeout; >>>>>>>> -        break; >>>>>>>> -    case AMDGPU_RING_TYPE_SDMA: >>>>>>>> -        timeout = adev->sdma_timeout; >>>>>>>> -        break; >>>>>>>> -    default: >>>>>>>> -        timeout = adev->video_timeout; >>>>>>>> -        break; >>>>>>>> -    } >>>>>>>> - >>>>>>>> -    r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, >>>>>>>> -               num_hw_submission, amdgpu_job_hang_limit, >>>>>>>> -               timeout, NULL, sched_score, ring->name); >>>>>>>> -    if (r) { >>>>>>>> -        DRM_ERROR("Failed to create scheduler on ring %s.\n", >>>>>>>> -              ring->name); >>>>>>>> -        return r; >>>>>>>> -    } >>>>>>>> +    if (!ring->fence_drv.fences) >>>>>>>> +        return -ENOMEM; >>>>>>>>            return 0; >>>>>>>>      } >>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >>>>>>>> index fae7d185ad0d..7f20ce73a243 100644 >>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >>>>>>>> @@ -251,6 +251,8 @@ struct amdgpu_ring { >>>>>>>>          bool has_compute_vm_bug; >>>>>>>>          bool            no_scheduler; >>>>>>>>          int            hw_prio; >>>>>>>> +    unsigned num_hw_submission; >>>>>>>> +    atomic_t        *sched_score; >>>>>>>>      }; >>>>>>>>        #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) --------------xxLZALHhgsUeHxRAOScsGuS1 Content-Type: text/plain; charset="UTF-8"; name="0001-drm-amd-amdgpu-set-disabled-vcn-to-no_schduler.patch" Content-Disposition: attachment; filename="0001-drm-amd-amdgpu-set-disabled-vcn-to-no_schduler.patch" Content-Transfer-Encoding: base64 RnJvbSBmOGU1M2M3NGNlN2QwOTRhYzE0NjQ4ZTlkYTZiZjQzYjMwOTgzMjNmIE1vbiBTZXAg MTcgMDA6MDA6MDAgMjAwMQpGcm9tOiBKaW5nd2VuIENoZW4gPEppbmd3ZW4uQ2hlbjJAYW1k LmNvbT4KRGF0ZTogV2VkLCAyIE1hciAyMDIyIDE3OjQ0OjM4ICswODAwClN1YmplY3Q6IFtQ QVRDSF0gZHJtL2FtZC9hbWRncHU6IHNldCBkaXNhYmxlZCB2Y24gdG8gbm9fc2NoZHVsZXIK CltXaHldCmFmdGVyIHRoZSByZXNldCBkb21haW4gaW50cm9kdWNlZCwgdGhlIHNjaGVkLnJl YWR5IHdpbGwgYmUgaW5pdCBhZnRlcgpod19pbml0LCB3aGljaCB3aWxsIG92ZXJ3cml0ZSB0 aGUgc2V0dXAgaW4gdmNuIGh3X2luaXQsIGFuZCBsZWFkIHRvCnZjbiBpYiB0ZXN0IGZhaWwu CgpbSG93XQpzZXQgZGlzYWJsZWQgdmNuIHRvIG5vX3NjaGVkdWxlcgoKU2lnbmVkLW9mZi1i eTogSmluZ3dlbiBDaGVuIDxKaW5nd2VuLkNoZW4yQGFtZC5jb20+CkNoYW5nZS1JZDogSTY5 Y2ZkN2I1ZmUwYjlmODZjMjYzYjI5M2RjNjYzYTkzNjhmMDU1YjAKLS0tCiBkcml2ZXJzL2dw dS9kcm0vYW1kL2FtZGdwdS92Y25fdjNfMC5jIHwgMiArKwogMSBmaWxlIGNoYW5nZWQsIDIg aW5zZXJ0aW9ucygrKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1 L3Zjbl92M18wLmMgYi9kcml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdwdS92Y25fdjNfMC5jCmlu ZGV4IGRhMTFjZWJhMDY5OC4uNWI1MTVjYTM2NzQ4IDEwMDY0NAotLS0gYS9kcml2ZXJzL2dw dS9kcm0vYW1kL2FtZGdwdS92Y25fdjNfMC5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9hbWQv YW1kZ3B1L3Zjbl92M18wLmMKQEAgLTI5NSw2ICsyOTUsNyBAQCBzdGF0aWMgaW50IHZjbl92 M18wX2h3X2luaXQodm9pZCAqaGFuZGxlKQogCQkJcmluZyA9ICZhZGV2LT52Y24uaW5zdFtp XS5yaW5nX2RlYzsKIAkJCWlmIChhbWRncHVfdmNuX2lzX2Rpc2FibGVkX3ZjbihhZGV2LCBW Q05fREVDT0RFX1JJTkcsIGkpKSB7CiAJCQkJcmluZy0+c2NoZWQucmVhZHkgPSBmYWxzZTsK KwkJCQlyaW5nLT5ub19zY2hlZHVsZXIgPSB0cnVlOwogCQkJCWRldl9pbmZvKGFkZXYtPmRl diwgInJpbmcgJXMgaXMgZGlzYWJsZWQgYnkgaHlwZXJ2aXNvclxuIiwgcmluZy0+bmFtZSk7 CiAJCQl9IGVsc2UgewogCQkJCXJpbmctPndwdHIgPSAwOwpAQCAtMzA3LDYgKzMwOCw3IEBA IHN0YXRpYyBpbnQgdmNuX3YzXzBfaHdfaW5pdCh2b2lkICpoYW5kbGUpCiAJCQkJcmluZyA9 ICZhZGV2LT52Y24uaW5zdFtpXS5yaW5nX2VuY1tqXTsKIAkJCQlpZiAoYW1kZ3B1X3Zjbl9p c19kaXNhYmxlZF92Y24oYWRldiwgVkNOX0VOQ09ERV9SSU5HLCBpKSkgewogCQkJCQlyaW5n LT5zY2hlZC5yZWFkeSA9IGZhbHNlOworCQkJCQlyaW5nLT5ub19zY2hlZHVsZXIgPSB0cnVl OwogCQkJCQlkZXZfaW5mbyhhZGV2LT5kZXYsICJyaW5nICVzIGlzIGRpc2FibGVkIGJ5IGh5 cGVydmlzb3JcbiIsIHJpbmctPm5hbWUpOwogCQkJCX0gZWxzZSB7CiAJCQkJCXJpbmctPndw dHIgPSAwOwotLSAKMi4zMi4wIChBcHBsZSBHaXQtMTMyKQoK --------------xxLZALHhgsUeHxRAOScsGuS1--