From: Aurabindo Pillai <aurabindo.pillai@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>,
"Wentland, Harry" <Harry.Wentland@amd.com>,
"Kazlauskas, Nicholas" <nicholas.kazlauskas@amd.com>,
"Deucher, Alexander" <alexander.deucher@amd.com>,
"for 3.8" <stable@vger.kernel.org>
Subject: Re: [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states
Date: Thu, 26 Aug 2021 09:34:48 -0400 [thread overview]
Message-ID: <f50a71cf-cf4b-45aa-693e-697f2a139a34@amd.com> (raw)
In-Reply-To: <CADnq5_M+THmHo_-ti=or18cRvBuExdiNcXybVLcVRj2_KfsBuw@mail.gmail.com>
Bug info added and applied, thanks!
On 8/25/21 10:00 PM, Alex Deucher wrote:
> On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai
> <aurabindo.pillai@amd.com> wrote:
>>
>> [Why & How]
>> The DCN3 SoC parameter num_states was calculated but not saved into the
>> object.
>>
>> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
>> Cc: stable@vger.kernel.org
>
> Please add:
> Bug: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1403&data=04%7C01%7Caurabindo.pillai%40amd.com%7C13083d4cd17f491b251608d968355aa9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637655400644887757%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=5OBOO0C%2FszESMd5QEjmRKKRsOM4KiMKFNWz6IdLOipM%3D&reserved=0
> to the series. With that fixed, series is:
> Acked-by: Alex Deucher <alexander.deucher@amd.com>zz
>
>> ---
>> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> index 1333f0541f1b..43ac6f42dd80 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
>> dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
>> }
>>
>> + dcn3_0_soc.num_states = num_states;
>> for (i = 0; i < dcn3_0_soc.num_states; i++) {
>> dcn3_0_soc.clock_limits[i].state = i;
>> dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
>> --
>> 2.30.2
>>
prev parent reply other threads:[~2021-08-26 13:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 2/4] drm/amd/display: Update bounding box states (v2) Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 3/4] drm/amd/display: Remove duplicate dml init Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 4/4] drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box Aurabindo Pillai
2021-08-26 2:00 ` [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Alex Deucher
2021-08-26 13:34 ` Aurabindo Pillai [this message]
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