From: SRINIVASAN SHANMUGAM <srinivasan.shanmugam@amd.com>
To: "Christian König" <christian.koenig@amd.com>,
"Alex Deucher" <alexander.deucher@amd.com>
Cc: amd-gfx@lists.freedesktop.org,
"Felix Kuehling" <felix.kuehling@amd.com>,
"Lancelot Six" <lancelot.six@amd.com>,
"James Zhu" <james.zhu@amd.com>,
"Lijo Lazar" <lijo.lazar@amd.com>,
"Samuel Pitoiset" <hakzsam@gmail.com>,
"Natalie Vock" <natalie.vock@gmx.de>,
"Timur Kristóf" <timur.kristof@gmail.com>,
"Pierre-Eric Pelloux-Prayer" <pierre-eric.pelloux-prayer@amd.com>
Subject: Re: [PATCH 5/7] drm/amdgpu: Make first-level trap state GPUVM-owned
Date: Wed, 14 Oct 2026 14:31:01 +0530 [thread overview]
Message-ID: <fea17c71-c8f8-4e35-abd2-cbe9e2aedf1f@amd.com> (raw)
In-Reply-To: <c7583972-aab5-42dc-a121-e619ce2d2e03@amd.com>
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On 10/12/2026 8:02 PM, Christian König wrote:
> On 10/8/26 09:05, Srinivasan Shanmugam wrote:
>> The first-level trap state belongs to the GPUVM because the TBA and TMA
>> are mappings in that GPUVM.
> Oh, that was actually not what I thought of.
>
> The idea was to use the VM PDs root reservation object to allocate the trap handler and so simplify the handling.
>
> Moving that into the amdgpu_vm structure was not part of this plan. It's not really a page table and so probably better suited in fpriv after all.
>
> On the other hand we want to modify it through the VM IOCTLs and so making it part of the VM is probably not so bad.
>
> I need to think about that a bit more when I have time.
Hi Christian,
Good Morning!
Thanks for your feed backs and reviews, No rush, but when you have some
free time, Just a quick follow up on the trap object ownership discussion.
My thinking was that the trap state is tied to the GPUVM mappings
(TBA/TMA), and queues using the same GPUVM share the same trap state.
Since the control path is also moving through the VM ioctl interface,
keeping the trap object in |amdgpu_vm| felt natural to me.
However, I'm happy to follow whichever approach you think is best in the
long term.
Thanks, Srini
>
> Regards,
> Christian.
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next prev parent reply other threads:[~2026-10-14 9:01 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 7:05 [PATCH 0/7] drm/amdgpu: Add CWSR and second-level trap handler support Srinivasan Shanmugam
2026-10-08 7:05 ` [PATCH 1/7] drm/amdgpu: Add CWSR infrastructure for user queues Srinivasan Shanmugam
2026-10-12 11:47 ` Christian König
2026-10-08 7:05 ` [PATCH 2/7] drm/amdgpu: Integrate CWSR with " Srinivasan Shanmugam
2026-10-12 13:12 ` Christian König
2026-10-08 7:05 ` [PATCH 3/7] drm/amdgpu: Add CWSR userspace interfaces Srinivasan Shanmugam
2026-10-12 13:14 ` Christian König
2026-10-08 7:05 ` [PATCH 4/7] drm/amdgpu: Add second-level trap handler infrastructure Srinivasan Shanmugam
2026-10-12 14:07 ` Christian König
2026-10-08 7:05 ` [PATCH 5/7] drm/amdgpu: Make first-level trap state GPUVM-owned Srinivasan Shanmugam
2026-10-12 14:32 ` Christian König
2026-10-14 9:01 ` SRINIVASAN SHANMUGAM [this message]
2026-10-08 7:05 ` [PATCH 6/7] drm/amdgpu: Program trap TBA/TMA for kernel-managed VMIDs Srinivasan Shanmugam
2026-10-12 15:05 ` Christian König
2026-10-08 7:05 ` [PATCH 7/7] drm/amdgpu/uapi: Add SET/CLEAR L2 TRAP to VM ioctl Srinivasan Shanmugam
2026-10-12 15:10 ` Christian König
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