[PATCH 0/7] DC: don't overclock DCE 6-10 and other fixes

[PATCH 0/7] DC: don't overclock DCE 6-10 and other fixes

[Timur Kristóf]

This series fixes various issues that I found while trying to
get old GPUs with DCE 6 to work well with DC.

The most important part of this series is tweaking how
the engine clock is set on DCE 6-10.

For DCE 6 the maximum according to max_clks_by_state is 600 Mhz,
but dce60_validate_bandwidth sets it to 681 MHz, and then
dce60_update_clocks further increases it by 15%, resulting in
a whopping 783 MHz, which is overall 30% more than what the
hardware was supposed to handle. My Tahiti GPU didn't even boot
with DC enabled with that clock setting.
There is a similar issue with DCE 8-10 too, additionally the
dce80_max_clks_by_state data seems to be incorrect, so I changed
the maximum to 625 MHz for DCE 8-10, which is what the legacy
code uses.

I tested these changes and made sure 4K 60Hz (10 bit) output
still works with them on the following GPUs:

* Tahiti (DCE 6)
* Oland (DCE 6.4)
* Hawaii (DCE 8)
* Tonga, Fiji (DCE 10)

I would appreciate if someone from AMD could confirm what the
maximum display engine clocks for these parts really are.

Other than that, the rest of the series deals with some
ligher problems:

There are patches to fill the display information on DCE 6-10
(previously only filled on DCE 11), such as the first CRTC and
its line time, as well as vblank time, display clock etc.
These are going to be needed for DPM.

It also removes some errors and warnings from the logs which
are caused by the VBIOS on old GPUs reporting some information
differently, namely some VBIOS seem to lack encoder capability
entries for some connectors, as well as the actual amount of
connectors on the GPU not matching the number of entries
reported by the VBIOS.
The DC code base already handles these cases well. They are
not actually errors, so we shouldn't spam the logs with them.

Finally, there is also a fix for set_pixel_clock_v3 which
works slightly differently than the other versions.

Timur Kristóf (7):
  drm/amd/display: Don't overclock DCE 6 by 15%
  drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
  drm/amd/display: Find first CRTC and its line time in
    dce110_fill_display_configs
  drm/amd/display: Fill display clock and vblank time in
    dce110_fill_display_configs
  drm/amd/display: Don't warn when missing DCE encoder caps
  drm/amd/display: Don't print errors for nonexistent connectors
  drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3

 .../gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +--
 .../drm/amd/display/dc/bios/command_table.c   |  2 +-
 .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 14 +++----
 .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 40 +++++++++++--------
 .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 10 ++---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 15 ++++++-
 .../drm/amd/display/dc/dce/dce_link_encoder.c |  8 ++--
 7 files changed, 51 insertions(+), 43 deletions(-)

-- 
2.50.1

[PATCH 1/7] drm/amd/display: Don't overclock DCE 6 by 15%

[Timur Kristóf]

The extra 15% clock was added as a workaround for a Polaris issue
which uses DCE 11, and should not have been used on DCE 6 which
is already hardcoded to the highest possible display clock.
Unfortunately, the extra 15% was mistakenly copied and kept
even on code paths which don't affect Polaris.

This commit fixes that and also adds a check to make sure
not to exceed the maximum DCE 6 display clock.

Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
index 0267644717b2..cfd7309f2c6a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
@@ -123,11 +123,9 @@ static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
 {
 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	struct dm_pp_power_level_change_request level_change_req;
-	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
-
-	/*TODO: W/A for dal3 linux, investigate why this works */
-	if (!clk_mgr_dce->dfs_bypass_active)
-		patched_disp_clk = patched_disp_clk * 115 / 100;
+	const int max_disp_clk =
+		clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
+	int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
 
 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
 	/* get max clock state from PPLIB */
-- 
2.50.1

[PATCH 2/7] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%

[Timur Kristóf]

Adjust the nominal (and performance) clocks for DCE 8-10,
and set them to 625 MHz, which is the value used by the legacy
display code in amdgpu_atombios_get_clock_info.

This was tested with Hawaii, Tonga and Fiji.
These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.

The extra 15% clock was added as a workaround for a Polaris issue
which uses DCE 11, and should not have been used on DCE 8-10 which
are already hardcoded to the highest possible display clock.
Unfortunately, the extra 15% was mistakenly copied and kept
even on code paths which don't affect Polaris.

This commit fixes that and also	adds a check to	make sure
not to exceed the maximum DCE 8-10 display clock.

Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

x
---
 .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 26feefbb8990..69e9540f553b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
 /* ClocksStateLow */
 { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
 /* ClocksStateNominal */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
+{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
 /* ClocksStatePerformance */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
+{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
 
 int dentist_get_divider_from_did(int did)
 {
@@ -400,11 +400,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
 {
 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	struct dm_pp_power_level_change_request level_change_req;
-	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
-
-	/*TODO: W/A for dal3 linux, investigate why this works */
-	if (!clk_mgr_dce->dfs_bypass_active)
-		patched_disp_clk = patched_disp_clk * 115 / 100;
+	const int max_disp_clk =
+		clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
+	int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
 
 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
 	/* get max clock state from PPLIB */
-- 
2.50.1

[PATCH 3/7] drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs

[Timur Kristóf]

dce110_fill_display_configs is shared between DCE 6-11, and
finding the first CRTC and its line time is relevant to DCE 6 too.
Move the code to find it from DCE 11 specific code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 30 ++++++++++++-------
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index f8409453434c..baeac8f1c04f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -120,9 +120,12 @@ void dce110_fill_display_configs(
 	const struct dc_state *context,
 	struct dm_pp_display_configuration *pp_display_cfg)
 {
+	struct dc *dc = context->clk_mgr->ctx->dc;
 	int j;
 	int num_cfgs = 0;
 
+	pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
+
 	for (j = 0; j < context->stream_count; j++) {
 		int k;
 
@@ -164,6 +167,23 @@ void dce110_fill_display_configs(
 		cfg->v_refresh /= stream->timing.h_total;
 		cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
 							/ stream->timing.v_total;
+
+		/* Find first CRTC index and calculate its line time.
+		 * This is necessary for DPM on SI GPUs.
+		 */
+		if (cfg->pipe_idx < pp_display_cfg->crtc_index) {
+			const struct dc_crtc_timing *timing =
+				&context->streams[0]->timing;
+
+			pp_display_cfg->crtc_index = cfg->pipe_idx;
+			pp_display_cfg->line_time_in_us =
+				timing->h_total * 10000 / timing->pix_clk_100hz;
+		}
+	}
+
+	if (!num_cfgs) {
+		pp_display_cfg->crtc_index = 0;
+		pp_display_cfg->line_time_in_us = 0;
 	}
 
 	pp_display_cfg->display_count = num_cfgs;
@@ -232,16 +252,6 @@ void dce11_pplib_apply_display_requirements(
 
 	dce110_fill_display_configs(context, pp_display_cfg);
 
-	/* TODO: is this still applicable?*/
-	if (pp_display_cfg->display_count == 1) {
-		const struct dc_crtc_timing *timing =
-			&context->streams[0]->timing;
-
-		pp_display_cfg->crtc_index =
-			pp_display_cfg->disp_configs[0].pipe_idx;
-		pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
-	}
-
 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
 		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
 }
-- 
2.50.1

[PATCH 4/7] drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs

[Timur Kristóf]

Also needed by DCE 6.
This way the code that gathers this info can be shared between
different DCE versions and doesn't have to be repeated.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c    |  2 --
 .../drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 10 +++-------
 .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c   |  2 --
 3 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 69e9540f553b..17a8b46b0818 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -386,8 +386,6 @@ static void dce_pplib_apply_display_requirements(
 {
 	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
 
-	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
-
 	dce110_fill_display_configs(context, pp_display_cfg);
 
 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index baeac8f1c04f..13cf415e38e5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -124,6 +124,9 @@ void dce110_fill_display_configs(
 	int j;
 	int num_cfgs = 0;
 
+	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
+	pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
+	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
 	pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
 
 	for (j = 0; j < context->stream_count; j++) {
@@ -243,13 +246,6 @@ void dce11_pplib_apply_display_requirements(
 	pp_display_cfg->min_engine_clock_deep_sleep_khz
 			= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
 
-	pp_display_cfg->avail_mclk_switch_time_us =
-						dce110_get_min_vblank_time_us(context);
-	/* TODO: dce11.2*/
-	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
-
-	pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
-
 	dce110_fill_display_configs(context, pp_display_cfg);
 
 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
index cfd7309f2c6a..7044b437fe9d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
@@ -109,8 +109,6 @@ static void dce60_pplib_apply_display_requirements(
 {
 	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
 
-	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
-
 	dce110_fill_display_configs(context, pp_display_cfg);
 
 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
-- 
2.50.1

[PATCH 5/7] drm/amd/display: Don't warn when missing DCE encoder caps

[Timur Kristóf]

On some GPUs the VBIOS just doesn't have encoder caps,
or maybe not for every encoder.

This isn't really a problem and it's handled well,
so let's not litter the logs with it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 4a9d07c31bc5..0c50fe266c8a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -896,13 +896,13 @@ void dce110_link_encoder_construct(
 						enc110->base.id, &bp_cap_info);
 
 	/* Override features with DCE-specific values */
-	if (BP_RESULT_OK == result) {
+	if (result == BP_RESULT_OK) {
 		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
 				bp_cap_info.DP_HBR2_EN;
 		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 				bp_cap_info.DP_HBR3_EN;
 		enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
-	} else {
+	} else if (result != BP_RESULT_NORECORD) {
 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 				__func__,
 				result);
@@ -1798,13 +1798,13 @@ void dce60_link_encoder_construct(
 						enc110->base.id, &bp_cap_info);
 
 	/* Override features with DCE-specific values */
-	if (BP_RESULT_OK == result) {
+	if (result == BP_RESULT_OK) {
 		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
 				bp_cap_info.DP_HBR2_EN;
 		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 				bp_cap_info.DP_HBR3_EN;
 		enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
-	} else {
+	} else if (result != BP_RESULT_NORECORD) {
 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 				__func__,
 				result);
-- 
2.50.1

[PATCH 6/7] drm/amd/display: Don't print errors for nonexistent connectors

[Timur Kristóf]

When getting the number of connectors, the VBIOS reports
the number of valid indices, but it doesn't say which indices
are valid, and not every valid index has an actual connector.
If we don't find a connector on an index, that is not an error.

Considering these are not actual errors, don't litter the logs.

Fixes: 60df5628144b ("drm/amd/display: handle invalid connector indices")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +----
 drivers/gpu/drm/amd/display/dc/core/dc.c          | 15 ++++++++++++++-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 67f08495b7e6..154fd2c18e88 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -174,11 +174,8 @@ static struct graphics_object_id bios_parser_get_connector_id(
 		return object_id;
 	}
 
-	if (tbl->ucNumberOfObjects <= i) {
-		dm_error("Can't find connector id %d in connector table of size %d.\n",
-			 i, tbl->ucNumberOfObjects);
+	if (tbl->ucNumberOfObjects <= i)
 		return object_id;
-	}
 
 	id = le16_to_cpu(tbl->asObjects[i].usObjectID);
 	object_id = object_id_from_bios_object_id(id);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cf3893a2f8ce..33d6a5116aad 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -217,11 +217,24 @@ static bool create_links(
 		connectors_num,
 		num_virtual_links);
 
-	// condition loop on link_count to allow skipping invalid indices
+	/* When getting the number of connectors, the VBIOS reports the number of valid indices,
+	 * but it doesn't say which indices are valid, and not every index has an actual connector.
+	 * So, if we don't find a connector on an index, that is not an error.
+	 *
+	 * - There is no guarantee that the first N indices will be valid
+	 * - VBIOS may report a higher amount of valid indices than there are actual connectors
+	 * - Some VBIOS have valid configurations for more connectors than there actually are
+	 *   on the card. This may be because the manufacturer used the same VBIOS for different
+	 *   variants of the same card.
+	 */
 	for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
+		struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);
 		struct link_init_data link_init_params = {0};
 		struct dc_link *link;
 
+		if (connector_id.id == CONNECTOR_ID_UNKNOWN)
+			continue;
+
 		DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 
 		link_init_params.ctx = dc->ctx;
-- 
2.50.1

[PATCH 7/7] drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3

[Timur Kristóf]

For later VBIOS versions, the fractional feedback divider is
calculated as the remainder of dividing the feedback divider by
a factor, which is set to 1000000. For reference, see:
- calculate_fb_and_fractional_fb_divider
- calc_pll_max_vco_construct

However, in case of old VBIOS versions that have
set_pixel_clock_v3, they only have 1 byte available for the
fractional feedback divider, and it's expected to be set to the
remainder from dividing the feedback divider by 10.
For reference see the legacy display code:
- amdgpu_pll_compute
- amdgpu_atombios_crtc_program_pll

This commit fixes set_pixel_clock_v3 by dividing the fractional
feedback divider passed to the function by 100000.

Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 2bcae0643e61..58e88778da7f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3(
 	allocation.sPCLKInput.usFbDiv =
 			cpu_to_le16((uint16_t)bp_params->feedback_divider);
 	allocation.sPCLKInput.ucFracFbDiv =
-			(uint8_t)bp_params->fractional_feedback_divider;
+			(uint8_t)(bp_params->fractional_feedback_divider / 100000);
 	allocation.sPCLKInput.ucPostDiv =
 			(uint8_t)bp_params->pixel_clock_post_divider;
 
-- 
2.50.1

Re: [PATCH 1/7] drm/amd/display: Don't overclock DCE 6 by 15%

[Alex Deucher]

On Thu, Jul 31, 2025 at 5:44 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> The extra 15% clock was added as a workaround for a Polaris issue
> which uses DCE 11, and should not have been used on DCE 6 which
> is already hardcoded to the highest possible display clock.
> Unfortunately, the extra 15% was mistakenly copied and kept
> even on code paths which don't affect Polaris.
>
> This commit fixes that and also adds a check to make sure
> not to exceed the maximum DCE 6 display clock.
>
> Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
> Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> index 0267644717b2..cfd7309f2c6a 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> @@ -123,11 +123,9 @@ static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
>  {
>         struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>         struct dm_pp_power_level_change_request level_change_req;
> -       int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> -       /*TODO: W/A for dal3 linux, investigate why this works */
> -       if (!clk_mgr_dce->dfs_bypass_active)
> -               patched_disp_clk = patched_disp_clk * 115 / 100;
> +       const int max_disp_clk =
> +               clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> +       int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
>
>         level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
>         /* get max clock state from PPLIB */
> --
> 2.50.1
>

Re: [PATCH 2/7] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%

[Alex Deucher]

On Thu, Jul 31, 2025 at 5:58 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> Adjust the nominal (and performance) clocks for DCE 8-10,
> and set them to 625 MHz, which is the value used by the legacy
> display code in amdgpu_atombios_get_clock_info.
>
> This was tested with Hawaii, Tonga and Fiji.
> These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.
>
> The extra 15% clock was added as a workaround for a Polaris issue
> which uses DCE 11, and should not have been used on DCE 8-10 which
> are already hardcoded to the highest possible display clock.
> Unfortunately, the extra 15% was mistakenly copied and kept
> even on code paths which don't affect Polaris.
>
> This commit fixes that and also adds a check to make sure
> not to exceed the maximum DCE 8-10 display clock.
>
> Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
> Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
>
> x

Stray x here.  with that fixed:
Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 26feefbb8990..69e9540f553b 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
>  /* ClocksStateLow */
>  { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
>  /* ClocksStateNominal */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
>  /* ClocksStatePerformance */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
>
>  int dentist_get_divider_from_did(int did)
>  {
> @@ -400,11 +400,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
>  {
>         struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>         struct dm_pp_power_level_change_request level_change_req;
> -       int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> -       /*TODO: W/A for dal3 linux, investigate why this works */
> -       if (!clk_mgr_dce->dfs_bypass_active)
> -               patched_disp_clk = patched_disp_clk * 115 / 100;
> +       const int max_disp_clk =
> +               clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> +       int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
>
>         level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
>         /* get max clock state from PPLIB */
> --
> 2.50.1
>

Re: [PATCH 3/7] drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs

[Alex Deucher]

On Thu, Jul 31, 2025 at 6:03 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> dce110_fill_display_configs is shared between DCE 6-11, and
> finding the first CRTC and its line time is relevant to DCE 6 too.
> Move the code to find it from DCE 11 specific code.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 30 ++++++++++++-------
>  1 file changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> index f8409453434c..baeac8f1c04f 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> @@ -120,9 +120,12 @@ void dce110_fill_display_configs(
>         const struct dc_state *context,
>         struct dm_pp_display_configuration *pp_display_cfg)
>  {
> +       struct dc *dc = context->clk_mgr->ctx->dc;
>         int j;
>         int num_cfgs = 0;
>
> +       pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
> +
>         for (j = 0; j < context->stream_count; j++) {
>                 int k;
>
> @@ -164,6 +167,23 @@ void dce110_fill_display_configs(
>                 cfg->v_refresh /= stream->timing.h_total;
>                 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
>                                                         / stream->timing.v_total;
> +
> +               /* Find first CRTC index and calculate its line time.
> +                * This is necessary for DPM on SI GPUs.
> +                */
> +               if (cfg->pipe_idx < pp_display_cfg->crtc_index) {
> +                       const struct dc_crtc_timing *timing =
> +                               &context->streams[0]->timing;
> +
> +                       pp_display_cfg->crtc_index = cfg->pipe_idx;
> +                       pp_display_cfg->line_time_in_us =
> +                               timing->h_total * 10000 / timing->pix_clk_100hz;
> +               }
> +       }
> +
> +       if (!num_cfgs) {
> +               pp_display_cfg->crtc_index = 0;
> +               pp_display_cfg->line_time_in_us = 0;
>         }
>
>         pp_display_cfg->display_count = num_cfgs;
> @@ -232,16 +252,6 @@ void dce11_pplib_apply_display_requirements(
>
>         dce110_fill_display_configs(context, pp_display_cfg);
>
> -       /* TODO: is this still applicable?*/
> -       if (pp_display_cfg->display_count == 1) {
> -               const struct dc_crtc_timing *timing =
> -                       &context->streams[0]->timing;
> -
> -               pp_display_cfg->crtc_index =
> -                       pp_display_cfg->disp_configs[0].pipe_idx;
> -               pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
> -       }
> -
>         if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
>                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
>  }
> --
> 2.50.1
>

Re: [PATCH 4/7] drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs

[Alex Deucher]

On Thu, Jul 31, 2025 at 5:53 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> Also needed by DCE 6.
> This way the code that gathers this info can be shared between
> different DCE versions and doesn't have to be repeated.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c    |  2 --
>  .../drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 10 +++-------
>  .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c   |  2 --
>  3 files changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 69e9540f553b..17a8b46b0818 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -386,8 +386,6 @@ static void dce_pplib_apply_display_requirements(
>  {
>         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
>
> -       pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
> -
>         dce110_fill_display_configs(context, pp_display_cfg);
>
>         if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> index baeac8f1c04f..13cf415e38e5 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> @@ -124,6 +124,9 @@ void dce110_fill_display_configs(
>         int j;
>         int num_cfgs = 0;
>
> +       pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
> +       pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
> +       pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
>         pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
>
>         for (j = 0; j < context->stream_count; j++) {
> @@ -243,13 +246,6 @@ void dce11_pplib_apply_display_requirements(
>         pp_display_cfg->min_engine_clock_deep_sleep_khz
>                         = context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
>
> -       pp_display_cfg->avail_mclk_switch_time_us =
> -                                               dce110_get_min_vblank_time_us(context);
> -       /* TODO: dce11.2*/
> -       pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
> -
> -       pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
> -
>         dce110_fill_display_configs(context, pp_display_cfg);
>
>         if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> index cfd7309f2c6a..7044b437fe9d 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> @@ -109,8 +109,6 @@ static void dce60_pplib_apply_display_requirements(
>  {
>         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
>
> -       pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
> -
>         dce110_fill_display_configs(context, pp_display_cfg);
>
>         if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
> --
> 2.50.1
>

Re: [PATCH 5/7] drm/amd/display: Don't warn when missing DCE encoder caps

[Alex Deucher]

On Thu, Jul 31, 2025 at 5:53 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On some GPUs the VBIOS just doesn't have encoder caps,
> or maybe not for every encoder.
>
> This isn't really a problem and it's handled well,
> so let's not litter the logs with it.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> index 4a9d07c31bc5..0c50fe266c8a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> @@ -896,13 +896,13 @@ void dce110_link_encoder_construct(
>                                                 enc110->base.id, &bp_cap_info);
>
>         /* Override features with DCE-specific values */
> -       if (BP_RESULT_OK == result) {
> +       if (result == BP_RESULT_OK) {
>                 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
>                                 bp_cap_info.DP_HBR2_EN;
>                 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
>                                 bp_cap_info.DP_HBR3_EN;
>                 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
> -       } else {
> +       } else if (result != BP_RESULT_NORECORD) {
>                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
>                                 __func__,
>                                 result);
> @@ -1798,13 +1798,13 @@ void dce60_link_encoder_construct(
>                                                 enc110->base.id, &bp_cap_info);
>
>         /* Override features with DCE-specific values */
> -       if (BP_RESULT_OK == result) {
> +       if (result == BP_RESULT_OK) {
>                 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
>                                 bp_cap_info.DP_HBR2_EN;
>                 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
>                                 bp_cap_info.DP_HBR3_EN;
>                 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
> -       } else {
> +       } else if (result != BP_RESULT_NORECORD) {
>                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
>                                 __func__,
>                                 result);
> --
> 2.50.1
>

Re: [PATCH 6/7] drm/amd/display: Don't print errors for nonexistent connectors

[Alex Deucher]

On Thu, Jul 31, 2025 at 2:03 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> When getting the number of connectors, the VBIOS reports
> the number of valid indices, but it doesn't say which indices
> are valid, and not every valid index has an actual connector.
> If we don't find a connector on an index, that is not an error.
>
> Considering these are not actual errors, don't litter the logs.
>
> Fixes: 60df5628144b ("drm/amd/display: handle invalid connector indices")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +----
>  drivers/gpu/drm/amd/display/dc/core/dc.c          | 15 ++++++++++++++-
>  2 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> index 67f08495b7e6..154fd2c18e88 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> @@ -174,11 +174,8 @@ static struct graphics_object_id bios_parser_get_connector_id(
>                 return object_id;
>         }
>
> -       if (tbl->ucNumberOfObjects <= i) {
> -               dm_error("Can't find connector id %d in connector table of size %d.\n",
> -                        i, tbl->ucNumberOfObjects);
> +       if (tbl->ucNumberOfObjects <= i)
>                 return object_id;
> -       }
>
>         id = le16_to_cpu(tbl->asObjects[i].usObjectID);
>         object_id = object_id_from_bios_object_id(id);
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index cf3893a2f8ce..33d6a5116aad 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -217,11 +217,24 @@ static bool create_links(
>                 connectors_num,
>                 num_virtual_links);
>
> -       // condition loop on link_count to allow skipping invalid indices
> +       /* When getting the number of connectors, the VBIOS reports the number of valid indices,
> +        * but it doesn't say which indices are valid, and not every index has an actual connector.
> +        * So, if we don't find a connector on an index, that is not an error.
> +        *
> +        * - There is no guarantee that the first N indices will be valid
> +        * - VBIOS may report a higher amount of valid indices than there are actual connectors
> +        * - Some VBIOS have valid configurations for more connectors than there actually are
> +        *   on the card. This may be because the manufacturer used the same VBIOS for different
> +        *   variants of the same card.
> +        */
>         for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
> +               struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);
>                 struct link_init_data link_init_params = {0};
>                 struct dc_link *link;
>
> +               if (connector_id.id == CONNECTOR_ID_UNKNOWN)
> +                       continue;
> +
>                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
>
>                 link_init_params.ctx = dc->ctx;
> --
> 2.50.1
>

Re: [PATCH 7/7] drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3

[Alex Deucher]

On Thu, Jul 31, 2025 at 5:53 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> For later VBIOS versions, the fractional feedback divider is
> calculated as the remainder of dividing the feedback divider by
> a factor, which is set to 1000000. For reference, see:
> - calculate_fb_and_fractional_fb_divider
> - calc_pll_max_vco_construct
>
> However, in case of old VBIOS versions that have
> set_pixel_clock_v3, they only have 1 byte available for the
> fractional feedback divider, and it's expected to be set to the
> remainder from dividing the feedback divider by 10.
> For reference see the legacy display code:
> - amdgpu_pll_compute
> - amdgpu_atombios_crtc_program_pll
>
> This commit fixes set_pixel_clock_v3 by dividing the fractional
> feedback divider passed to the function by 100000.
>
> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> index 2bcae0643e61..58e88778da7f 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> @@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3(
>         allocation.sPCLKInput.usFbDiv =
>                         cpu_to_le16((uint16_t)bp_params->feedback_divider);
>         allocation.sPCLKInput.ucFracFbDiv =
> -                       (uint8_t)bp_params->fractional_feedback_divider;
> +                       (uint8_t)(bp_params->fractional_feedback_divider / 100000);
>         allocation.sPCLKInput.ucPostDiv =
>                         (uint8_t)bp_params->pixel_clock_post_divider;
>
> --
> 2.50.1
>

Re: [PATCH 2/7] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%

[Timur Kristóf]

On Mon, 2025-08-04 at 11:56 -0400, Alex Deucher wrote:
> On Thu, Jul 31, 2025 at 5:58 AM Timur Kristóf
> <timur.kristof@gmail.com> wrote:
> > 
> > Adjust the nominal (and performance) clocks for DCE 8-10,
> > and set them to 625 MHz, which is the value used by the legacy
> > display code in amdgpu_atombios_get_clock_info.
> > 
> > This was tested with Hawaii, Tonga and Fiji.
> > These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.
> > 
> > The extra 15% clock was added as a workaround for a Polaris issue
> > which uses DCE 11, and should not have been used on DCE 8-10 which
> > are already hardcoded to the highest possible display clock.
> > Unfortunately, the extra 15% was mistakenly copied and kept
> > even on code paths which don't affect Polaris.
> > 
> > This commit fixes that and also adds a check to make sure
> > not to exceed the maximum DCE 8-10 display clock.
> > 
> > Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for
> > Polaris")
> > Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > 
> > x
> 
> Stray x here.  with that fixed:
> Acked-by: Alex Deucher <alexander.deucher@amd.com>

Thanks!
Sorry about that, that's a typo that I made during a rebase.

Maybe a silly question but what is the right way to deal with it?
Should I send the entire series or just the patch with the typo fixed?
Or can you just delete the typo when you are applying it to your tree?

Timur

> 
> > ---
> >  .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 12 +++++---
> > ----
> >  1 file changed, 5 insertions(+), 7 deletions(-)
> > 
> > diff --git
> > a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > index 26feefbb8990..69e9540f553b 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > @@ -72,9 +72,9 @@ static const struct state_dependent_clocks
> > dce80_max_clks_by_state[] = {
> >  /* ClocksStateLow */
> >  { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> >  /* ClocksStateNominal */
> > -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> > +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
> >  /* ClocksStatePerformance */
> > -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> > +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
> > 
> >  int dentist_get_divider_from_did(int did)
> >  {
> > @@ -400,11 +400,9 @@ static void dce_update_clocks(struct clk_mgr
> > *clk_mgr_base,
> >  {
> >         struct clk_mgr_internal *clk_mgr_dce =
> > TO_CLK_MGR_INTERNAL(clk_mgr_base);
> >         struct dm_pp_power_level_change_request level_change_req;
> > -       int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> > -
> > -       /*TODO: W/A for dal3 linux, investigate why this works */
> > -       if (!clk_mgr_dce->dfs_bypass_active)
> > -               patched_disp_clk = patched_disp_clk * 115 / 100;
> > +       const int max_disp_clk =
> > +               clk_mgr_dce-
> > >max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> > +       int patched_disp_clk = MIN(max_disp_clk, context-
> > >bw_ctx.bw.dce.dispclk_khz);
> > 
> >         level_change_req.power_level =
> > dce_get_required_clocks_state(clk_mgr_base, context);
> >         /* get max clock state from PPLIB */
> > --
> > 2.50.1
> > 

Re: [PATCH 2/7] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%

[Alex Deucher]

On Mon, Aug 4, 2025 at 12:35 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On Mon, 2025-08-04 at 11:56 -0400, Alex Deucher wrote:
> > On Thu, Jul 31, 2025 at 5:58 AM Timur Kristóf
> > <timur.kristof@gmail.com> wrote:
> > >
> > > Adjust the nominal (and performance) clocks for DCE 8-10,
> > > and set them to 625 MHz, which is the value used by the legacy
> > > display code in amdgpu_atombios_get_clock_info.
> > >
> > > This was tested with Hawaii, Tonga and Fiji.
> > > These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.
> > >
> > > The extra 15% clock was added as a workaround for a Polaris issue
> > > which uses DCE 11, and should not have been used on DCE 8-10 which
> > > are already hardcoded to the highest possible display clock.
> > > Unfortunately, the extra 15% was mistakenly copied and kept
> > > even on code paths which don't affect Polaris.
> > >
> > > This commit fixes that and also adds a check to make sure
> > > not to exceed the maximum DCE 8-10 display clock.
> > >
> > > Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for
> > > Polaris")
> > > Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> > > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > >
> > > x
> >
> > Stray x here.  with that fixed:
> > Acked-by: Alex Deucher <alexander.deucher@amd.com>
>
> Thanks!
> Sorry about that, that's a typo that I made during a rebase.
>
> Maybe a silly question but what is the right way to deal with it?
> Should I send the entire series or just the patch with the typo fixed?
> Or can you just delete the typo when you are applying it to your tree?

If you end up resending the series, you can fix it then.  If not, I
can fix it up when I apply the patches.  I wanted to give it a few
more days so the display guys have a chance to review them.

Alex

>
> Timur
>
> >
> > > ---
> > >  .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 12 +++++---
> > > ----
> > >  1 file changed, 5 insertions(+), 7 deletions(-)
> > >
> > > diff --git
> > > a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > > index 26feefbb8990..69e9540f553b 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > > @@ -72,9 +72,9 @@ static const struct state_dependent_clocks
> > > dce80_max_clks_by_state[] = {
> > >  /* ClocksStateLow */
> > >  { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> > >  /* ClocksStateNominal */
> > > -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> > > +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
> > >  /* ClocksStatePerformance */
> > > -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> > > +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
> > >
> > >  int dentist_get_divider_from_did(int did)
> > >  {
> > > @@ -400,11 +400,9 @@ static void dce_update_clocks(struct clk_mgr
> > > *clk_mgr_base,
> > >  {
> > >         struct clk_mgr_internal *clk_mgr_dce =
> > > TO_CLK_MGR_INTERNAL(clk_mgr_base);
> > >         struct dm_pp_power_level_change_request level_change_req;
> > > -       int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> > > -
> > > -       /*TODO: W/A for dal3 linux, investigate why this works */
> > > -       if (!clk_mgr_dce->dfs_bypass_active)
> > > -               patched_disp_clk = patched_disp_clk * 115 / 100;
> > > +       const int max_disp_clk =
> > > +               clk_mgr_dce-
> > > >max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> > > +       int patched_disp_clk = MIN(max_disp_clk, context-
> > > >bw_ctx.bw.dce.dispclk_khz);
> > >
> > >         level_change_req.power_level =
> > > dce_get_required_clocks_state(clk_mgr_base, context);
> > >         /* get max clock state from PPLIB */
> > > --
> > > 2.50.1
> > >

Re: [PATCH 0/7] DC: don't overclock DCE 6-10 and other fixes

[Timur Kristóf]

Hi Harry & Daniel,

I apologize, I just realized that I forgot to copy you directly on
these series. Can you please take a look and review?

DC: don't overclock DCE 6-10 and other fixes
https://lists.freedesktop.org/archives/amd-gfx/2025-July/128002.html

drm/amd/display: Fix DP audio DTO1 clock source on DCE 6.
https://lists.freedesktop.org/archives/amd-gfx/2025-August/128101.html

DC: Fix page flip timeouts on DCE 6
https://lists.freedesktop.org/archives/amd-gfx/2025-August/128102.html


Thanks & best regards,
Timur

On Thu, 2025-07-31 at 11:43 +0200, Timur Kristóf wrote:
> This series fixes various issues that I found while trying to
> get old GPUs with DCE 6 to work well with DC.
> 
> The most important part of this series is tweaking how
> the engine clock is set on DCE 6-10.
> 
> For DCE 6 the maximum according to max_clks_by_state is 600 Mhz,
> but dce60_validate_bandwidth sets it to 681 MHz, and then
> dce60_update_clocks further increases it by 15%, resulting in
> a whopping 783 MHz, which is overall 30% more than what the
> hardware was supposed to handle. My Tahiti GPU didn't even boot
> with DC enabled with that clock setting.
> There is a similar issue with DCE 8-10 too, additionally the
> dce80_max_clks_by_state data seems to be incorrect, so I changed
> the maximum to 625 MHz for DCE 8-10, which is what the legacy
> code uses.
> 
> I tested these changes and made sure 4K 60Hz (10 bit) output
> still works with them on the following GPUs:
> 
> * Tahiti (DCE 6)
> * Oland (DCE 6.4)
> * Hawaii (DCE 8)
> * Tonga, Fiji (DCE 10)
> 
> I would appreciate if someone from AMD could confirm what the
> maximum display engine clocks for these parts really are.
> 
> Other than that, the rest of the series deals with some
> ligher problems:
> 
> There are patches to fill the display information on DCE 6-10
> (previously only filled on DCE 11), such as the first CRTC and
> its line time, as well as vblank time, display clock etc.
> These are going to be needed for DPM.
> 
> It also removes some errors and warnings from the logs which
> are caused by the VBIOS on old GPUs reporting some information
> differently, namely some VBIOS seem to lack encoder capability
> entries for some connectors, as well as the actual amount of
> connectors on the GPU not matching the number of entries
> reported by the VBIOS.
> The DC code base already handles these cases well. They are
> not actually errors, so we shouldn't spam the logs with them.
> 
> Finally, there is also a fix for set_pixel_clock_v3 which
> works slightly differently than the other versions.
> 
> Timur Kristóf (7):
>   drm/amd/display: Don't overclock DCE 6 by 15%
>   drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
>   drm/amd/display: Find first CRTC and its line time in
>     dce110_fill_display_configs
>   drm/amd/display: Fill display clock and vblank time in
>     dce110_fill_display_configs
>   drm/amd/display: Don't warn when missing DCE encoder caps
>   drm/amd/display: Don't print errors for nonexistent connectors
>   drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3
> 
>  .../gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +--
>  .../drm/amd/display/dc/bios/command_table.c   |  2 +-
>  .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 14 +++----
>  .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 40 +++++++++++------
> --
>  .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 10 ++---
>  drivers/gpu/drm/amd/display/dc/core/dc.c      | 15 ++++++-
>  .../drm/amd/display/dc/dce/dce_link_encoder.c |  8 ++--
>  7 files changed, 51 insertions(+), 43 deletions(-)

Re: [PATCH 1/7] drm/amd/display: Don't overclock DCE 6 by 15%

[Rodrigo Siqueira]

On 07/31, Timur Kristóf wrote:
> The extra 15% clock was added as a workaround for a Polaris issue
> which uses DCE 11, and should not have been used on DCE 6 which
> is already hardcoded to the highest possible display clock.
> Unfortunately, the extra 15% was mistakenly copied and kept
> even on code paths which don't affect Polaris.
> 
> This commit fixes that and also adds a check to make sure
> not to exceed the maximum DCE 6 display clock.
> 
> Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
> Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  .../gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> index 0267644717b2..cfd7309f2c6a 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> @@ -123,11 +123,9 @@ static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
>  {
>  	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>  	struct dm_pp_power_level_change_request level_change_req;
> -	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> -	/*TODO: W/A for dal3 linux, investigate why this works */
> -	if (!clk_mgr_dce->dfs_bypass_active)
> -		patched_disp_clk = patched_disp_clk * 115 / 100;
> +	const int max_disp_clk =
> +		clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> +	int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
>  
>  	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
>  	/* get max clock state from PPLIB */
> -- 
> 2.50.1
>

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> 

-- 
Rodrigo Siqueira

Re: [PATCH 2/7] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%

[Rodrigo Siqueira]

On 07/31, Timur Kristóf wrote:
> Adjust the nominal (and performance) clocks for DCE 8-10,
> and set them to 625 MHz, which is the value used by the legacy
> display code in amdgpu_atombios_get_clock_info.
> 
> This was tested with Hawaii, Tonga and Fiji.
> These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.
> 
> The extra 15% clock was added as a workaround for a Polaris issue
> which uses DCE 11, and should not have been used on DCE 8-10 which
> are already hardcoded to the highest possible display clock.
> Unfortunately, the extra 15% was mistakenly copied and kept
> even on code paths which don't affect Polaris.
> 
> This commit fixes that and also	adds a check to	make sure
> not to exceed the maximum DCE 8-10 display clock.
> 
> Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
> Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> 
> x
> ---
>  .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 26feefbb8990..69e9540f553b 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
>  /* ClocksStateLow */
>  { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
>  /* ClocksStateNominal */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
>  /* ClocksStatePerformance */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
>  
>  int dentist_get_divider_from_did(int did)
>  {
> @@ -400,11 +400,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
>  {
>  	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>  	struct dm_pp_power_level_change_request level_change_req;
> -	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> -	/*TODO: W/A for dal3 linux, investigate why this works */
> -	if (!clk_mgr_dce->dfs_bypass_active)
> -		patched_disp_clk = patched_disp_clk * 115 / 100;
> +	const int max_disp_clk =
> +		clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> +	int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
>  
>  	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
>  	/* get max clock state from PPLIB */
> -- 
> 2.50.1
>

Very nice patch.

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> 

-- 
Rodrigo Siqueira

Re: [PATCH 3/7] drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs

[Rodrigo Siqueira]

On 07/31, Timur Kristóf wrote:
> dce110_fill_display_configs is shared between DCE 6-11, and
> finding the first CRTC and its line time is relevant to DCE 6 too.
> Move the code to find it from DCE 11 specific code.
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 30 ++++++++++++-------
>  1 file changed, 20 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> index f8409453434c..baeac8f1c04f 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> @@ -120,9 +120,12 @@ void dce110_fill_display_configs(
>  	const struct dc_state *context,
>  	struct dm_pp_display_configuration *pp_display_cfg)
>  {
> +	struct dc *dc = context->clk_mgr->ctx->dc;
>  	int j;
>  	int num_cfgs = 0;
>  
> +	pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
> +
>  	for (j = 0; j < context->stream_count; j++) {
>  		int k;
>  
> @@ -164,6 +167,23 @@ void dce110_fill_display_configs(
>  		cfg->v_refresh /= stream->timing.h_total;
>  		cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
>  							/ stream->timing.v_total;
> +
> +		/* Find first CRTC index and calculate its line time.
> +		 * This is necessary for DPM on SI GPUs.
> +		 */
> +		if (cfg->pipe_idx < pp_display_cfg->crtc_index) {
> +			const struct dc_crtc_timing *timing =
> +				&context->streams[0]->timing;
> +
> +			pp_display_cfg->crtc_index = cfg->pipe_idx;
> +			pp_display_cfg->line_time_in_us =
> +				timing->h_total * 10000 / timing->pix_clk_100hz;
> +		}
> +	}
> +
> +	if (!num_cfgs) {
> +		pp_display_cfg->crtc_index = 0;
> +		pp_display_cfg->line_time_in_us = 0;
>  	}
>  
>  	pp_display_cfg->display_count = num_cfgs;
> @@ -232,16 +252,6 @@ void dce11_pplib_apply_display_requirements(
>  
>  	dce110_fill_display_configs(context, pp_display_cfg);
>  
> -	/* TODO: is this still applicable?*/
> -	if (pp_display_cfg->display_count == 1) {
> -		const struct dc_crtc_timing *timing =
> -			&context->streams[0]->timing;
> -
> -		pp_display_cfg->crtc_index =
> -			pp_display_cfg->disp_configs[0].pipe_idx;
> -		pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
> -	}
> -
>  	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
>  		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
>  }
> -- 
> 2.50.1
>

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> 

-- 
Rodrigo Siqueira

Re: [PATCH 4/7] drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs

[Rodrigo Siqueira]

On 07/31, Timur Kristóf wrote:
> Also needed by DCE 6.
> This way the code that gathers this info can be shared between
> different DCE versions and doesn't have to be repeated.
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c    |  2 --
>  .../drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 10 +++-------
>  .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c   |  2 --
>  3 files changed, 3 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 69e9540f553b..17a8b46b0818 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -386,8 +386,6 @@ static void dce_pplib_apply_display_requirements(
>  {
>  	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
>  
> -	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
> -
>  	dce110_fill_display_configs(context, pp_display_cfg);
>  
>  	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> index baeac8f1c04f..13cf415e38e5 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> @@ -124,6 +124,9 @@ void dce110_fill_display_configs(
>  	int j;
>  	int num_cfgs = 0;
>  
> +	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
> +	pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
> +	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
>  	pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
>  
>  	for (j = 0; j < context->stream_count; j++) {
> @@ -243,13 +246,6 @@ void dce11_pplib_apply_display_requirements(
>  	pp_display_cfg->min_engine_clock_deep_sleep_khz
>  			= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
>  
> -	pp_display_cfg->avail_mclk_switch_time_us =
> -						dce110_get_min_vblank_time_us(context);
> -	/* TODO: dce11.2*/
> -	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
> -
> -	pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
> -
>  	dce110_fill_display_configs(context, pp_display_cfg);
>  
>  	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> index cfd7309f2c6a..7044b437fe9d 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> @@ -109,8 +109,6 @@ static void dce60_pplib_apply_display_requirements(
>  {
>  	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
>  
> -	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
> -
>  	dce110_fill_display_configs(context, pp_display_cfg);
>  
>  	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
> -- 
> 2.50.1
>

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> 

-- 
Rodrigo Siqueira

Re: [PATCH 5/7] drm/amd/display: Don't warn when missing DCE encoder caps

[Rodrigo Siqueira]

On 07/31, Timur Kristóf wrote:
> On some GPUs the VBIOS just doesn't have encoder caps,
> or maybe not for every encoder.
> 
> This isn't really a problem and it's handled well,
> so let's not litter the logs with it.
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> index 4a9d07c31bc5..0c50fe266c8a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> @@ -896,13 +896,13 @@ void dce110_link_encoder_construct(
>  						enc110->base.id, &bp_cap_info);
>  
>  	/* Override features with DCE-specific values */
> -	if (BP_RESULT_OK == result) {
> +	if (result == BP_RESULT_OK) {
>  		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
>  				bp_cap_info.DP_HBR2_EN;
>  		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
>  				bp_cap_info.DP_HBR3_EN;
>  		enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
> -	} else {
> +	} else if (result != BP_RESULT_NORECORD) {
>  		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
>  				__func__,
>  				result);
> @@ -1798,13 +1798,13 @@ void dce60_link_encoder_construct(
>  						enc110->base.id, &bp_cap_info);
>  
>  	/* Override features with DCE-specific values */
> -	if (BP_RESULT_OK == result) {
> +	if (result == BP_RESULT_OK) {
>  		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
>  				bp_cap_info.DP_HBR2_EN;
>  		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
>  				bp_cap_info.DP_HBR3_EN;
>  		enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
> -	} else {
> +	} else if (result != BP_RESULT_NORECORD) {
>  		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
>  				__func__,
>  				result);
> -- 
> 2.50.1
>

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> 

-- 
Rodrigo Siqueira

Re: [PATCH 6/7] drm/amd/display: Don't print errors for nonexistent connectors

[Rodrigo Siqueira]

On 07/31, Timur Kristóf wrote:
> When getting the number of connectors, the VBIOS reports
> the number of valid indices, but it doesn't say which indices
> are valid, and not every valid index has an actual connector.
> If we don't find a connector on an index, that is not an error.
> 
> Considering these are not actual errors, don't litter the logs.
> 
> Fixes: 60df5628144b ("drm/amd/display: handle invalid connector indices")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  drivers/gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +----
>  drivers/gpu/drm/amd/display/dc/core/dc.c          | 15 ++++++++++++++-
>  2 files changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> index 67f08495b7e6..154fd2c18e88 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> @@ -174,11 +174,8 @@ static struct graphics_object_id bios_parser_get_connector_id(
>  		return object_id;
>  	}
>  
> -	if (tbl->ucNumberOfObjects <= i) {
> -		dm_error("Can't find connector id %d in connector table of size %d.\n",
> -			 i, tbl->ucNumberOfObjects);
> +	if (tbl->ucNumberOfObjects <= i)
>  		return object_id;
> -	}
>  
>  	id = le16_to_cpu(tbl->asObjects[i].usObjectID);
>  	object_id = object_id_from_bios_object_id(id);
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index cf3893a2f8ce..33d6a5116aad 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -217,11 +217,24 @@ static bool create_links(
>  		connectors_num,
>  		num_virtual_links);
>  
> -	// condition loop on link_count to allow skipping invalid indices
> +	/* When getting the number of connectors, the VBIOS reports the number of valid indices,
> +	 * but it doesn't say which indices are valid, and not every index has an actual connector.
> +	 * So, if we don't find a connector on an index, that is not an error.
> +	 *
> +	 * - There is no guarantee that the first N indices will be valid
> +	 * - VBIOS may report a higher amount of valid indices than there are actual connectors
> +	 * - Some VBIOS have valid configurations for more connectors than there actually are
> +	 *   on the card. This may be because the manufacturer used the same VBIOS for different
> +	 *   variants of the same card.
> +	 */
>  	for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
> +		struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);
>  		struct link_init_data link_init_params = {0};
>  		struct dc_link *link;
>  
> +		if (connector_id.id == CONNECTOR_ID_UNKNOWN)
> +			continue;
> +
>  		DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
>  
>  		link_init_params.ctx = dc->ctx;
> -- 
> 2.50.1
>

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> 

-- 
Rodrigo Siqueira

Re: [PATCH 7/7] drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3

[Rodrigo Siqueira]

On 07/31, Timur Kristóf wrote:
> For later VBIOS versions, the fractional feedback divider is
> calculated as the remainder of dividing the feedback divider by
> a factor, which is set to 1000000. For reference, see:
> - calculate_fb_and_fractional_fb_divider
> - calc_pll_max_vco_construct
> 
> However, in case of old VBIOS versions that have
> set_pixel_clock_v3, they only have 1 byte available for the
> fractional feedback divider, and it's expected to be set to the
> remainder from dividing the feedback divider by 10.
> For reference see the legacy display code:
> - amdgpu_pll_compute
> - amdgpu_atombios_crtc_program_pll
> 
> This commit fixes set_pixel_clock_v3 by dividing the fractional
> feedback divider passed to the function by 100000.
> 
> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> index 2bcae0643e61..58e88778da7f 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> @@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3(
>  	allocation.sPCLKInput.usFbDiv =
>  			cpu_to_le16((uint16_t)bp_params->feedback_divider);
>  	allocation.sPCLKInput.ucFracFbDiv =
> -			(uint10_t)bp_params->fractional_feedback_divider;
> +			(uint8_t)(bp_params->fractional_feedback_divider / 100000);
>  	allocation.sPCLKInput.ucPostDiv =
>  			(uint8_t)bp_params->pixel_clock_post_divider;
>  
> -- 
> 2.50.1
>

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> 

-- 
Rodrigo Siqueira

Re: [PATCH 0/7] DC: don't overclock DCE 6-10 and other fixes

[Alex Hung]

Reviewed-by: Alex Hung <alex.hung@amd.com>

This patch series was also tested in the promotion test and in CI 
without any regression.

On 7/31/25 03:43, Timur Kristóf wrote:
> This series fixes various issues that I found while trying to
> get old GPUs with DCE 6 to work well with DC.
> 
> The most important part of this series is tweaking how
> the engine clock is set on DCE 6-10.
> 
> For DCE 6 the maximum according to max_clks_by_state is 600 Mhz,
> but dce60_validate_bandwidth sets it to 681 MHz, and then
> dce60_update_clocks further increases it by 15%, resulting in
> a whopping 783 MHz, which is overall 30% more than what the
> hardware was supposed to handle. My Tahiti GPU didn't even boot
> with DC enabled with that clock setting.
> There is a similar issue with DCE 8-10 too, additionally the
> dce80_max_clks_by_state data seems to be incorrect, so I changed
> the maximum to 625 MHz for DCE 8-10, which is what the legacy
> code uses.
> 
> I tested these changes and made sure 4K 60Hz (10 bit) output
> still works with them on the following GPUs:
> 
> * Tahiti (DCE 6)
> * Oland (DCE 6.4)
> * Hawaii (DCE 8)
> * Tonga, Fiji (DCE 10)
> 
> I would appreciate if someone from AMD could confirm what the
> maximum display engine clocks for these parts really are.
> 
> Other than that, the rest of the series deals with some
> ligher problems:
> 
> There are patches to fill the display information on DCE 6-10
> (previously only filled on DCE 11), such as the first CRTC and
> its line time, as well as vblank time, display clock etc.
> These are going to be needed for DPM.
> 
> It also removes some errors and warnings from the logs which
> are caused by the VBIOS on old GPUs reporting some information
> differently, namely some VBIOS seem to lack encoder capability
> entries for some connectors, as well as the actual amount of
> connectors on the GPU not matching the number of entries
> reported by the VBIOS.
> The DC code base already handles these cases well. They are
> not actually errors, so we shouldn't spam the logs with them.
> 
> Finally, there is also a fix for set_pixel_clock_v3 which
> works slightly differently than the other versions.
> 
> Timur Kristóf (7):
>    drm/amd/display: Don't overclock DCE 6 by 15%
>    drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
>    drm/amd/display: Find first CRTC and its line time in
>      dce110_fill_display_configs
>    drm/amd/display: Fill display clock and vblank time in
>      dce110_fill_display_configs
>    drm/amd/display: Don't warn when missing DCE encoder caps
>    drm/amd/display: Don't print errors for nonexistent connectors
>    drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3
> 
>   .../gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +--
>   .../drm/amd/display/dc/bios/command_table.c   |  2 +-
>   .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 14 +++----
>   .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 40 +++++++++++--------
>   .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 10 ++---
>   drivers/gpu/drm/amd/display/dc/core/dc.c      | 15 ++++++-
>   .../drm/amd/display/dc/dce/dce_link_encoder.c |  8 ++--
>   7 files changed, 51 insertions(+), 43 deletions(-)
> 

Re: [PATCH 0/7] DC: don't overclock DCE 6-10 and other fixes

[Alex Deucher]

On Sun, Aug 17, 2025 at 11:08 PM Alex Hung <alex.hung@amd.com> wrote:
>
> Reviewed-by: Alex Hung <alex.hung@amd.com>
>
> This patch series was also tested in the promotion test and in CI
> without any regression.

Did you pick these series up or would you like me to?

Alex

>
> On 7/31/25 03:43, Timur Kristóf wrote:
> > This series fixes various issues that I found while trying to
> > get old GPUs with DCE 6 to work well with DC.
> >
> > The most important part of this series is tweaking how
> > the engine clock is set on DCE 6-10.
> >
> > For DCE 6 the maximum according to max_clks_by_state is 600 Mhz,
> > but dce60_validate_bandwidth sets it to 681 MHz, and then
> > dce60_update_clocks further increases it by 15%, resulting in
> > a whopping 783 MHz, which is overall 30% more than what the
> > hardware was supposed to handle. My Tahiti GPU didn't even boot
> > with DC enabled with that clock setting.
> > There is a similar issue with DCE 8-10 too, additionally the
> > dce80_max_clks_by_state data seems to be incorrect, so I changed
> > the maximum to 625 MHz for DCE 8-10, which is what the legacy
> > code uses.
> >
> > I tested these changes and made sure 4K 60Hz (10 bit) output
> > still works with them on the following GPUs:
> >
> > * Tahiti (DCE 6)
> > * Oland (DCE 6.4)
> > * Hawaii (DCE 8)
> > * Tonga, Fiji (DCE 10)
> >
> > I would appreciate if someone from AMD could confirm what the
> > maximum display engine clocks for these parts really are.
> >
> > Other than that, the rest of the series deals with some
> > ligher problems:
> >
> > There are patches to fill the display information on DCE 6-10
> > (previously only filled on DCE 11), such as the first CRTC and
> > its line time, as well as vblank time, display clock etc.
> > These are going to be needed for DPM.
> >
> > It also removes some errors and warnings from the logs which
> > are caused by the VBIOS on old GPUs reporting some information
> > differently, namely some VBIOS seem to lack encoder capability
> > entries for some connectors, as well as the actual amount of
> > connectors on the GPU not matching the number of entries
> > reported by the VBIOS.
> > The DC code base already handles these cases well. They are
> > not actually errors, so we shouldn't spam the logs with them.
> >
> > Finally, there is also a fix for set_pixel_clock_v3 which
> > works slightly differently than the other versions.
> >
> > Timur Kristóf (7):
> >    drm/amd/display: Don't overclock DCE 6 by 15%
> >    drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
> >    drm/amd/display: Find first CRTC and its line time in
> >      dce110_fill_display_configs
> >    drm/amd/display: Fill display clock and vblank time in
> >      dce110_fill_display_configs
> >    drm/amd/display: Don't warn when missing DCE encoder caps
> >    drm/amd/display: Don't print errors for nonexistent connectors
> >    drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3
> >
> >   .../gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +--
> >   .../drm/amd/display/dc/bios/command_table.c   |  2 +-
> >   .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 14 +++----
> >   .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 40 +++++++++++--------
> >   .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 10 ++---
> >   drivers/gpu/drm/amd/display/dc/core/dc.c      | 15 ++++++-
> >   .../drm/amd/display/dc/dce/dce_link_encoder.c |  8 ++--
> >   7 files changed, 51 insertions(+), 43 deletions(-)
> >
>