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* mixing SCMI and PSCI power domain hierarchy
@ 2025-04-07 23:31 Kevin Hilman
  2025-04-10 13:07 ` Ulf Hansson
  0 siblings, 1 reply; 12+ messages in thread
From: Kevin Hilman @ 2025-04-07 23:31 UTC (permalink / raw)
  To: cristian.marussi@arm.com, souvik.chakravarty@arm.com,
	Sudeep Holla, Ulf Hansson
  Cc: arm-scmi@vger.kernel.org, Dhruva Gole, Sebin Francis

Hello SCMI folks,

I'm trying to figure out how to model a power-domain hierarchy when
there is a mixture of SCMI and PSCI domains.

Let's say I have a top-level PD, managed by PSCI, but inside it it has
both a CPU cluster (with cluster & CPU PDs controlled by PSCI) as well
as some other sub-domains for leaf devices that are controlled by SCMI.
A simplified version looks something like this:

SOC
 |
 |- TOP1_PD (PSCI)
     |
     |-- LEAF1_PD (SCMI)
     |-- LEAF2_PD (SCMI)
     |
     \-- CLUSTER_PD (PSCI)
         |
         |-- CPU1_PD (PSCI)
         \-- CPU2_PD (PSCI)

             
So the main question is: how do I describe the SCMI part of this today
in DT?  Currently, I have something like this for the SCMI-controlled
PDs:

	scmi_pds: protocol@11 {
		reg = <0x11>;
		#power-domain-cells = <1>;
		bootph-all;
	};

and the leaf devices under LEAF1_PD and LEAF2_PD would have
`power-domains = <&scmi_pds N>` properties, indicating their PD is
managed by SCMI.  That part works fine.  And I'm also able to model the
CPU PDs and CLUSTER_PD just fine, including using
domain-idle-states... (Hi Ulf ;)

But... how do I describe the relationship of this hierarchy?  In
particular, when the SCMI-controlled PDs are actually subdomains of a
top-level, non-SCMI PD.  I tried adding `power-domains = <&TOP1_PD>`
inside the scmi_pds node, but that property seems to be ignored.  So it
seems that currently it has not been considered to have SCMI PDs as
sub-domains of other PDs.  Is that correct?  Is this something anyone
else has considered adding?

The hierarchy I describe above is not made up, it's for the TI AM62L
SoC, which is in the process of being upstreamed[1], and we're trying to
figure out the proper way to describe the power domain hierarchy of this
SoC in a way that can support the multiple low-power idle states that
the SoC family plans to support.

All suggestions, redirections, corrections welcome!

Thanks,

Kevin

[1]
https://lore.kernel.org/r/20250109-am62lx-v3-0-ef171e789527@ti.com

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2025-05-28 20:09 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-07 23:31 mixing SCMI and PSCI power domain hierarchy Kevin Hilman
2025-04-10 13:07 ` Ulf Hansson
2025-04-16  0:22   ` Kevin Hilman
2025-04-16 13:22     ` Ulf Hansson
2025-04-16 16:34       ` Kevin Hilman
2025-04-16 19:28         ` Kevin Hilman
2025-04-25 10:48           ` Ulf Hansson
2025-04-16 23:57       ` Kevin Hilman
2025-04-25 11:08         ` Ulf Hansson
2025-04-25 14:39           ` Kevin Hilman
2025-05-16 12:36             ` Ulf Hansson
2025-05-28 20:09               ` Kevin Hilman

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