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Mon, 09 Sep 2024 02:51:43 -0700 (PDT) Received: from [192.168.0.122] ([59.188.211.160]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20710e15cfdsm30915395ad.6.2024.09.09.02.51.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Sep 2024 02:51:43 -0700 (PDT) Message-ID: <1a318d4f-8883-490f-a537-d641cf845a7c@gmail.com> Date: Mon, 9 Sep 2024 17:51:40 +0800 Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/3] tty: serial: samsung: Fix serial rx on Apple A7-A9 To: Kwanghoon Son , Krzysztof Kozlowski , Alim Akhtar , Greg Kroah-Hartman , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: asahi@lists.linux.dev References: <20240909084222.3209-1-towinchenmi@gmail.com> <20240909084222.3209-4-towinchenmi@gmail.com> Content-Language: en-MW From: Nick Chan In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/9/2024 17:43, Kwanghoon Son wrote: > On Mon, 2024-09-09 at 16:37 +0800, Nick Chan wrote: >> Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is >> enabled by bit 11 in UCON. >> >> Access these bits in addition to the original RXTO and RXTO enable bits, >> to allow serial rx to function on A7-A9 SoCs. This change does not >> appear to affect the A10 SoC and up. >> >> Signed-off-by: Nick Chan >> > > [snip] > >> diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h >> index 1e8686695487..964a4fbf2626 100644 >> --- a/include/linux/serial_s3c.h >> +++ b/include/linux/serial_s3c.h >> @@ -246,24 +246,28 @@ >> S5PV210_UFCON_TXTRIG4 | \ >> S5PV210_UFCON_RXTRIG4) >> >> -#define APPLE_S5L_UCON_RXTO_ENA 9 >> -#define APPLE_S5L_UCON_RXTHRESH_ENA 12 >> -#define APPLE_S5L_UCON_TXTHRESH_ENA 13 >> -#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) >> -#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) >> -#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) >> +#define APPLE_S5L_UCON_RXTO_ENA 9 >> +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 >> +#define APPLE_S5L_UCON_RXTHRESH_ENA 12 >> +#define APPLE_S5L_UCON_TXTHRESH_ENA 13 >> +#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) >> +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) >> +#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) >> +#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > Small thing, but other diff is not needed except > APPLE_S5L_UCON_RXTO_LEGACY_ENA. > > Kwang. The other diffs are there to keep everything aligned, it looks like a jumbled mess here in the email, but in an editor like nano it is all aligned, before or after this series. > >> >> #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ >> S3C2410_UCON_RXIRQMODE | \ >> S3C2410_UCON_RXFIFO_TOI) >> #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ >> + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ >> APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ >> APPLE_S5L_UCON_TXTHRESH_ENA_MSK) >> >> +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) >> #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) >> #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) >> #define APPLE_S5L_UTRSTAT_RXTO BIT(9) >> -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) >> +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) >> >> #ifndef __ASSEMBLY__ >> > Nick Chan