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Tue, 4 Oct 2022 20:26:47 -0700 Received: from dev.nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 4 Oct 2022 20:26:44 -0700 From: Chaitanya Kulkarni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH 16/21] mmc: core: use lib tagset init helper Date: Tue, 4 Oct 2022 20:22:52 -0700 Message-ID: <20221005032257.80681-17-kch@nvidia.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20221005032257.80681-1-kch@nvidia.com> References: <20221005032257.80681-1-kch@nvidia.com> Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT059:EE_|PH7PR12MB5781:EE_ X-MS-Office365-Filtering-Correlation-Id: 924c6177-d801-48b0-c783-08daa681755f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2022 03:26:57.4674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 924c6177-d801-48b0-c783-08daa681755f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5781 Use the block layer helper to initialize the common fields of tag_set such as blk_mq_ops, number of h/w queues, queue depth, command size, numa_node, timeout, BLK_MQ_F_XXX flags, driver data. This initialization is spread all over the block drivers. This avoids the code repetation of the inialization code of the tag set in current block drivers and any future ones. Signed-off-by: Chaitanya Kulkarni --- drivers/mmc/core/queue.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/core/queue.c b/drivers/mmc/core/queue.c index fefaa901b50f..599a34a5680a 100644 --- a/drivers/mmc/core/queue.c +++ b/drivers/mmc/core/queue.c @@ -417,7 +417,6 @@ struct gendisk *mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card) spin_lock_init(&mq->lock); memset(&mq->tag_set, 0, sizeof(mq->tag_set)); - mq->tag_set.ops = &mmc_mq_ops; /* * The queue depth for CQE must match the hardware because the request * tag is used to index the hardware queue. @@ -427,11 +426,9 @@ struct gendisk *mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card) min_t(int, card->ext_csd.cmdq_depth, host->cqe_qdepth); else mq->tag_set.queue_depth = MMC_QUEUE_DEPTH; - mq->tag_set.numa_node = NUMA_NO_NODE; - mq->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_BLOCKING; - mq->tag_set.nr_hw_queues = 1; - mq->tag_set.cmd_size = sizeof(struct mmc_queue_req); - mq->tag_set.driver_data = mq; + blk_mq_init_tag_set(&mq->tag_set, &mmc_mq_ops, 1, 0, + sizeof(struct mmc_queue_req), NUMA_NO_NODE, 0, + BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_BLOCKING, mq); /* * Since blk_mq_alloc_tag_set() calls .init_request() of mmc_mq_ops, -- 2.29.0