From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFD4D24F4F for ; Fri, 11 Nov 2022 17:34:16 +0000 (UTC) Received: by mail-ej1-f45.google.com with SMTP id n12so14039033eja.11 for ; Fri, 11 Nov 2022 09:34:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B+9IrtAc191rAMJ9lamUKYajmKH7hj/07wCLXl1AJ5g=; b=DIJW4KppnxTe5jNYgySEgLVz/BgGBJ9LxSXsFSI0l8GY2mlIsocAwy5HdrKOpW24pj Ix2cWw0/z52VisPWJJyE89qEbOuL7uSa8CI6escg2QrIDGCNsxx9ZcusvKArTHJeAa/c JZv86yvZc6FcJZ0BONBXZE9FTzxlHDfBp9EogP74wScUNIhedW3xw3lya4GNpsMJ67J4 iiMH0kyrkhRBxEcOJj/iJKmxORuvm+ptDJSzU95YD/YVYx7MC0evRVLQ8b7T2ZEpa11q cw+WFLZqnXZ2K//+HeQXY1La5WWam60r4gfxj/aKceX1AqAZ+N9IEkzFVU4pfEoKaTKD /Drg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B+9IrtAc191rAMJ9lamUKYajmKH7hj/07wCLXl1AJ5g=; b=CENjsKB3o/ZwC/Jry1K9llWARE72yHQ6q6WLa8wW/y0+qotqhsAeSXJ7m/52Kt9BW0 AGaQoWUYjNJ9nQHUlO4rqXgmG6WQRsU/xHhcc0dAxJIsHX3Whkg7fDENwHZYatBNx3Iu 8HpkHeVA94zHHWEjrjG53v4/k3bIOhoc8j1oSOHuF1KJoD5okyi681I/3+qHAqi9BbkL z8Vo5U47w/ynCnDH2PkpicNf5RwxZgjTF34knm1zXNd/dfkyy2zN8OGy4bhQcJgB4Mvz yj6QlqVlAr7LqIGQXh1mXgidSyKyg713WD7nYE0bW+NAMQ5qEjgrpsRvzmzY7evVrMMX ZewA== X-Gm-Message-State: ANoB5pkPaaYSnWC/7OTKia1eYtZYyU9mV7LUYQHmF6ZaB0lQpmSf61IN 5kPoFqlI8EtQpBi1JV4YNNKLTnJUHe4= X-Google-Smtp-Source: AA0mqf6kmFSn98UQppLfpDVIILHJIkkiozI9/PhISa0GLrMIph2jrKJ74oNPGwXwIvcOMdBCpdeCyg== X-Received: by 2002:a17:906:4d58:b0:781:bc28:f455 with SMTP id b24-20020a1709064d5800b00781bc28f455mr2692591ejv.170.1668188054895; Fri, 11 Nov 2022 09:34:14 -0800 (PST) Received: from localhost ([85.153.204.139]) by smtp.gmail.com with UTF8SMTPSA id b12-20020a17090630cc00b00780b1979adesm1066664ejb.218.2022.11.11.09.34.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Nov 2022 09:34:14 -0800 (PST) From: Sasha Finkelstein To: thierry.reding@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sasha Finkelstein Subject: [PATCH v3 2/4] pwm: Add Apple PWM controller Date: Fri, 11 Nov 2022 20:33:46 +0300 Message-Id: <20221111173348.6537-3-fnkl.kernel@gmail.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20221111173348.6537-1-fnkl.kernel@gmail.com> References: <20221111173348.6537-1-fnkl.kernel@gmail.com> Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Adds the Apple PWM controller driver. Signed-off-by: Sasha Finkelstein Acked-by: Sven Peter --- drivers/pwm/Kconfig | 12 ++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-apple.c | 127 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/pwm/pwm-apple.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..c3be11468414 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -51,6 +51,18 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_APPLE + tristate "Apple SoC PWM support" + depends on ARCH_APPLE || COMPILE_TEST + help + Generic PWM framework driver for PWM controller present on + Apple SoCs + + Say Y here if you have an ARM Apple laptop, otherwise say N + + To compile this driver as a module, choose M here: the module + will be called pwm-apple. + config PWM_ATMEL tristate "Atmel PWM support" depends on ARCH_AT91 || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..19899b912e00 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_APPLE) += pwm-apple.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c new file mode 100644 index 000000000000..b0c3f86fd578 --- /dev/null +++ b/drivers/pwm/pwm-apple.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Driver for the Apple SoC PWM controller + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_CONTROL 0x00 +#define PWM_ON_CYCLES 0x1c +#define PWM_OFF_CYCLES 0x18 + +#define CTRL_ENABLE BIT(0) +#define CTRL_MODE BIT(2) +#define CTRL_UPDATE BIT(5) +#define CTRL_TRIGGER BIT(9) +#define CTRL_INVERT BIT(10) +#define CTRL_OUTPUT_ENABLE BIT(14) + +struct apple_pwm { + struct pwm_chip chip; + void __iomem *base; + u64 clkrate; +}; + +static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct apple_pwm *fpwm; + u64 on_cycles, off_cycles; + + fpwm = container_of(chip, struct apple_pwm, chip); + if (state->enabled) { + on_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->duty_cycle, NSEC_PER_SEC); + off_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->period, NSEC_PER_SEC) - on_cycles; + writel(on_cycles, fpwm->base + PWM_ON_CYCLES); + writel(off_cycles, fpwm->base + PWM_OFF_CYCLES); + writel(CTRL_ENABLE | CTRL_OUTPUT_ENABLE | CTRL_UPDATE, + fpwm->base + PWM_CONTROL); + } else { + writel(0, fpwm->base + PWM_CONTROL); + } + return 0; +} + +static void apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct apple_pwm *fpwm; + u32 on_cycles, off_cycles, ctrl; + + fpwm = container_of(chip, struct apple_pwm, chip); + + ctrl = readl(fpwm->base + PWM_CONTROL); + on_cycles = readl(fpwm->base + PWM_ON_CYCLES); + off_cycles = readl(fpwm->base + PWM_OFF_CYCLES); + + state->enabled = (ctrl & CTRL_ENABLE) && (ctrl & CTRL_OUTPUT_ENABLE); + state->polarity = PWM_POLARITY_NORMAL; + state->duty_cycle = div_u64(on_cycles, fpwm->clkrate) * NSEC_PER_SEC; + state->period = div_u64(off_cycles + on_cycles, fpwm->clkrate) * NSEC_PER_SEC; +} + +static const struct pwm_ops apple_pwm_ops = { + .apply = apple_pwm_apply, + .get_state = apple_pwm_get_state, + .owner = THIS_MODULE, +}; + +static int apple_pwm_probe(struct platform_device *pdev) +{ + struct apple_pwm *pwm; + struct clk *clk; + int ret; + + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->base)) + return PTR_ERR(pwm->base); + + platform_set_drvdata(pdev, pwm); + + clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + pwm->clkrate = clk_get_rate(clk); + pwm->chip.dev = &pdev->dev; + pwm->chip.npwm = 1; + pwm->chip.ops = &apple_pwm_ops; + + ret = devm_pwmchip_add(&pdev->dev, &pwm->chip); + return ret; +} + +static const struct of_device_id apple_pwm_of_match[] = { + { .compatible = "apple,s5l-fpwm" }, + {} +}; +MODULE_DEVICE_TABLE(of, apple_pwm_of_match); + +static struct platform_driver apple_pwm_driver = { + .probe = apple_pwm_probe, + .driver = { + .name = "apple-pwm", + .owner = THIS_MODULE, + .of_match_table = apple_pwm_of_match, + }, +}; +module_platform_driver(apple_pwm_driver); + +MODULE_DESCRIPTION("Apple SoC PWM driver"); +MODULE_LICENSE("Dual MIT/GPL"); -- 2.38.1