From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96B7C14BFB4 for ; Sun, 8 Sep 2024 09:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.181 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725786604; cv=none; b=KxGJAwwP8ZkWRZSIJYpak3UIXlXEBiTl6rykc5BwNfIiSVy2BLaqKnW4Df0g7KQvcaB0N087Y8bq1l+YeAV8aN52CfPNJvahPQXt6FohueOd0aYBg8qLt4HlvO7Q0cs6C2KbxVta7oSDud89R216C7PO6Q7h/wVXnUJMiz9shi8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725786604; c=relaxed/simple; bh=epk2xrtaofY4Pms3sf5q4kdXa2ntKR40Qb1RWwvJjgE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hb8dk5dWLwo9MpLQeh8xBuRfrGtsI1A++mwXHn49Zg/DelyuKg3hXLBycgUdF1N/kMd/YbEvXSGGFvqyN6LKP5qvwsG9RPF44xPD4QqLGYTPTbU/c6wPA5VNotAzekgpUDgUhn92laB9S7iCSPnfAwHAMZVO0Al4NVQTg5mGXfQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KQCnbMdT; arc=none smtp.client-ip=209.85.210.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KQCnbMdT" Received: by mail-pf1-f181.google.com with SMTP id d2e1a72fcca58-718d6ad6050so1594760b3a.0 for ; Sun, 08 Sep 2024 02:10:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725786602; x=1726391402; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RMS8c5/u0QQ/ldqnzOaZXPb8Wd+9JvT8PF4nOfpjFOU=; b=KQCnbMdTKOvdQlrEJL5B9h7dlzH1YGja2+F/AG9lYtwJbNWzTLN52PzDW8iSEQoZFZ 6tXqb1mQFjU2VKBj5ZuzGXYJFIW5KZdJxeqS7ml6RoQsnywmQgwP7zuuC698CGm//CoK BK4adc6IdYPcljbYMChQ4+oJcscNBc2D4EiXRMI3DesqKlZQOOJz81L3JQMXmrlaqFu8 6vSiALzfLi6lzYVTR47eH58idJ5KoX/Dh1js+BtuqkhhMBkPiFhGfgtH1l/i6ZSiPzQU Ld2eBeRDOPIo6VJaSNkKXMaN3BZR7pUpr4tbu1341Mz8bVQUNxVf4TzttWWyFYmvl7qV 3+rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725786602; x=1726391402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RMS8c5/u0QQ/ldqnzOaZXPb8Wd+9JvT8PF4nOfpjFOU=; b=F5tnNSAb3xSF1DIfrCZ7OGlYcRiyFBMhpzaB92HNG/Z3g2yMylmqdEMzWjnzKM2X3a GvTUc8hdj+Qn66JgeIV4Okv76U1InbC/AEy+s5K1VNYO7ySycWzcmf8QoEhdJ8rK/ZYu HQEiytU2Minw1MYtseNV/H4jbiMz7UMNc76GVv+kYWxklWml35pouNt2CUQG9j/Xdx2p 6xI8iue5UexJejvfNSgolSKVN/Nm7RezfzBzjybu1crkwoCZqmWnNE3wzEyzr0RS9uIH V27Va9L0qhjOhfg2dQvPahmfAfK2UJlChgGXYr11mMvRAxylkvKog3pqaQiYigAkEHw4 xBbQ== X-Gm-Message-State: AOJu0YxxOGoVpQ/KY8zJm3P0nkIg9eCUAeFWuq3b23k6Nhek2cRZ4ZI9 gCB7Jm3yWnOHQAkYNRrJYxa3zWldJ403XJ7sU6CNkrOq3ZtHVXkw X-Google-Smtp-Source: AGHT+IFNncUr20DzqhMG3l7Ouz7oZSjCzi/Oh/wY/beA6m53P8SYV12bHS7Ulb4Q9cGqXx0n13I2Tw== X-Received: by 2002:a05:6a21:1693:b0:1cf:241d:6024 with SMTP id adf61e73a8af0-1cf241d640amr7325480637.18.1725786601729; Sun, 08 Sep 2024 02:10:01 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-718e5896e10sm1821439b3a.31.2024.09.08.02.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Sep 2024 02:10:01 -0700 (PDT) From: Nick Chan To: Krzysztof Kozlowski , Alim Akhtar , Greg Kroah-Hartman , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: asahi@lists.linux.dev, Nick Chan Subject: [PATCH v3 3/3] tty: serial: samsung: Fix serial rx on Apple A7-A9 Date: Sun, 8 Sep 2024 17:05:12 +0800 Message-ID: <20240908090939.2745-4-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240908090939.2745-1-towinchenmi@gmail.com> References: <20240908090939.2745-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is enabled by bit 11 in UCON. Access these bits in addition to the original RXTO and RXTO enable bits, to allow serial rx to function on A7-A9 SoCs. This change does not appear to affect the A10 SoC and up. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nick Chan --- drivers/tty/serial/samsung_tty.c | 19 +++++++++++++------ include/linux/serial_s3c.h | 18 +++++++++++------- 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 7574d4176e76..0d184ee2f9ce 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -550,6 +550,7 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port) case TYPE_APPLE_S5L: s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); + s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON); break; default: disable_irq_nosync(ourport->rx_irq); @@ -963,9 +964,11 @@ static irqreturn_t apple_serial_handle_irq(int irq, void *id) u32 pend = rd_regl(port, S3C2410_UTRSTAT); irqreturn_t ret = IRQ_NONE; - if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) { + if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO | + APPLE_S5L_UTRSTAT_RXTO_LEGACY)) { wr_regl(port, S3C2410_UTRSTAT, - APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO); + APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO | + APPLE_S5L_UTRSTAT_RXTO_LEGACY); ret = s3c24xx_serial_rx_irq(ourport); } if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { @@ -1190,7 +1193,8 @@ static void apple_s5l_serial_shutdown(struct uart_port *port) ucon = rd_regl(port, S3C2410_UCON); ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | APPLE_S5L_UCON_RXTHRESH_ENA_MSK | - APPLE_S5L_UCON_RXTO_ENA_MSK); + APPLE_S5L_UCON_RXTO_ENA_MSK | + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK); wr_regl(port, S3C2410_UCON, ucon); wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); @@ -1287,6 +1291,7 @@ static int apple_s5l_serial_startup(struct uart_port *port) /* Enable Rx Interrupt */ s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); + s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON); return ret; } @@ -2143,13 +2148,15 @@ static int s3c24xx_serial_resume_noirq(struct device *dev) ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | APPLE_S5L_UCON_RXTHRESH_ENA_MSK | - APPLE_S5L_UCON_RXTO_ENA_MSK); + APPLE_S5L_UCON_RXTO_ENA_MSK | + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK); if (ourport->tx_enabled) ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; if (ourport->rx_enabled) ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | - APPLE_S5L_UCON_RXTO_ENA_MSK; + APPLE_S5L_UCON_RXTO_ENA_MSK | + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK; wr_regl(port, S3C2410_UCON, ucon); @@ -2822,7 +2829,7 @@ OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup); static int __init apple_s5l_early_console_setup(struct earlycon_device *device, const char *opt) { - /* Apple A7-A11 require MMIO32 register accesses. */ + /* Apple A7-A11 requires MMIO32 register accesses. */ device->port.iotype = UPIO_MEM32; /* Close enough to S3C2410 for earlycon... */ diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index 1e8686695487..964a4fbf2626 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h @@ -246,24 +246,28 @@ S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_RXTRIG4) -#define APPLE_S5L_UCON_RXTO_ENA 9 -#define APPLE_S5L_UCON_RXTHRESH_ENA 12 -#define APPLE_S5L_UCON_TXTHRESH_ENA 13 -#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) -#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) -#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) +#define APPLE_S5L_UCON_RXTO_ENA 9 +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 +#define APPLE_S5L_UCON_RXTHRESH_ENA 12 +#define APPLE_S5L_UCON_TXTHRESH_ENA 13 +#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) +#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) +#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI) #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ APPLE_S5L_UCON_TXTHRESH_ENA_MSK) +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) #define APPLE_S5L_UTRSTAT_RXTO BIT(9) -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) #ifndef __ASSEMBLY__ -- 2.46.0