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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the CPU clusters can be used due to the "Apple Fusion Architecture" big.LITTLE switcher. The values for the P-cluster is used in this case. Signed-off-by: Nick Chan --- Nick Chan (9): arm64: dts: apple: s5l8960x: Add CPU caches arm64: dts: apple: t7000: Add CPU caches arm64: dts: apple: t7001: Add CPU caches arm64: dts: apple: s800-0-3: Add CPU caches arm64: dts: apple: s8001: Add CPU caches arm64: dts: apple: t8010: Add CPU caches arm64: dts: apple: t8011: Add CPU caches arm64: dts: apple: t8012: Add CPU caches arm64: dts: apple: t8015: Add CPU caches arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/apple/s800-0-3.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/apple/s8001.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/apple/t7000.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/apple/t7001.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/apple/t8010.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/apple/t8011.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/apple/t8012.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/apple/t8015.dtsi | 32 ++++++++++++++++++++++++++++++++ 9 files changed, 142 insertions(+) --- base-commit: 3febe9de5ca5267618675650871a626d0901f8cb change-id: 20250220-caches-bea5d32f91fb Best regards, -- Nick Chan