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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add information about CPU caches in Apple A8X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index 8e2c67e19c4167fc6639458ce79588e153336603..a2efa81305df47bdfea6bc2a4d6749719a6ee619 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -39,6 +39,9 @@ cpu0: cpu@0 { operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -49,6 +52,9 @@ cpu1: cpu@1 { operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu2: cpu@2 { @@ -59,6 +65,16 @@ cpu2: cpu@2 { operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; }; }; -- 2.48.1