From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A8B21BB6BC for ; Fri, 28 Feb 2025 04:12:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740715956; cv=none; b=r8Qx7nO3EMbpdP/ffmGIw8A12dzL4LVVJs0siizNw/qQ2TFTfV2tNIfVFwZW/KQY9shTrg1TGeCLrhbwEXcHrXBZdu7TuHfTgIt4C/Hlw/BOU0mqrU6c15N2HrlRIBqH/hSnbLibFbEMu3FV6eOv7rYDFL4dsJUXpGyMkYG0VyQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740715956; c=relaxed/simple; bh=MbPXWlvl+CRdYMbAx6AekhnxkcwDgazyj5+54FmTU+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=myDWJBHvBvsU+rW6xoa9BVxfkqQCXwu8Q/Jye3LZ+zcbITwJN6EZ8Aiss9TMOLEXo6Onai1SMy5cmk7gY0ZZ6pxVC4JZiJW3LHOS+h0W6o1r7qvIoXxizrNfN8vOj768P8t3DBB4RD7q1KWHNNC9jucqEJfL0cOPcCjt94CEdvs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TOT4SceZ; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TOT4SceZ" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-2210d92292eso43906715ad.1 for ; Thu, 27 Feb 2025 20:12:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740715954; x=1741320754; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZpzR+hSxCg8C4vNujl/ovfsfahtzrD7JUQLRJ3RDxiE=; b=TOT4SceZwL5etP9HhfYGS+j/KK67TYFOzpXmmyvPxehXUKoT2dcjX2Nl6aoo2Jdo65 /qNIgDt6zGOkmr/1tERN06PUaMfTQ8bQkhDTLno59jiTvlU25f6a9cFOhRm1qUj5KKz4 gbvB0gvvocgEfsx8XlYDCLYsBoZU2WeoLEX261JNnwPH4TRAUho2lenmXlRKaEvEAiL7 3cyhxLwDBnzW/PWPltbISYj1zUn6HM5jzpugEG2IzyzqEGjgQAkzGCAT/hyYq/A0RTTs 8xPHS7KyzcHOyJ/kzPmZA9JzFDfe6WNbTli1EQ8T76rfgV1iAmvuZgogx5lXA2I4rajm 0kNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740715954; x=1741320754; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZpzR+hSxCg8C4vNujl/ovfsfahtzrD7JUQLRJ3RDxiE=; b=khMDYoFdtYrZEUBwwORi5TGvrIPSfQyjaL4v2y560R5iyahgQrogAcfWXMrhMKspAk BHpah+BZJonPY0+sz+AbJv31gST8i8twapW6iHJBXIONcClt6kWU/xsMEwrZAbhvTJnp WicjYMdFlJWOJ3y5uIDH7sAa0OCxo/eWsUoRqVK+6b4GnegORA6Q3CcdwEPPFVysTnmv JBGiV9SDw5aA3URcjWYIGxhstQvmhQEnVJ0HGWkkIfNp7JYko83vp9WEZeCuG8Q634qp H8oYfIPMavqXccXN2IblPxg+JGfPWIW76ZOyW7r7SWRLyXOI5u7tHiGxlXqn1aPReOKk L28A== X-Forwarded-Encrypted: i=1; AJvYcCWdyohlwxaMbheAXr6vOnlr94+TjhpdeJ7aVaKtLoq3cCdcHdRmI08j96ykfuwicZRqoPeIVw==@lists.linux.dev X-Gm-Message-State: AOJu0Yy6Q2gPu0jODvczkXl5ecH84XP0GVL17wrXsWMEgnNzgJfclLbH J3fkVWqoLuqV/Vs1eL92ffnZwno729knyU4Z7sPmHwk9W7NcXfd3biH7wQ== X-Gm-Gg: ASbGncs81980yeTfyKBZC5Ad7eKc8pIRZd6wg7VPXBGDHxxj0AEXB1k+VZa+uT+us50 oW2gePGmql4w/7eZ2hcYgoMb2K46u674H6LAjZ4AC/pG2Kk0q+8yB2QpdngGnubjB6qCgMeQPRp B0jd5eoeLE0VxoCBEas+YhIatasxAKRNFN25LykXBOcpqRAv5W4S1wGIhcegueTf4lU1179JKxB /HaYsVfg1RMsKgdfXhZ2D3Hvzm5LDkXGfd1pmtLaMW8oeF7Ou7tivcr5RoBNzcSQAK1L0/RHiTN h+12T/2FyPIXJturCsAUdqNG9Tg= X-Google-Smtp-Source: AGHT+IHK3qa7RuGqowdSc15W7HK7IolZ+tRUMo3877RhLFbbmwqqpjV1bo4qxgUgTcnsko2+lEp/KQ== X-Received: by 2002:a05:6a20:12c9:b0:1ee:6187:7fcc with SMTP id adf61e73a8af0-1f2f4ccb3c6mr3218629637.17.1740715954536; Thu, 27 Feb 2025 20:12:34 -0800 (PST) Received: from [127.0.1.1] ([49.130.74.133]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-aee7dec4114sm2387856a12.57.2025.02.27.20.12.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 20:12:34 -0800 (PST) From: Nick Chan Date: Fri, 28 Feb 2025 12:06:48 +0800 Subject: [PATCH v5 08/11] drivers/perf: apple_m1: Add Apple A8/A8X support Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250228-apple-cpmu-v5-8-9e124cd28ed4@gmail.com> References: <20250228-apple-cpmu-v5-0-9e124cd28ed4@gmail.com> In-Reply-To: <20250228-apple-cpmu-v5-0-9e124cd28ed4@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7312; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=MbPXWlvl+CRdYMbAx6AekhnxkcwDgazyj5+54FmTU+Q=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBnwTeJWzMZ5bLbH42Q8YHFFAw/hKbsz2aSQV2SB iA7Qf31W0KJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ8E3iQAKCRABygi3psUI JI67D/9+Dx1/AYHl+rmgDZEyZIMRqf+KhUVRC3B9/vbtqnUgOWrw0jI/iEkHQrvpirJ0HJ+MrQo ywDrkKx2v8uTxJNQPrFuWl+cGFf4Bm5Cu6iJzXwoPhYsuTTr+DtFWklW4EJkCyYz4ChVJ1iCS3Y 449mv78NS6z3HYbGQH9u38Xkw4BziXP9WqXepK4ecFayYJXwS4Dfwqa58MqCk1YVL9ODd24e3Sk 5YIObrLg77BOFfkp2w+uCsCT6L0ybTdeLYjDeuyjfxfoZYXmk1VIo703LVMVQvXcNlB5OqqVh2i uvKj4cnQh6zsLB7JwBaj11vhZQUKTgkURiNIIZM6JH2sun03L1neFlmetFpCNkzwkBOCWabqKRD 39YluYU3+m5g8nq5VC0aFTHb6e/TnJYZTg/QZ0/gpKhlIcYqtUkaP2FToACx3ESgAFIOaIWmqxr ZkWU94v5cYNL+gq23q1/XWeufQHIRxRTvs8bEUtn5yoXAzNP4XeNWvHHt5/cNyTpD/Zg0sg/pLT /i497Z2J+qmQvWPLdSIp7wnahESXaE2zfeQqkA75dij5CT7kIiCmhdUEuMwW2Qj4mgBGCzzh0V6 /GLxQ0vzf6lcO3F9N74oEdR4QuQiOk01t2k4MeE84LvNhoIu+zf6Y1Z0rN6R9Rvifm8ySgpldDW TZy3XJV0ul89ECw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found on the Apple A8, A8X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 124 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 93b49f08e5c740c5bba2eede191e279ed4965181..04825a1991ab1c670563e3ce91b43fa5d8c85920 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -27,6 +27,7 @@ #define ANY_BUT_0_1 GENMASK(9, 2) #define ONLY_2_TO_7 GENMASK(7, 2) #define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_3_5_7 (BIT(3) | BIT(5) | BIT(7)) #define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) /* @@ -182,6 +183,111 @@ static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] = { [A7_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, }; +enum a8_pmu_events { + A8_PMU_PERFCTR_UNKNOWN_1 = 0x1, + A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A8_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa, + A8_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb, + A8_PMU_PERFCTR_BIU_UPSTREAM_CYCLE = 0x13, + A8_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE = 0x14, + A8_PMU_PERFCTR_L2C_AGENT_LD = 0x1a, + A8_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b, + A8_PMU_PERFCTR_L2C_AGENT_ST = 0x1c, + A8_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d, + A8_PMU_PERFCTR_SCHEDULE_UOP = 0x52, + A8_PMU_PERFCTR_MAP_REWIND = 0x75, + A8_PMU_PERFCTR_MAP_STALL = 0x76, + A8_PMU_PERFCTR_MAP_INT_UOP = 0x7b, + A8_PMU_PERFCTR_MAP_LDST_UOP = 0x7c, + A8_PMU_PERFCTR_MAP_SIMD_UOP = 0x7d, + A8_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84, + A8_PMU_PERFCTR_INST_A32 = 0x8a, + A8_PMU_PERFCTR_INST_T32 = 0x8b, + A8_PMU_PERFCTR_INST_ALL = 0x8c, + A8_PMU_PERFCTR_INST_BRANCH = 0x8d, + A8_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e, + A8_PMU_PERFCTR_INST_BRANCH_RET = 0x8f, + A8_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90, + A8_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93, + A8_PMU_PERFCTR_INST_BRANCH_COND = 0x94, + A8_PMU_PERFCTR_INST_INT_LD = 0x95, + A8_PMU_PERFCTR_INST_INT_ST = 0x96, + A8_PMU_PERFCTR_INST_INT_ALU = 0x97, + A8_PMU_PERFCTR_INST_SIMD_LD = 0x98, + A8_PMU_PERFCTR_INST_SIMD_ST = 0x99, + A8_PMU_PERFCTR_INST_SIMD_ALU = 0x9a, + A8_PMU_PERFCTR_INST_LDST = 0x9b, + A8_PMU_PERFCTR_UNKNOWN_9c = 0x9c, + A8_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A8_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0, + A8_PMU_PERFCTR_L1D_TLB_MISS = 0xa1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3, + A8_PMU_PERFCTR_LD_UNIT_UOP = 0xa6, + A8_PMU_PERFCTR_ST_UNIT_UOP = 0xa7, + A8_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8, + A8_PMU_PERFCTR_LDST_X64_UOP = 0xb1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0, + A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1, + A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4, + A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5, + A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6, + A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8, + A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca, + A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb, + A8_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3, + A8_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4, + A8_PMU_PERFCTR_FETCH_RESTART = 0xde, + A8_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A8_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A8_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A8_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A8_PMU_CFG_COUNT_USER = BIT(8), + A8_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] = { + [0 ... A8_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_1] = ONLY_5_6_7, + [A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A8_PMU_PERFCTR_INST_A32] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_T32] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1), + [A8_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ALU] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ALU] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9c] = ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9f] = ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_f5] = ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_f6] = ONLY_3_5_7, + [A8_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -657,6 +763,12 @@ static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); } +static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -806,6 +918,17 @@ static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } +static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_typhoon_pmu"; + cpu_pmu->get_event_idx = a8_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = a7_pmu_reset; + cpu_pmu->start = a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -855,6 +978,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, }, { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, }, { }, }; -- 2.48.1