From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA29234EEE5 for ; Wed, 17 Dec 2025 16:25:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765988721; cv=none; b=FZ3tJNzB8Cgf8nxwkhY6vE/ezbUbMFpI55JPZWwg6wDXxAWGFuSW6FGOSBmLCQS+rJOC1i1hpasHtZmoulLKINwfpfxt/2rGb+U0UMiTdGQTeQf8Rqy5xDjXvxWnydduqHPZWITIi9M2QnU8fdVt+PY/m84V9Kacuxxy3EU3WLc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765988721; c=relaxed/simple; bh=rT7pSw9B9qpDA5uthGiBGByuYCvdc8tmOM1Erkf2EkY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hco+fKnm24kGStq21WBoUq/KVutXGXG1vTPnXStst+DYF8nMcsV90JffeGHE6rDtmlllKrtdENYVVrdsxK0/0Wg60OfYLqjsIZbsaH/GZSvf0jNiPS6wca1J4QP+X57b1z99jmGk6NHsMSIEsZ/PdQsA6YW5cRj/2Mv63UaLE3Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=E2DAxTcB; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="E2DAxTcB" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2a0d06ffa2aso42863395ad.3 for ; Wed, 17 Dec 2025 08:25:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1765988718; x=1766593518; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wCoRZwxAgH5sEhfaNxTmxjkp/QNB8K6lFiXGEg/VuDE=; b=E2DAxTcBLak5RfGAKl9RnMp827rGs57JAX1Z1MRaAcffqEK9IuU3RJYeu/GaJuW+Yo X5TXsOi5k61Rzh1+FaI9ZDXmy/6v2++rZk5h6ei6G447CV7hFYnornl75e8ZNxntXLzB 9VyUwu1wEA7a/HB7XetGGy9dDoYRIImqt1f2sFIBNG19Z9S9UPSbkkpq/C991CZDEWTL HExdjacFF1CmlQak/bbbg6NP+6AEO9UzQ0wzGr9ufDJi1ElsIb5jCshNuVxj97AXqDL1 hUg+5QNy7BtjUkSJngv7bDoD2VGTQt42BmrwE0R2lPHlcXHL4oNO8u/9AyeBKwX+aNvK LLgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765988718; x=1766593518; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wCoRZwxAgH5sEhfaNxTmxjkp/QNB8K6lFiXGEg/VuDE=; b=dni0Aq5S3VWBPm9vVzt1PvNpRREJ7zIJcFgnlO+xeaNXEXdp8R7o8FQ4DoMxyD1DAr MiVuXLW0nTzE1V+DVp06oEp+KstjxpR8VdS/wwOYHcPotY3Kv8dIv0FJva0FaFWUcInc Tr4GFYHg8CFfs81HVKYGEBDZIbJ5AwyTpgdl2j86wECmNXZBCrJIdW8dN+fYND9bC5nn ZvCxnzmKcY1XPiVOAmthio9f2iOPQoGqR84NSRxCifxCRYA8kzpq+34imw3E4ZmQDyJJ XYiJ453QyNYb8qJ4LNCNheoV5xT0YTEOOLKboQfgf6OA7BZxN11MbKtdeEwt4PM1hcjS G2vA== X-Forwarded-Encrypted: i=1; AJvYcCW0y8+TUhx4/23CHXITbVZHV5wpWLz8wwV7i/EUM/XMiaGb2BEqJTpfw1SsTNBiljSJYFmiZQ==@lists.linux.dev X-Gm-Message-State: AOJu0YwuI6axGqwgPUJVcfIkuFOBHVdtwLway24/nJWA7OXCep57DNmn nuWYDm/MeiVuuMwIUDU/j8ROtA8aoKkjSCpIw2o6Pa/7sID+gpLG2dx2JXPzau45 X-Gm-Gg: AY/fxX65IkxCpTcjF7Y+nMP4vRurYr6HieNzXMXLuh29PyZUD+UAOYIgj7Kob0l2Ubx VKgGg0fAelKFEZqaApneDaAm4qH/dYePFiYHZp4uaDhJN/lEXJ86IfFMO8y08EKiwzOmGwZMF3P tipBHT7+1jEPyUsx7eMPQylf8BzhY0t2Dp8//V5ECsKHXfNMYik9dVINuta04Gs+vr2xKbndk5d dG1X9IHRkoJXfX6F3UzexIv8g48kLmyyPagJy02sAfUHmkTFfiKWJKsVwDvASa3yJZ+92kActCf 8jJrSPgoiZ7Pj7kEgVZehQY03WntuycA+J7K0DQ8ZEhzekHHKLAGBVrEvUCsVh6KWozuNivnHxJ 0HUPL4m7Yh6X9RONz2rwApEx0zavYPrV3ar+f5wP0GURI6ASBI2Szmmzd9A7vqma5XoWAWq+ALl zu9rWSOmTPnpo8 X-Google-Smtp-Source: AGHT+IGsxuG66NmPgoGcIvFTuRcGywvfDcaA0oYthZm6gYWypcVNHcjuz76LOTpzG6laa39BqRJfYg== X-Received: by 2002:a17:902:f9c3:b0:295:96bc:8699 with SMTP id d9443c01a7336-29f23b53ef6mr126107535ad.20.1765988717686; Wed, 17 Dec 2025 08:25:17 -0800 (PST) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2a0b0687c62sm122980415ad.88.2025.12.17.08.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 08:25:17 -0800 (PST) From: Nick Chan Date: Thu, 18 Dec 2025 00:23:25 +0800 Subject: [PATCH v9 12/21] drivers/perf: apple_m1: Add Apple A11 Support Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251218-apple-cpmu-v9-12-4deadbe65d03@gmail.com> References: <20251218-apple-cpmu-v9-0-4deadbe65d03@gmail.com> In-Reply-To: <20251218-apple-cpmu-v9-0-4deadbe65d03@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7913; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=rT7pSw9B9qpDA5uthGiBGByuYCvdc8tmOM1Erkf2EkY=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBpQtlBlUPZ7CkzZkhTrLF97vH511U5+N08pPC1s 0vcfKOu4KWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaULZQQAKCRABygi3psUI JP5QEACK0rNh7Rsd+4HeKfNoraNRSolB86Ftlapris3QF94S1d/QvDbwLYiL9Wb6rH/MdQajB/s FQ/gNnm7e+2PZ9CJpEvNBzGHvOctdyDkvb8v5bX80UI/OYDYa6HnGFNxz20qxEJgfmI4AyHdHz7 ZYPVWwrYF07xReXV5HmPxkqL4lXBwRJCEiVeeMijWf7maH9OhI5Q2nuTND+RfkueeRBVrtMBCIp GvkI66xNAGZ8jnN/savtmD/Uy+TwsMRVfJ1XZfecsUabhvOQD5MSHzpSAzqRwCr1grChvmSUOnn is8DgXELDkKny62HmLAjbJsS9bPc7c95RAwRHJLkUCtBYnn7Q0ZV02xnQSBPPNaam9GgPTeRxsE QdNZShDdgzFHFl35uYPyD+iHwKGVpcZzGg+5HwW37qYu2hRGuvO8EndZaW6XN7Jro+w1knTl2nF llG92Pppxj0l1p0Vmxjeiv3vH9dSYPmXmXXoKdr5NTKhb0oxq5ee/YHudCCq9QkK+vKZ50eAQJ5 PBRFtVq077jnqWa74sh/Fmq17GJmFcafVov9PGYeIfNcjTOdtiUWsa3UkTCtFtnoGt+IN8puIPi DJHCg9nJeVg5VRHl5w+N9qpvMz3BrXBgQBA2cTsjnAQ0C+16gUaRTgfkJQ6HAhtAReu0z5OzXUy ntm+aljNRs2Sy4g== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 135 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 8c252731408224c3596b4157024a3ee885d98d9e..d6bbf6e43eae58caea02585541963dba1ea5a428 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -509,6 +509,111 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = { [A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, }; +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP = 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP = 0x52, + A11_PMU_PERFCTR_MAP_REWIND = 0x75, + A11_PMU_PERFCTR_MAP_STALL = 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP = 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP = 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84, + A11_PMU_PERFCTR_INST_ALL = 0x8c, + A11_PMU_PERFCTR_INST_BRANCH = 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET = 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND = 0x94, + A11_PMU_PERFCTR_INST_INT_LD = 0x95, + A11_PMU_PERFCTR_INST_INT_ST = 0x96, + A11_PMU_PERFCTR_INST_INT_ALU = 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD = 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST = 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU = 0x9a, + A11_PMU_PERFCTR_INST_LDST = 0x9b, + A11_PMU_PERFCTR_INST_BARRIER = 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS = 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP = 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP = 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP = 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART = 0xde, + A11_PMU_PERFCTR_ST_NT_UOP = 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP = 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 = 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd = 0xfd, + A11_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER = BIT(8), + A11_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] = { + [0 ... A11_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] = BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] = BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7), + [A11_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] = BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -1028,6 +1133,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1239,6 +1350,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_monsoon_pmu"; + cpu_pmu->get_event_idx = a11_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_mistral_pmu"; + cpu_pmu->get_event_idx = a11_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -1288,6 +1421,8 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,monsoon-pmu", .data = a11_pmu_monsoon_init, }, + { .compatible = "apple,mistral-pmu", .data = a11_pmu_mistral_init, }, { .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, }, { .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, }, { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, }, -- 2.52.0