From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out5-smtp.messagingengine.com (out5-smtp.messagingengine.com [66.111.4.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8556A3D8A for ; Tue, 4 Oct 2022 15:57:01 +0000 (UTC) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 5E7AE5C0113; Tue, 4 Oct 2022 11:57:00 -0400 (EDT) Received: from imap47 ([10.202.2.97]) by compute2.internal (MEProxy); Tue, 04 Oct 2022 11:57:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svenpeter.dev; h=cc:cc:content-type:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1664899020; x=1664985420; bh=8f ukQVxVOSYCkUPUNcLdJutRz1dvTUy8PfzYQAo6isM=; b=l+yg/n97knmHPcEq2h o1LpzdLSxj7lp0whnawB8nCPyhe8hVfE7JXmxVxcWnxyakUkc048tSTwcsaAQbPQ V2aN/jRmizYCSu0O4kaLtHRHCL4lB5XgiR/HOiVFpox0DD5tGT5PbyaEXJLtcDWy NA8JxGg8PEVkCKndIwphOFOx7HDpnNtlxGQcCo/bCmvWm1CPSdtHyly1fUS/n3HS dna4E693G0X1I5sRxxKBU5cVPfMFED184eswbXfN9pYmuAz6ikGNnuq8YYsbqkGS 5NtA+j4ig0CsDXqERjQ678c0XQXc1ZDgpmkTbVRCdqN2vckjS+Fus7dN6YME6gxh gP8g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-type:date:date:feedback-id :feedback-id:from:from:in-reply-to:in-reply-to:message-id :mime-version:references:reply-to:sender:subject:subject:to:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; t=1664899020; x=1664985420; bh=8fukQVxVOSYCkUPUNcLdJutRz1dv TUy8PfzYQAo6isM=; b=EfBHBnWPUcpmB4dRe8mtfBhdCPqVZYLyOQaIo3/Sfn7+ 4l571zNwxZ43nLEMlJeXsqXWjo1lbVFPH625GoZSrnRkSi75+9LX8SCC9qb1v1S7 hY3CqLWS0tqYJ8v5ItXbLOfl+LgF7/LykgRBRSoavERLs3B4fnMp3K++g1feJj4I eqlvhoc7FFol6yVRBEBVxyhtcZ9Lxb8o1TriuFNKb9YTQGu7CYD1nS9utZ/teV0m WXHVnrBfOsgPLy2n7Yk4uFXA/CthMZrXPjz+SDpbKk3G59lpcP4KenOMi4W59yrl busBS1ebQkybFt4IPsb6645MDwKysSBaxC4Ae1Dx/Q== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrfeeiuddgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvfevufgtsehttdertderredtnecuhfhrohhmpedfufhv vghnucfrvghtvghrfdcuoehsvhgvnhesshhvvghnphgvthgvrhdruggvvheqnecuggftrf grthhtvghrnhepleevgfegffehvedtieevhfekheeftedtjeetudevieehveevieelgffh ieevieeunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomh epshhvvghnsehsvhgvnhhpvghtvghrrdguvghv X-ME-Proxy: Feedback-ID: i51094778:Fastmail Received: by mailuser.nyi.internal (Postfix, from userid 501) id D834CA6007C; Tue, 4 Oct 2022 11:56:58 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-1015-gaf7d526680-fm-20220929.001-gaf7d5266 Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Message-Id: <3398859f-e872-4f1d-8a03-4dcb1e46e010@app.fastmail.com> In-Reply-To: <20221004112724.31621-2-konrad.dybcio@somainline.org> References: <20221004112724.31621-1-konrad.dybcio@somainline.org> <20221004112724.31621-2-konrad.dybcio@somainline.org> Date: Tue, 04 Oct 2022 17:56:38 +0200 From: "Sven Peter" To: "Konrad Dybcio" , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: "Nick Chan" , "Hector Martin" , "Alyssa Rosenzweig" , "Thomas Gleixner" , "Marc Zyngier" , "Rob Herring" , "Krzysztof Kozlowski" , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 2/2] irqchip/apple-aic: Add support for A7-A11 SoCs Content-Type: text/plain Hi, On Tue, Oct 4, 2022, at 13:27, Konrad Dybcio wrote: > Add support for A7-A11 SoCs by if-ing out some features only present > on: > > * A11 & newer (implementation-defined IPI & UNCORE registers) > * A11[1] & newer (fast IPI support). > > UNCORE/UNCORE2 and IPI registers conveniently both first appeared on > A11, so introduce just one check for that. > > Knowing whether the SoC supports the latter is necessary, as they are > written to, even if fast IPI is disabled. AFAIK that's only an artifact in this driver: It was added to prevent an FIQ storm in case there were pending fast ipis (i.e. the bootloader was broken ;)) when this driver didn't support fast ipis yet. > This in turn causes a crash > on older platforms, as the implemention-defined registers either do > something else or are not supposed to be touched - definitely not a > NOP though. > > [1] A11 is supposed to use this feature, but it currently doesn't work > for reasons unknown and hence remains disabled. It can easily be enabled > on A11 only, as there is a SoC-specific compatible in the DT with a > fallback to apple,aic. That said, it is not yet necessary, especially > with only one core up, and it has worked a-ok so far. Just to make sure I understand this correctly - we have the following three situations: - base: no fastipi, no uncore, will work on A11 and M1 though - A11: fastipi and uncore but fastipi is broken (possibly due to HW errata or some bug in this driver that only happens on A11) - M1 (or maybe even A12 already, doesn't matter though): fastipi and uncore support If we figured out _why_ fastipi is broken on A11 we would only need a single feature flag to enable both uncore and fastipi but for now we need two to disable fastipi for A11. I'm also curious: What are the symptoms when you enable fastipi on A11? Sven