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Sat, 01 Mar 2025 04:32:14 -0800 (PST) Received: from [192.168.0.101] ([59.188.211.160]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe825a99a7sm8346849a91.6.2025.03.01.04.32.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Mar 2025 04:32:14 -0800 (PST) Message-ID: <83130117-509a-45ff-bf96-26beb77246e1@gmail.com> Date: Sat, 1 Mar 2025 20:32:10 +0800 Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250220-caches-v1-0-2c7011097768@gmail.com> <4670e5f8-2a92-46bd-8faa-dd3774517f3e@app.fastmail.com> Content-Language: en-US From: Nick Chan In-Reply-To: <4670e5f8-2a92-46bd-8faa-dd3774517f3e@app.fastmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sven Peter 於 2025/3/1 夜晚7:11 寫道: > Hi, > > On Thu, Feb 20, 2025, at 13:21, Nick Chan wrote: >> Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple >> A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the >> CPU clusters can be used due to the "Apple Fusion Architecture" >> big.LITTLE switcher. The values for the P-cluster is used in this >> case. > So this means that the cache information will be "wrong" when the CPU > is in the lower power states and only correct for the higher ones? > I'm not familiar with how these values are used; are you and do you > know if this will have any weird or unexpected effects? > Would it be better to use the cache size for the lower rather than > the higher states or does this not matter much? The information in the device tree is only used for reporting cache sizes in /sys/devices/system/cpu. It represents the physical cache size which may not be the same as the architecturally visible cache size. Cache operations in the kernel consult ccsidr_el1 and csselr_el1, so it should be fine. > > > > Best, > > > Sven Nick Chan