From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BC91400996; Sat, 10 Oct 2026 11:10:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791630636; cv=none; b=SRv7oBgLwBno1SGpKfAVdt9p1N+8JfEpvDskOIkWM9sPOSmgF2+KJ6NGtB2mZ2ZqelKyYpuW/09FlPmk5+p03J6A9pd84JIp+3JOJCMXYTA4GFFmGISXVzyHAT/i3erieYqlTehNw1/7oB07Q1/j2EQHP0OcThdy1oMJ5QedSpk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791630636; c=relaxed/simple; bh=uGYpgQXj/ZDKjyztj2YLm6hq9MFUMSK7bVj1ORY4fS4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Ow42nBP3A3QBo0tTRIm53/zQGXP00PTY3zFdfq0jEYPHFkRKbPSkwg2U7pfJKt5S98oWF14ux3cErp7OSEIsVN1o9KFTdePXMSdDHAPBsgT1d4XrH2yBUaS6dKeU+fZjTC4kPAuc22FQki8LuyyLVbBaVqy+8iBEBymLQasULtI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tbe02Vz5; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tbe02Vz5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C99C51F000FF; Sat, 10 Oct 2026 11:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791630633; bh=yy/aE7bL88JUeWLGWq8Z4A6u4H8Q4cX7fVUebItHTGM=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=Tbe02Vz50K0GO8HexwXiHTgLG5Xz03HYD6bU2VIsuWbZ07W2JRiptR6/ZvCSLVGK7 MynFDKdkb8ecxn7V9B5jA6aenGsBq4e/V1bJ3xqq6uKaXWMlFg86qnV0Y7AWXmeseC NBWrBlD+4huIUYo0lGonq1jEAue0+2dKtfXM/qluGrfmVNPbM0CiJaBNJvaYOXFZp2 CWfcfvycnBP9Nu6Szmex1LqKdUtcMKIrPJn7bc3H3A1YbTGPFs+LzQmobPti4d+vj1 kDnGms+rqR+ewc9/ZU1kt1Y3PhGPXtMWHKLqaAR+zWbMZfIhqxXL65ULgPhhCS0nHX DyoGRaOS7rr0g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xFUyF-00000001L2v-1Zu7; Sat, 10 Oct 2026 11:10:31 +0000 Date: Sat, 10 Oct 2026 12:10:30 +0100 Message-ID: <864iet3j6h.wl-maz@kernel.org> From: Marc Zyngier To: Myria Sarvay Cc: Michael Reeves , Oliver Upton , Catalin Marinas , Will Deacon , Mark Rutland , Yureka Lilian , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Sven Peter , Janne Grunau , Neal Gompa , asahi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4 In-Reply-To: References: <20261008-apple-m3-m4-kvm-v1-0-7bb4cbf3d63b@gmail.com> <20261008-apple-m3-m4-kvm-v1-2-7bb4cbf3d63b@gmail.com> <86cxtk2utm.wl-maz@kernel.org> <86bj932ssc.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: myrialsarvay@gmail.com, michael.reeves077@gmail.com, oupton@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, yureka@cyberchaos.dev, fuad.tabba@linux.dev, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, sven@kernel.org, j@jannau.net, neal@gompa.dev, asahi@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sat, 10 Oct 2026 11:54:16 +0100, Myria Sarvay wrote: > > Hi Marc, > > (Resending because I forgot to reply all, sorry Marc) > > On Fri, Oct 09, 2026 at 09:16:03AM +0100, Marc Zyngier wrote: > > On Fri, 09 Oct 2026 01:03:57 +0100, > > Michael Reeves wrote: > > > > > > > I can provide the binary (and a few scripts) to test this easily. > > > > Should they have been fixed, we can always create a second > > > > implementation list to cover the PMU. > > > > > > Can you please send that so we can try? That would be much > > > appreciated, thank you. > > > > I've sent you (and Yureka) details over IRC. If you need help with > > setting things up, let me know directly. > > > > Thanks, > > > > M. > > > > -- > > Without deviation from the norm, progress is not possible. > > I've tested the patches on my M3 Max (t6031-j514c), and without these > patches, it SErrors, and with them (and including the M3/M4 MIDRs in > the has_vgic_v3 list in arch/arm64/kernel/cpufeature.c) it doesn't > SError, and the iso boots correctly to a login getty. Thanks for letting me know. When you post v2 to fix the has_vgic_v3 list, please collect the details of what this was tested on in the cover letter, it may become useful in the future. Cheers, M. -- Without deviation from the norm, progress is not possible.