From: Brian Norris <briannorris@chromium.org>
To: Wen Gong <wgong@codeaurora.org>
Cc: linux-wireless@vger.kernel.org, ath10k@lists.infradead.org
Subject: Re: [PATCH] ath10k: support PCIe enter L1 state
Date: Wed, 14 Nov 2018 16:28:36 -0800 [thread overview]
Message-ID: <20181115002836.GA71934@google.com> (raw)
In-Reply-To: <1542163848-837-1-git-send-email-wgong@codeaurora.org>
Hi Wen,
On Wed, Nov 14, 2018 at 10:50:48AM +0800, Wen Gong wrote:
> QCA6174A/QCA9377 PCIe chips support PCIe L1 and L1SS, and indicate the
> L1/L1SS capabilities in PCI configuration space. Currently ath10k driver
> write target PCIe config flags to disallow HW enter into L1, this leads
> some HW modules are still powered up even when both system PCIe RC and
> QCA6174A/QCA9377 endpoint decides to enter into L1 or L1SS.
>
> This cause ~12 mA power drain of bottom power consumption for all scenarios.
> Fix this issue by removing the drive code to write PCIe config flags.
>
> Tested with QCA6174 PCI with firmware
> WLAN.RM.4.4.1-00109-QCARMSWPZ-1, but this will also affect QCA9377 PCI.
> It's not a regression with new firmware releases.
>
> Signed-off-by: Wen Gong <wgong@codeaurora.org>
Is there some reason L1 was disabled in the first place? Was it known to
be unreliable?
Brian
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next prev parent reply other threads:[~2018-11-15 0:28 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 2:50 [PATCH] ath10k: support PCIe enter L1 state Wen Gong
2018-11-15 0:28 ` Brian Norris [this message]
2018-11-15 6:38 ` Wen Gong
2018-11-15 18:43 ` Brian Norris
2018-11-16 7:00 ` Kalle Valo
2018-11-16 7:56 ` Michał Kazior
2019-02-08 13:42 ` Kalle Valo
2019-02-08 17:05 ` Brian Norris
2019-03-08 9:42 ` Kalle Valo
2019-12-02 18:48 ` Brian Norris
2020-02-13 11:15 ` Kalle Valo
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