* Bug in CCK hw_rate definitions?
@ 2015-09-15 21:35 Ben Greear
2015-09-21 7:32 ` Michal Kazior
0 siblings, 1 reply; 3+ messages in thread
From: Ben Greear @ 2015-09-15 21:35 UTC (permalink / raw)
To: ath10k
ath10k hw.h has this:
enum ath10k_hw_rate_cck {
ATH10K_HW_RATE_CCK_LP_11M = 0,
ATH10K_HW_RATE_CCK_LP_5_5M,
ATH10K_HW_RATE_CCK_LP_2M,
ATH10K_HW_RATE_CCK_LP_1M,
But, at least in 10.1 firmware, it appears that CCK hw_rates are 0x40, 0x41, etc
(For those of you with firmware, see ar600P_phy.c, 'RC' column of the rate table.)
Am I missing something or is the driver code just wrong?
Thanks,
Ben
--
Ben Greear <greearb@candelatech.com>
Candela Technologies Inc http://www.candelatech.com
_______________________________________________
ath10k mailing list
ath10k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath10k
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: Bug in CCK hw_rate definitions?
2015-09-15 21:35 Bug in CCK hw_rate definitions? Ben Greear
@ 2015-09-21 7:32 ` Michal Kazior
2015-09-29 20:42 ` Ben Greear
0 siblings, 1 reply; 3+ messages in thread
From: Michal Kazior @ 2015-09-21 7:32 UTC (permalink / raw)
To: Ben Greear; +Cc: ath10k
On 15 September 2015 at 23:35, Ben Greear <greearb@candelatech.com> wrote:
> ath10k hw.h has this:
>
> enum ath10k_hw_rate_cck {
> ATH10K_HW_RATE_CCK_LP_11M = 0,
> ATH10K_HW_RATE_CCK_LP_5_5M,
> ATH10K_HW_RATE_CCK_LP_2M,
> ATH10K_HW_RATE_CCK_LP_1M,
>
> But, at least in 10.1 firmware, it appears that CCK hw_rates are 0x40, 0x41,
> etc
> (For those of you with firmware, see ar600P_phy.c, 'RC' column of the rate
> table.)
>
> Am I missing something or is the driver code just wrong?
These macros are used only to decode L_SIG_RATE now. It can take values 0..15.
If you need/want to change ath10k_hw_rate_cck you'll need to make sure
to update ath10k_mac_hw_rate_to_idx() or its callsite accordingly.
Michał
_______________________________________________
ath10k mailing list
ath10k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath10k
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: Bug in CCK hw_rate definitions?
2015-09-21 7:32 ` Michal Kazior
@ 2015-09-29 20:42 ` Ben Greear
0 siblings, 0 replies; 3+ messages in thread
From: Ben Greear @ 2015-09-29 20:42 UTC (permalink / raw)
To: Michal Kazior; +Cc: ath10k
On 09/21/2015 12:32 AM, Michal Kazior wrote:
> On 15 September 2015 at 23:35, Ben Greear <greearb@candelatech.com> wrote:
>> ath10k hw.h has this:
>>
>> enum ath10k_hw_rate_cck {
>> ATH10K_HW_RATE_CCK_LP_11M = 0,
>> ATH10K_HW_RATE_CCK_LP_5_5M,
>> ATH10K_HW_RATE_CCK_LP_2M,
>> ATH10K_HW_RATE_CCK_LP_1M,
>>
>> But, at least in 10.1 firmware, it appears that CCK hw_rates are 0x40, 0x41,
>> etc
>> (For those of you with firmware, see ar600P_phy.c, 'RC' column of the rate
>> table.)
>>
>> Am I missing something or is the driver code just wrong?
>
> These macros are used only to decode L_SIG_RATE now. It can take values 0..15.
>
> If you need/want to change ath10k_hw_rate_cck you'll need to make sure
> to update ath10k_mac_hw_rate_to_idx() or its callsite accordingly.
Just to close the loop on this:
I was confused about exactly how this was being used.
In the end, I have this working to my satisfaction without having
to change the enums.
Thanks,
Ben
--
Ben Greear <greearb@candelatech.com>
Candela Technologies Inc http://www.candelatech.com
_______________________________________________
ath10k mailing list
ath10k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath10k
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-09-29 20:42 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-09-15 21:35 Bug in CCK hw_rate definitions? Ben Greear
2015-09-21 7:32 ` Michal Kazior
2015-09-29 20:42 ` Ben Greear
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).