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Mon, 03 May 2021 23:56:01 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 8BAFDC433D3; Mon, 3 May 2021 23:56:00 +0000 (UTC) Received: from [10.46.162.249] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: hemantk) by smtp.codeaurora.org (Postfix) with ESMTPSA id 78341C433F1; Mon, 3 May 2021 23:55:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 78341C433F1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=hemantk@codeaurora.org Subject: Re: [PATCH] mhi: add MHI_STATE_M2 to resume success criteria To: Baochen Qiang , manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, ath11k@lists.infradead.org References: <20210420035339.282963-1-bqiang@codeaurora.org> From: Hemant Kumar Message-ID: <11a51914-141d-24b6-cffa-4eb093aaea7f@codeaurora.org> Date: Mon, 3 May 2021 16:55:59 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210420035339.282963-1-bqiang@codeaurora.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210503_165606_559018_A97CF8CE X-CRM114-Status: GOOD ( 22.87 ) X-BeenThere: ath11k@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "ath11k" Errors-To: ath11k-bounces+ath11k=archiver.kernel.org@lists.infradead.org On 4/19/21 8:53 PM, Baochen Qiang wrote: > During system resume, mhi driver triggers M3->M0 transition and then waits > for target device to enter M0 state. Once done, the device queues a state > change event into ctrl event ring and notify mhi dirver by raising an > interrupt, where a tasklet is scheduled to process this event. In most cases, > the taklet is served timely and wait operation succeeds. > > However, there are cases where CPU is busy and can not serve this tasklet > for some time. Once delay goes long enough, the device moves itself to M1 > state and also interrupts mhi driver after inserting a new state change > event to ctrl ring. Later CPU finally has time to process the ring, however > there are two events in it now: > 1. for M3->M0 event, which is processed first as queued first, > tasklet handler updates device state to M0 and wakes up the task, > i.e., the mhi driver. > 2. for M0->M1 event, which is processed later, tasklet handler > triggers M1->M2 transition and updates device state to M2 directly, > then wakes up the mhi driver(if still sleeping on this wait queue). > Note that although mhi driver has been woken up while processing the first > event, it may still has no chance to run before the second event is processed. > In other words, mhi driver has to keep waiting till timeout cause the M0 state > has been missed. > > kernel log here: > ... > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3 > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0 > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1 > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2 > ... > > Fix this issue by simply adding M2 as a valid state for resume. > > Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 > > Signed-off-by: Baochen Qiang nice explanation of the issue! Reviewed-by: Hemant Kumar -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- ath11k mailing list ath11k@lists.infradead.org http://lists.infradead.org/mailman/listinfo/ath11k