[ath9k-devel] [PATCH v3 00/10] Add support for WOW in ath9k

[ath9k-devel] [PATCH v3 00/10] Add support for WOW in ath9k

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

Add support for hardware WoW in ath9k. Magic-packet,
beacon loss triggers, deauth/disassoc patterns
(a special case of user pattern) are tested with 
AR9485. User pattern needs a bit of investigation
on parsing to appropriate 802.11 format.
we will do more rigorous testing and address bugs.
Also we will quickly validate with chipsets like
AR9462, AR9280, AR9285, AR9287 for any bugs.

Thanks a lot to Vadivel for providing me the hardware and
inputs to test. Thanks to Rajkumar, Russell for
their invaluable help. Thanks to Aeolous, Senthil and
Sujith, Raja. Thanks a lot to Luis for providing the complete
frame work for WoW in his initial wow patches.

Mohammed Shafi Shajakhan (10):
  ath9k_hw: Add register definitions for WoW support
  ath9k: Add definitions and structures to support WoW
  ath9k_hw: Add WoW hardware capability flags
  ath9k_hw: advertise WoW support for capable chipsets
  ath9k: advertise supported WoW flags to upper layer
  ath9k_hw: INI changes for WoW for AR9002 chipsets
  ath9k_hw: Add hardware code for WoW
  ath: Add Wake-on-Wireless debug mask
  ath9k: Add WoW related mac80211 callbacks
  ath9k: do not disable hardware while wow is enabled

 drivers/net/wireless/ath/ath.h                   |    2 +
 drivers/net/wireless/ath/ath9k/Makefile          |    1 +
 drivers/net/wireless/ath/ath9k/ar9002_hw.c       |    5 +
 drivers/net/wireless/ath/ath9k/ar9002_initvals.h |   14 +
 drivers/net/wireless/ath/ath9k/ath9k.h           |   28 ++
 drivers/net/wireless/ath/ath9k/hw.c              |    8 +
 drivers/net/wireless/ath/ath9k/hw.h              |   68 +++
 drivers/net/wireless/ath/ath9k/init.c            |   17 +
 drivers/net/wireless/ath/ath9k/main.c            |  390 +++++++++++++++
 drivers/net/wireless/ath/ath9k/pci.c             |    3 +
 drivers/net/wireless/ath/ath9k/reg.h             |  145 ++++++-
 drivers/net/wireless/ath/ath9k/wow.c             |  560 ++++++++++++++++++++++
 12 files changed, 1240 insertions(+), 1 deletions(-)
 create mode 100644 drivers/net/wireless/ath/ath9k/wow.c

[ath9k-devel] [PATCH v3 01/10] ath9k_hw: Add register definitions for WoW support

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

*MAC WoW registers

back-off shift, MAC interrupt enable, magic packet enable,
pattern match enable, aifs, slot wait period, keep alive
frame failure count, beacon fail enable, beacon timeout,
keep alive timeout, auto keep alive disable,
keep alive fail disable and their corresponding
status registers. keep alive frame delay,
pattern end/byte offsets, transmit buffers for
keep alive frames and storing the user patterns

*Power Management Control registers

pme_d3cold_vaux, host_pme_enable, aux_pwr_detect,
power_state_mask, wow_pme_clear

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/reg.h |  145 +++++++++++++++++++++++++++++++++-
 1 files changed, 144 insertions(+), 1 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 5046b28..e808d52 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -696,9 +696,12 @@
 #define AR_WA_BIT7			(1 << 7)
 #define AR_WA_BIT23			(1 << 23)
 #define AR_WA_D3_L1_DISABLE		(1 << 14)
+#define AR_WA_UNTIE_RESET_EN		(1 << 15) /* Enable PCI Reset
+						     to POR (power-on-reset) */
 #define AR_WA_D3_TO_L1_DISABLE_REAL     (1 << 16)
 #define AR_WA_ASPM_TIMER_BASED_DISABLE  (1 << 17)
-#define AR_WA_RESET_EN                  (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
+#define AR_WA_RESET_EN                  (1 << 18) /* Enable PCI-Reset to
+						     POR (bit 15) */
 #define AR_WA_ANALOG_SHIFT              (1 << 20)
 #define AR_WA_POR_SHORT                 (1 << 21) /* PCI-E Phy reset control */
 #define AR_WA_BIT22			(1 << 22)
@@ -1028,6 +1031,8 @@ enum {
 #define AR_PCIE_PM_CTRL                          (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
 #define AR_PCIE_PM_CTRL_ENA                      0x00080000
 
+#define AR_PCIE_PHY_REG3			 0x18c08
+
 #define AR_NUM_GPIO                              14
 #define AR928X_NUM_GPIO                          10
 #define AR9285_NUM_GPIO                          12
@@ -1231,6 +1236,8 @@ enum {
 #define AR_RTC_PLL_CLKSEL       0x00000300
 #define AR_RTC_PLL_CLKSEL_S     8
 #define AR_RTC_PLL_BYPASS	0x00010000
+#define AR_RTC_PLL_NOPWD	0x00040000
+#define AR_RTC_PLL_NOPWD_S	18
 
 #define PLL3 0x16188
 #define PLL3_DO_MEAS_MASK 0x40000000
@@ -1883,6 +1890,8 @@ enum {
 #define AR_PCU_MISC_MODE2_HWWAR2                       0x02000000
 #define AR_PCU_MISC_MODE2_RESERVED2                    0xFFFE0000
 
+#define AR_PCU_MISC_MODE3			       0x83d0
+
 #define AR_MAC_PCU_ASYNC_FIFO_REG3			0x8358
 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL		0x00000400
 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET		0x80000000
@@ -1905,6 +1914,140 @@ enum {
 #define AR_RATE_DURATION_32     0x8780
 #define AR_RATE_DURATION(_n)    (AR_RATE_DURATION_0 + ((_n)<<2))
 
+/* WoW - Wake On Wireless */
+
+#define AR_PMCTRL_AUX_PWR_DET		0x10000000 /* Puts Chip in L2 state */
+#define AR_PMCTRL_D3COLD_VAUX		0x00800000
+#define AR_PMCTRL_HOST_PME_EN		0x00400000 /* Send OOB WAKE_L on WoW
+						      event */
+#define AR_PMCTRL_WOW_PME_CLR		0x00200000 /* Clear WoW event */
+#define AR_PMCTRL_PWR_STATE_MASK	0x0f000000 /* Power State Mask */
+#define AR_PMCTRL_PWR_STATE_D1D3	0x0f000000 /* Activate D1 and D3 */
+#define AR_PMCTRL_PWR_STATE_D1D3_REAL	0x0f000000 /* Activate D1 and D3 */
+#define AR_PMCTRL_PWR_STATE_D0		0x08000000 /* Activate D0 */
+#define AR_PMCTRL_PWR_PM_CTRL_ENA	0x00008000 /* Enable power mgmt */
+
+#define AR_WOW_BEACON_TIMO_MAX		0xffffffff
+
+/*
+ * MAC WoW Registers
+ */
+
+#define AR_WOW_PATTERN			0x825C
+#define AR_WOW_COUNT			0x8260
+#define AR_WOW_BCN_EN			0x8270
+#define AR_WOW_BCN_TIMO			0x8274
+#define AR_WOW_KEEP_ALIVE_TIMO		0x8278
+#define AR_WOW_KEEP_ALIVE		0x827c
+#define AR_WOW_US_SCALAR		0x8284
+#define AR_WOW_KEEP_ALIVE_DELAY		0x8288
+#define AR_WOW_PATTERN_MATCH		0x828c
+#define AR_WOW_PATTERN_OFF1		0x8290	/* pattern bytes 0 -> 3 */
+#define AR_WOW_PATTERN_OFF2		0x8294	/* pattern bytes 4 -> 7 */
+
+/* for AR9285 or later version of chips */
+#define AR_WOW_EXACT			0x829c
+#define AR_WOW_LENGTH1			0x8360
+#define AR_WOW_LENGTH2			0X8364
+/* register to enable match for less than 256 bytes packets */
+#define AR_WOW_PATTERN_MATCH_LT_256B	0x8368
+
+#define AR_SW_WOW_CONTROL		0x20018
+#define AR_SW_WOW_ENABLE		0x1
+#define AR_SWITCH_TO_REFCLK		0x2
+#define AR_RESET_CONTROL		0x4
+#define AR_RESET_VALUE_MASK		0x8
+#define AR_HW_WOW_DISABLE		0x10
+#define AR_CLR_MAC_INTERRUPT		0x20
+#define AR_CLR_KA_INTERRUPT		0x40
+
+/* AR_WOW_PATTERN register values */
+#define AR_WOW_BACK_OFF_SHIFT(x)	((x & 0xf) << 28) /* in usecs */
+#define AR_WOW_MAC_INTR_EN		0x00040000
+#define AR_WOW_MAGIC_EN			0x00010000
+#define AR_WOW_PATTERN_EN(x)		(x & 0xff)
+#define AR_WOW_PAT_FOUND_SHIFT	8
+#define AR_WOW_PATTERN_FOUND(x)		(x & (0xff << AR_WOW_PAT_FOUND_SHIFT))
+#define AR_WOW_PATTERN_FOUND_MASK	((0xff) << AR_WOW_PAT_FOUND_SHIFT)
+#define AR_WOW_MAGIC_PAT_FOUND		0x00020000
+#define AR_WOW_MAC_INTR			0x00080000
+#define AR_WOW_KEEP_ALIVE_FAIL		0x00100000
+#define AR_WOW_BEACON_FAIL		0x00200000
+
+#define AR_WOW_STATUS(x)		(x & (AR_WOW_PATTERN_FOUND_MASK | \
+					      AR_WOW_MAGIC_PAT_FOUND	| \
+					      AR_WOW_KEEP_ALIVE_FAIL	| \
+					      AR_WOW_BEACON_FAIL))
+#define AR_WOW_CLEAR_EVENTS(x)		(x & ~(AR_WOW_PATTERN_EN(0xff) | \
+					       AR_WOW_MAGIC_EN | \
+					       AR_WOW_MAC_INTR_EN | \
+					       AR_WOW_BEACON_FAIL | \
+					       AR_WOW_KEEP_ALIVE_FAIL))
+
+/* AR_WOW_COUNT register values */
+#define AR_WOW_AIFS_CNT(x)		(x & 0xff)
+#define AR_WOW_SLOT_CNT(x)		((x & 0xff) << 8)
+#define AR_WOW_KEEP_ALIVE_CNT(x)	((x & 0xff) << 16)
+
+/* AR_WOW_BCN_EN register */
+#define AR_WOW_BEACON_FAIL_EN		0x00000001
+
+/* AR_WOW_BCN_TIMO rgister */
+#define AR_WOW_BEACON_TIMO		0x40000000 /* valid if BCN_EN is set */
+
+/* AR_WOW_KEEP_ALIVE_TIMO register */
+#define AR_WOW_KEEP_ALIVE_TIMO_VALUE
+#define AR_WOW_KEEP_ALIVE_NEVER		0xffffffff
+
+/* AR_WOW_KEEP_ALIVE register  */
+#define AR_WOW_KEEP_ALIVE_AUTO_DIS	0x00000001
+#define AR_WOW_KEEP_ALIVE_FAIL_DIS	0x00000002
+
+/* AR_WOW_KEEP_ALIVE_DELAY register */
+#define AR_WOW_KEEP_ALIVE_DELAY_VALUE	0x000003e8 /* 1 msec */
+
+
+/*
+ * keep it long for beacon workaround - ensure no false alarm
+ */
+#define AR_WOW_BMISSTHRESHOLD		0x20
+
+/* AR_WOW_PATTERN_MATCH register */
+#define AR_WOW_PAT_END_OF_PKT(x)	(x & 0xf)
+#define AR_WOW_PAT_OFF_MATCH(x)		((x & 0xf) << 8)
+
+/*
+ * default values for Wow Configuration for backoff, aifs, slot, keep-alive
+ * to be programmed into various registers.
+ */
+#define AR_WOW_PAT_BACKOFF	0x00000004 /* AR_WOW_PATTERN_REG */
+#define AR_WOW_CNT_AIFS_CNT	0x00000022 /* AR_WOW_COUNT_REG */
+#define AR_WOW_CNT_SLOT_CNT	0x00000009 /* AR_WOW_COUNT_REG */
+/*
+ * Keepalive count applicable for AR9280 2.0 and above.
+ */
+#define AR_WOW_CNT_KA_CNT 0x00000008    /* AR_WOW_COUNT register */
+
+/* WoW - Transmit buffer for keep alive frames */
+#define AR_WOW_TRANSMIT_BUFFER	0xe000 /* E000 - EFFC */
+
+#define AR_WOW_TXBUF(i)		(AR_WOW_TRANSMIT_BUFFER + ((i) << 2))
+
+#define AR_WOW_KA_DESC_WORD2	0xe000
+
+#define AR_WOW_KA_DATA_WORD0	0xe030
+
+/* WoW Transmit Buffer for patterns */
+#define AR_WOW_TB_PATTERN(i)	(0xe100 + (i << 8))
+#define AR_WOW_TB_MASK(i)	(0xec00 + (i << 5))
+
+/* Currently Pattern 0-7 are supported - so bit 0-7 are set */
+#define AR_WOW_PATTERN_SUPPORTED	0xff
+#define AR_WOW_LENGTH_MAX		0xff
+#define AR_WOW_LEN1_SHIFT(_i)	((0x3 - ((_i) & 0x3)) << 0x3)
+#define AR_WOW_LENGTH1_MASK(_i)	(AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i))
+#define AR_WOW_LEN2_SHIFT(_i)	((0x7 - ((_i) & 0x7)) << 0x3)
+#define AR_WOW_LENGTH2_MASK(_i)	(AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i))
 
 #define AR9271_CORE_CLOCK	117   /* clock to 117Mhz */
 #define AR9271_TARGET_BAUD_RATE	19200 /* 115200 */
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 02/10] ath9k: Add definitions and structures to support WoW

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

*add structures, macros and variables for WoW, so that the driver
can make use of it.
*maintain a list for user enabled patterns and masks
*track pattern slots for the hardware limitation on the
maximum number of patterns that can be stored.
*track interrupts enabled before WoW suspend, so
that can be reconfigured after resume
*have macros to parse user defined wow configurations to
hardware code

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/ath9k.h |   19 +++++++++++++++++++
 drivers/net/wireless/ath/ath9k/hw.h    |   20 ++++++++++++++++++++
 2 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index f72c4a3..4c530e5 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -506,6 +506,18 @@ static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
 }
 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 
+struct ath9k_wow_pattern {
+	u8 pattern_bytes[MAX_PATTERN_SIZE];
+	u8 mask_bytes[MAX_PATTERN_SIZE];
+	u32 pattern_len;
+	struct list_head list;
+};
+
+struct ath9k_wow_info {
+	u32 num_of_patterns;
+	struct list_head wow_patterns;
+};
+
 /********************/
 /*   LED Control    */
 /********************/
@@ -707,6 +719,13 @@ struct ath_softc {
 	struct ath_ant_comb ant_comb;
 	u8 ant_tx, ant_rx;
 	struct dfs_pattern_detector *dfs_detector;
+
+#ifdef CONFIG_PM_SLEEP
+	bool wow_got_bmiss_intr;
+	bool wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
+	u32 wow_intr_before_sleep;
+	struct ath9k_wow_info wow_info;
+#endif
 };
 
 void ath9k_tasklet(unsigned long data);
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 9409660..2d5ae5e 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -179,6 +179,23 @@
 #define PAPRD_TABLE_SZ			24
 #define PAPRD_IDEAL_AGC2_PWR_RANGE	0xe0
 
+/* Wake on Wireless */
+
+#define MAX_PATTERN_SIZE		256
+#define MAX_PATTERN_MASK_SIZE		32
+#define MAX_NUM_PATTERN			8
+#define MAX_NUM_USER_PATTERN		6 /*  deducting the disassociate and
+					      deauthenticate packets */
+
+/*
+ * WoW trigger mapping to hardware code
+ */
+
+#define AH_WOW_USER_PATTERN_EN		BIT(0)
+#define AH_WOW_MAGIC_PATTERN_EN		BIT(1)
+#define AH_WOW_LINK_CHANGE		BIT(2)
+#define AH_WOW_BEACON_MISS		BIT(3)
+
 enum ath_hw_txq_subtype {
 	ATH_TXQ_AC_BE = 0,
 	ATH_TXQ_AC_BK = 1,
@@ -861,6 +878,9 @@ struct ath_hw {
 	/* Enterprise mode cap */
 	u32 ent_mode;
 
+#ifdef CONFIG_PM_SLEEP
+	u32 wow_event_mask;
+#endif
 	bool is_clk_25mhz;
 	int (*get_mac_revision)(void);
 	int (*external_reset)(void);
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 03/10] ath9k_hw: Add WoW hardware capability flags

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

have seperate wow capability flags for
*basic wow support
*device capable of matching exact user defined pattern
or de-authentication/disassoc pattern
*device such AR9280 requires first four bytes for
all sort of patterns

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/hw.h |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 2d5ae5e..c8b800d 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -228,8 +228,22 @@ enum ath9k_hw_caps {
 	ATH9K_HW_CAP_RTT			= BIT(14),
 	ATH9K_HW_CAP_MCI			= BIT(15),
 	ATH9K_HW_CAP_DFS			= BIT(16),
+	ATH9K_HW_WOW_DEVICE_CAPABLE		= BIT(17),
+	ATH9K_HW_WOW_PATTERN_MATCH_EXACT	= BIT(18),
+	ATH9K_HW_WOW_PATTERN_MATCH_DWORD	= BIT(19),
 };
 
+/*
+ * WoW device capabilities
+ * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
+ * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
+ * an exact user defined pattern or de-authentication/disassoc pattern.
+ * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
+ * bytes of the pattern for user defined pattern, de-authentication and
+ * disassociation patterns for all types of possible frames recieved
+ * of those types.
+ */
+
 struct ath9k_hw_capabilities {
 	u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 	u16 rts_aggr_limit;
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 04/10] ath9k_hw: advertise WoW support for capable chipsets

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

support WoW for all chipsets starting from AR9280, AR9285, AR9287,
AR9380, AR9382, AR9485, AR9462. Really all hardware may not support
WoW even though the flag is set and the WoW working depends on
your laptop, BIOS apart from the hardware.

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/hw.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index a42c26f..041d797 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -2572,6 +2572,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 	}
 
 
+	if (AR_SREV_9280_20_OR_LATER(ah)) {
+		pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
+				 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
+
+		if (AR_SREV_9280(ah))
+			pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
+	}
+
 	return 0;
 }
 
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 05/10] ath9k: advertise supported WoW flags to upper layer

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

currently the code supports WoW triggers due to
*magic packet
*user defined patterns
*deauth and disassoc patterns
*disconnect - beacon miss, last beacon received timeout,
no ack for keeep alive frames.

we need to support other WoW offload features in the
near future. also a minor cleanup.

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/init.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 9dfce1a..576f808 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -713,6 +713,22 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 	hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
 	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
 
+#ifdef CONFIG_PM_SLEEP
+
+	if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
+	    device_can_wakeup(sc->dev)) {
+
+		hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT |
+					  WIPHY_WOWLAN_DISCONNECT;
+		hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN;
+		hw->wiphy->wowlan.pattern_min_len = 1;
+		hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE;
+		INIT_LIST_HEAD(&sc->wow_info.wow_patterns);
+
+	}
+
+#endif
+
 	hw->queues = 4;
 	hw->max_rates = 4;
 	hw->channel_change_time = 5000;
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 06/10] ath9k_hw: INI changes for WoW for AR9002 chipsets

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

for AR9002 family of chipsets and for WoW sleep, we reprogram
the SerDes so that the PLL and CHK REQ are both enabled. this
uses more power but in certain cases this is required as otherwise
WoW sleep is unstable and chip may disappear.

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/ar9002_hw.c       |    5 +++++
 drivers/net/wireless/ath/ath9k/ar9002_initvals.h |   14 ++++++++++++++
 drivers/net/wireless/ath/ath9k/hw.h              |    3 +++
 3 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index edf21ea..0e6ee60 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -43,6 +43,11 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
 		INIT_INI_ARRAY(&ah->iniPcieSerdes,
 			   ar9280PciePhy_clkreq_always_on_L1_9280,
 			   ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
+#ifdef CONFIG_PM_SLEEP
+		INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
+			       ar9280PciePhy_awow,
+			       ARRAY_SIZE(ar9280PciePhy_awow), 2);
+#endif
 
 	if (AR_SREV_9287_11_OR_LATER(ah)) {
 		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
index 4d18c66..beb6162 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
@@ -925,6 +925,20 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
 	{0x00004044, 0x00000000},
 };
 
+static const u32 ar9280PciePhy_awow[][2] = {
+	/* Addr      allmodes  */
+	{0x00004040, 0x9248fd00},
+	{0x00004040, 0x24924924},
+	{0x00004040, 0xa8000019},
+	{0x00004040, 0x13160820},
+	{0x00004040, 0xe5980560},
+	{0x00004040, 0xc01dcffd},
+	{0x00004040, 0x1aaabe41},
+	{0x00004040, 0xbe105554},
+	{0x00004040, 0x00043007},
+	{0x00004044, 0x00000000},
+};
+
 static const u32 ar9285Modes_9285_1_2[][5] = {
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index c8b800d..f3ee7b9 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -845,6 +845,9 @@ struct ath_hw {
 	struct ar5416IniArray iniBank7;
 	struct ar5416IniArray iniAddac;
 	struct ar5416IniArray iniPcieSerdes;
+#ifdef CONFIG_PM_SLEEP
+	struct ar5416IniArray iniPcieSerdesWow;
+#endif
 	struct ar5416IniArray iniPcieSerdesLowPower;
 	struct ar5416IniArray iniModesFastClock;
 	struct ar5416IniArray iniAdditional;
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 07/10] ath9k_hw: Add hardware code for WoW

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

add a new file wow.c which takes care of the hardware code
for WoW.

*program the descriptors and data words to periodically
send Keep Alive Frames.
*program the user defined patterns/masks and pattern length
in the hardware registers.
*'ath9k_hw_wow_enable' is called during the drivers suspend
callback which takes care of the following
	- tracking wow event mask (to suppress spurious
	  wow events)
	- properly configure suspend/resume WAR registers
	- configure PCIE PM control register
	- configure MAC WoW registers and their timeouts
	- enabling wow configuration like magic packet,
	  user patterns based on users configuration
	- configuring timeouts for KAL, beacon miss,
	  aifs, slot time, backoff
	- create Keep Alive Pattern ('KAL')
*'ath9k_hw_wow_wakeup' is called during the drivers resume
callback which takes care of the following
	- primary task is to find the reason for wakeup
	  from the wow status register
	- configure/restore AR_PCIE_PM_CTRL register
	- clear all WoW events
	- configure/restore suspend/resume WAR registers

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/Makefile |    1 +
 drivers/net/wireless/ath/ath9k/hw.h     |   31 ++
 drivers/net/wireless/ath/ath9k/wow.c    |  560 +++++++++++++++++++++++++++++++
 3 files changed, 592 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/wireless/ath/ath9k/wow.c

diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 9c41232..2ad8f94 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -17,6 +17,7 @@ ath9k-$(CONFIG_ATH9K_DFS_CERTIFIED) += \
 		dfs.o \
 		dfs_pattern_detector.o \
 		dfs_pri_detector.o
+ath9k-$(CONFIG_PM_SLEEP) += wow.o
 
 obj-$(CONFIG_ATH9K) += ath9k.o
 
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index f3ee7b9..92e34c4 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -1096,6 +1096,37 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
 }
 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 
+
+#ifdef CONFIG_PM_SLEEP
+const char *ath9k_hw_wow_event_to_string(u32 wow_event);
+void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
+				u8 *user_mask, int pattern_count,
+				int pattern_len);
+u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
+void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
+#else
+static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
+{
+	return NULL;
+}
+static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
+					      u8 *user_pattern,
+					      u8 *user_mask,
+					      int pattern_count,
+					      int pattern_len)
+{
+}
+static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
+{
+	return 0;
+}
+static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
+{
+}
+#endif
+
+
+
 #define ATH9K_CLOCK_RATE_CCK		22
 #define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
 #define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
diff --git a/drivers/net/wireless/ath/ath9k/wow.c b/drivers/net/wireless/ath/ath9k/wow.c
new file mode 100644
index 0000000..3e4e568
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/wow.c
@@ -0,0 +1,560 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/export.h>
+#include "ath9k.h"
+#include "reg.h"
+#include "hw-ops.h"
+
+const char *ath9k_hw_wow_event_to_string(u32 wow_event)
+{
+	if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
+		return " Magic pattern ";
+	if (wow_event & AH_WOW_USER_PATTERN_EN)
+		return " User pattern ";
+	if (wow_event & AH_WOW_LINK_CHANGE)
+		return " Link change ";
+	if (wow_event & AH_WOW_BEACON_MISS)
+		return " Beacon reason ";
+
+	return  " unknown reason ";
+}
+EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
+
+static void ath9k_hw_config_serdes_wow_sleep(struct ath_hw *ah)
+{
+	int i;
+
+	for (i = 0; i < ah->iniPcieSerdesWow.ia_rows; i++)
+		REG_WRITE(ah, INI_RA(&ah->iniPcieSerdesWow, i, 0),
+			  INI_RA(&ah->iniPcieSerdesWow, i, 1));
+
+	usleep_range(1000, 1500);
+}
+
+static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
+{
+	struct ath_common *common = ath9k_hw_common(ah);
+
+	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+
+	/* set rx disable bit */
+	REG_WRITE(ah, AR_CR, AR_CR_RXD);
+
+	if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
+		ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
+			REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
+		return;
+	} else {
+		if (!AR_SREV_9300_20_OR_LATER(ah))
+			REG_WRITE(ah, AR_RXDP, 0x0);
+	}
+
+	/* AR9280 WoW has sleep issue, do not set it to sleep */
+	if (AR_SREV_9280_20(ah))
+		return;
+
+	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
+}
+
+#define KAL_FRAME_LEN		28
+#define KAL_FRAME_TYPE		0x2 /* data frame */
+#define KAL_FRAME_SUB_TYPE	0x4 /* null data frame */
+#define KAL_DURATION_ID		0x3d
+#define KAL_NUM_DATA_WORDS	6
+#define KAL_NUM_DESC_WORDS	12
+
+static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
+{
+	struct ath_common *common = ath9k_hw_common(ah);
+	u32 frame_len = KAL_FRAME_LEN;
+	u32 tpc = MAX_RATE_POWER;
+	u32 antenna_mode = 1;
+	u32 transmit_rate;
+	u32 frame_type = KAL_FRAME_TYPE; /* frame type -> data */
+	u32 sub_type = KAL_FRAME_SUB_TYPE; /* subtype -> NULL data */
+	u32 to_ds = 1;
+	u32 duration_id = KAL_DURATION_ID;
+	u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
+	u32 ctl[13] = {0};
+	u32 data_word[KAL_NUM_DATA_WORDS];
+	u8 i;
+	u32 wow_ka_data_word0;
+
+	memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
+	memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
+
+	if (ah->curchan->channelFlags & CHANNEL_CCK)
+		transmit_rate = 0x1b; /* CCK_1M hardware value for this rate */
+	else
+		transmit_rate = 0xb; /* OFDM_6M hardware value for this rate */
+
+	/* set the transmit buffer */
+	ctl[0] = (frame_len | (tpc << 16));
+
+	if (!(AR_SREV_9300_20_OR_LATER(ah)))
+		ctl[0] += (antenna_mode << 25);
+
+	ctl[1] = 0;
+	ctl[3] = transmit_rate;
+	ctl[4] = 0;
+	ctl[7] = (ah->txchainmask) << 2;
+
+	if (AR_SREV_9300_20_OR_LATER(ah))
+		ctl[2] = 0xf << 16; /* tx_tries 0 */
+	else
+		ctl[2] = 0x7 << 16; /* tx_tries 0 */
+
+
+	for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
+		REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
+
+	/* for AR9300 family 13 descriptor words */
+	if (AR_SREV_9300_20_OR_LATER(ah))
+		REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
+
+	data_word[0] = (frame_type << 2) | (sub_type << 4) |
+			(to_ds << 8) | (duration_id << 16);
+	data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
+			(ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
+	data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
+			(ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
+	data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
+			(sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
+	data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
+			(ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
+	data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
+
+	if (AR_SREV_9462_20_OR_LATER(ah)) {
+		/* AR9462 2.0 has an extra descriptor word (time based
+		 * discard) compared to other chips */
+		REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
+		wow_ka_data_word0 = AR_WOW_TXBUF(13);
+	} else {
+		wow_ka_data_word0 = AR_WOW_TXBUF(12);
+	}
+
+	for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
+		REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
+
+}
+
+void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
+				u8 *user_mask, int pattern_count,
+				int pattern_len)
+{
+	int i;
+	u32 pattern_val, mask_val;
+	u32 set, clr;
+
+	/* FIXME: should check count by querying the hardware capability */
+	if (pattern_count >= MAX_NUM_PATTERN)
+		return;
+
+	REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
+
+	/* set the registers for pattern */
+	for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
+		memcpy(&pattern_val, user_pattern, 4);
+		REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
+			  pattern_val);
+		user_pattern += 4;
+	}
+
+	/* set the registers for mask */
+	for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
+		memcpy(&mask_val, user_mask, 4);
+		REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
+		user_mask += 4;
+	}
+
+	/* set the pattern length to be matched
+	 *
+	 * AR_WOW_LENGTH1_REG1
+	 * bit 31:24 pattern 0 length
+	 * bit 23:16 pattern 1 length
+	 * bit 15:8 pattern 2 length
+	 * bit 7:0 pattern 3 length
+	 *
+	 * AR_WOW_LENGTH1_REG2
+	 * bit 31:24 pattern 4 length
+	 * bit 23:16 pattern 5 length
+	 * bit 15:8 pattern 6 length
+	 * bit 7:0 pattern 7 length
+	 *
+	 * the below logic writes out the new
+	 * pattern length for the corresponding
+	 * pattern_count, while masking out the
+	 * other fields
+	 */
+
+	ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
+
+	if (!AR_SREV_9285_12_OR_LATER(ah))
+		return;
+
+	if (pattern_count < 4) {
+		/* Pattern 0-3 uses AR_WOW_LENGTH1 register */
+		set = (pattern_len & AR_WOW_LENGTH_MAX) <<
+		       AR_WOW_LEN1_SHIFT(pattern_count);
+		clr = AR_WOW_LENGTH1_MASK(pattern_count);
+		REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
+	} else {
+		/* Pattern 4-7 uses AR_WOW_LENGTH2 register */
+		set = (pattern_len & AR_WOW_LENGTH_MAX) <<
+		       AR_WOW_LEN2_SHIFT(pattern_count);
+		clr = AR_WOW_LENGTH2_MASK(pattern_count);
+		REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
+	}
+
+}
+EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
+
+u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
+{
+	u32 wow_status = 0;
+	u32 val = 0, rval;
+	u32 set, clr;
+
+	/*
+	 * read the WoW status register to know
+	 * the wakeup reason
+	 */
+	rval = REG_READ(ah, AR_WOW_PATTERN);
+	val = AR_WOW_STATUS(rval);
+
+	/*
+	 * mask only the WoW events that we have enabled. Sometimes
+	 * we have spurious WoW events from the AR_WOW_PATTERN
+	 * register. This mask will clean it up.
+	 */
+
+	val &= ah->wow_event_mask;
+
+	if (val) {
+
+		if (val & AR_WOW_MAGIC_PAT_FOUND)
+			wow_status |= AH_WOW_MAGIC_PATTERN_EN;
+
+		if (AR_WOW_PATTERN_FOUND(val))
+			wow_status |= AH_WOW_USER_PATTERN_EN;
+
+		if (val & AR_WOW_KEEP_ALIVE_FAIL)
+			wow_status |= AH_WOW_LINK_CHANGE;
+
+		if (val & AR_WOW_BEACON_FAIL)
+			wow_status |= AH_WOW_BEACON_MISS;
+
+	}
+
+	/*
+	 * set and clear WOW_PME_CLEAR registers for the chip to
+	 * generate next wow signal.
+	 * disable D3 before accessing other registers ?
+	 */
+
+	set = AR_PMCTRL_WOW_PME_CLR;
+	clr = AR_PMCTRL_PWR_STATE_D1D3;
+	/* do we need to check the bit value 0x01000000 (7-10) ?? */
+	REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
+
+	/*
+	 * clear all events
+	 */
+	REG_WRITE(ah, AR_WOW_PATTERN,
+		  AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
+
+	/*
+	 * tie reset register for AR9002 family of chipsets
+	 * NB: not tieing it back might have some repurcussions.
+	 */
+
+	if (!AR_SREV_9300_20_OR_LATER(ah)) {
+		set = AR_WA_UNTIE_RESET_EN |
+		      AR_WA_POR_SHORT |
+		      AR_WA_RESET_EN;
+		REG_SET_BIT(ah, AR_WA, set);
+	}
+
+
+	/*
+	 * restore the beacon threshold to init value
+	 */
+	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
+
+	/*
+	 * Restore the way the PCI-E reset, Power-On-Reset, external
+	 * PCIE_POR_SHORT pins are tied to its original value.
+	 * Previously just before WoW sleep, we untie the PCI-E
+	 * reset to our Chip's Power On Reset so that any PCI-E
+	 * reset from the bus will not reset our chip
+	 */
+
+	if (AR_SREV_9280_20_OR_LATER(ah) && ah->is_pciexpress)
+		ath9k_hw_configpcipowersave(ah, false);
+
+	ah->wow_event_mask = 0;
+
+	return wow_status;
+}
+EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
+
+/* delay of 4 ms between two keep alive frames */
+#define KA_DELAY	4
+#define KAL_TIMEOUT	900
+void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
+{
+	u32 wow_event_mask;
+	u32 set, clr;
+
+	/*
+	 * wow_event_mask is a mask to the AR_WOW_PATTERN register to
+	 * indicate which WoW events we have enabled. The WoW events
+	 * are from the 'pattern_enable' in this function and
+	 * 'pattern_count' of ath9k_hw_wow_apply_pattern()
+	 */
+
+	wow_event_mask = ah->wow_event_mask;
+
+	/*
+	 * Untie Power-on-Reset from the PCI-E-Reset. When we are in
+	 * WOW sleep, we do want the Reset from the PCI-E to disturb
+	 * our hw state
+	 */
+
+	if (ah->is_pciexpress) {
+
+		/*
+		 * we need to untie the internal POR (power-on-reset)
+		 * to the external PCI-E reset. We also need to tie
+		 * the PCI-E Phy reset to the PCI-E reset.
+		 */
+
+		if (AR_SREV_9300_20_OR_LATER(ah)) {
+			set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
+			clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
+			REG_RMW(ah, AR_WA, set, clr);
+		} else {
+			if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
+				set = AR9285_WA_DEFAULT;
+			else
+				set = AR9280_WA_DEFAULT;
+
+			/*
+			 * In AR9280 and AR9285, bit 14 in WA register
+			 * (disable L1) should only be set when device
+			 * enters D3 state and be cleared when device
+			 * comes back to D0
+			 */
+
+			if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
+				set = set | AR_WA_D3_L1_DISABLE;
+
+			clr = AR_WA_UNTIE_RESET_EN;
+			set |= AR_WA_RESET_EN | AR_WA_POR_SHORT;
+			REG_RMW(ah, AR_WA, set, clr);
+
+			/*
+			 * for WoW sleep, we reprogram the SerDes so that the
+			 * PLL and CLK REQ are both enabled. This uses more
+			 * power but otherwise WoW sleep is unstable and the
+			 * chip may disappear.
+			 */
+
+			if (AR_SREV_9285_12_OR_LATER(ah))
+				ath9k_hw_config_serdes_wow_sleep(ah);
+
+		}
+	}
+
+	/*
+	 * set the power states appropriately and enable PME
+	 */
+	set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
+	      AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
+
+	/*
+	 * set and clear WOW_PME_CLEAR registers for the chip
+	 * to generate next wow signal.
+	 */
+	REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
+	clr = AR_PMCTRL_WOW_PME_CLR;
+	REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
+
+	/*
+	 * Setup for:
+	 *	- beacon misses
+	 *	- magic pattern
+	 *	- keep alive timeout
+	 *	- pattern matching
+	 */
+
+	/*
+	 * Program default values for pattern backoff, aifs/slot/KAL count,
+	 * beacon miss timeout, KAL timeout, etc.
+	 */
+
+	set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
+	REG_SET_BIT(ah, AR_WOW_PATTERN, set);
+
+	set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
+	      AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
+	      AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
+	REG_SET_BIT(ah, AR_WOW_COUNT, set);
+
+	if (pattern_enable & AH_WOW_BEACON_MISS)
+		set = AR_WOW_BEACON_TIMO;
+	/* We are not using beacon miss, program a large value */
+	else
+		set = AR_WOW_BEACON_TIMO_MAX;
+
+	REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
+
+	/*
+	 * Keep alive timo in ms except AR9280
+	 */
+	if (!pattern_enable || AR_SREV_9280(ah))
+		set = AR_WOW_KEEP_ALIVE_NEVER;
+	else
+		set = KAL_TIMEOUT * 32;
+
+	REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
+
+	/*
+	 * Keep alive delay in us. based on 'power on clock',
+	 * therefore in usec
+	 */
+	set = KA_DELAY * 1000;
+	REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
+
+	/*
+	 * Create keep alive pattern to respond to beacons
+	 */
+	ath9k_wow_create_keep_alive_pattern(ah);
+
+	/*
+	 * Configure MAC WoW Registers
+	 */
+
+	set = 0;
+	/* Send keep alive timeouts anyway */
+	clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
+
+	if (pattern_enable & AH_WOW_LINK_CHANGE)
+		wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
+	else
+		set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
+
+	/*
+	 * FIXME: For now disable keep alive frame
+	 * failure. This seems to sometimes trigger
+	 * unnecessary wake up with AR9485 chipsets.
+	 */
+	set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
+
+	REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
+
+
+	/*
+	 * we are relying on a bmiss failure. ensure we have
+	 * enough threshold to prevent false positives
+	 */
+	REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
+		      AR_WOW_BMISSTHRESHOLD);
+
+	set = 0;
+	clr = 0;
+
+	if (pattern_enable & AH_WOW_BEACON_MISS) {
+		set = AR_WOW_BEACON_FAIL_EN;
+		wow_event_mask |= AR_WOW_BEACON_FAIL;
+	} else {
+		clr = AR_WOW_BEACON_FAIL_EN;
+	}
+
+	REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
+
+	set = 0;
+	clr = 0;
+	/*
+	 * Enable the magic packet registers
+	 */
+	if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
+		set = AR_WOW_MAGIC_EN;
+		wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
+	} else {
+		clr = AR_WOW_MAGIC_EN;
+	}
+	set |= AR_WOW_MAC_INTR_EN;
+	REG_RMW(ah, AR_WOW_PATTERN, set, clr);
+
+	/*
+	 * For AR9285 and later version of chipsets
+	 * enable WoW pattern match for packets less
+	 * than 256 bytes for all patterns
+	 */
+	if (AR_SREV_9285_12_OR_LATER(ah))
+		REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
+			  AR_WOW_PATTERN_SUPPORTED);
+
+	/*
+	 * Set the power states appropriately and enable PME
+	 */
+	clr = 0;
+	set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
+	      AR_PMCTRL_PWR_PM_CTRL_ENA;
+	/*
+	 * This is needed for AR9300 chipsets to wake-up
+	 * the host.
+	 */
+	if (AR_SREV_9300_20_OR_LATER(ah))
+		clr = AR_PCIE_PM_CTRL_ENA;
+
+	REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
+
+	if (AR_SREV_9462(ah)) {
+		/*
+		 * this is needed to prevent the chip waking up
+		 * the host within 3-4 seconds with certain
+		 * platform/BIOS. the fix it to enable
+		 * D1 & D3 to match original definition and
+		 * also match the OTP value. Anyway this
+		 * is more related to SW WOW.
+		 */
+		clr = AR_PMCTRL_PWR_STATE_D1D3;
+		REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
+
+		set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
+		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
+	}
+
+
+
+	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
+
+	if (AR_SREV_9300_20_OR_LATER(ah)) {
+		/* to bring down WOW power low margin */
+		set = BIT(13);
+		REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
+		/* HW WoW */
+		clr = BIT(5);
+		REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
+	}
+
+	ath9k_hw_set_powermode_wow_sleep(ah);
+	ah->wow_event_mask = wow_event_mask;
+}
+EXPORT_SYMBOL(ath9k_hw_wow_enable);
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 08/10] ath: Add Wake-on-Wireless debug mask

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

to help the developers and users to debug/know
whats happening with WoW

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index c54b7d3..9bd0248 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -215,6 +215,7 @@ void ath_printk(const char *level, const struct ath_common *common,
  *	used exclusively for WLAN-BT coexistence starting from
  *	AR9462.
  * @ATH_DBG_DFS: radar datection
+ * @ATH_DBG_WOW: Wake on Wireless
  * @ATH_DBG_ANY: enable all debugging
  *
  * The debug level is used to control the amount and type of debugging output
@@ -242,6 +243,7 @@ enum ATH_DEBUG {
 	ATH_DBG_BSTUCK		= 0x00008000,
 	ATH_DBG_MCI		= 0x00010000,
 	ATH_DBG_DFS		= 0x00020000,
+	ATH_DBG_WOW		= 0x00040000,
 	ATH_DBG_ANY		= 0xffffffff
 };
 
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 09/10] ath9k: Add WoW related mac80211 callbacks

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

add suspend/resume/set_wakeup callbacks to the driver

*suspend

- bail out only if all the conditions for configuring WoW.
  is fine, currently multivif case is not handled
- check for associated state.
- map wow triggers from user space data.
- add deauth/disassoc pattern and user defined pattern,
  for the later a list is maintained.
- store the interrupt mask before suspend, enabled beacon
  miss interrupt for WoW.
- configure WoW in the hardware by calling ath9k_hw_wow_enable.

*resume

- restore the interrupts based on the interrupt mask
  stored before suspend.
- call ath9k_hw_wow_wakeup to configure/restore the hardware.
- after wow wakeup clear away WoW events and query the
  WoW wakeup reason from the status register

*set_wakeup

- to call 'device_set_wakeup_enable' from cfg80211/mac80211
  when wow is configured and as per Rafael/Johannnes the
  right way to do so rather in the driver suspend/resume
  call back

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/ath9k.h |    9 +
 drivers/net/wireless/ath/ath9k/init.c  |    1 +
 drivers/net/wireless/ath/ath9k/main.c  |  390 ++++++++++++++++++++++++++++++++
 3 files changed, 400 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 4c530e5..43de1e1 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -518,6 +518,14 @@ struct ath9k_wow_info {
 	struct list_head wow_patterns;
 };
 
+#ifdef CONFIG_PM_SLEEP
+void ath_wow_cleanup(struct ath_softc *sc);
+#else
+static inline void ath_wow_cleanup(struct ath_softc *sc)
+{
+}
+#endif
+
 /********************/
 /*   LED Control    */
 /********************/
@@ -719,6 +727,7 @@ struct ath_softc {
 	struct ath_ant_comb ant_comb;
 	u8 ant_tx, ant_rx;
 	struct dfs_pattern_detector *dfs_detector;
+	u32 wow_enabled;
 
 #ifdef CONFIG_PM_SLEEP
 	bool wow_got_bmiss_intr;
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 576f808..a5a4794 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -885,6 +885,7 @@ void ath9k_deinit_device(struct ath_softc *sc)
 	ath9k_ps_restore(sc);
 
 	ieee80211_unregister_hw(hw);
+	ath_wow_cleanup(sc);
 	ath_rx_cleanup(sc);
 	ath_tx_cleanup(sc);
 	ath9k_deinit_softc(sc);
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 85f9ab4..cbb5bb8 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -486,6 +486,17 @@ irqreturn_t ath_isr(int irq, void *dev)
 	if (status & SCHED_INTR)
 		sched = true;
 
+#ifdef CONFIG_PM_SLEEP
+	if (status & ATH9K_INT_BMISS) {
+		if (sc->wow_sleep_proc_intr) {
+			ath_dbg(common, ANY, "during WoW we got a BMISS\n");
+			sc->wow_got_bmiss_intr = true;
+			sc->wow_sleep_proc_intr = false;
+		}
+	ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
+	}
+#endif
+
 	/*
 	 * If a FATAL or RXORN interrupt is received, we have to reset the
 	 * chip immediately.
@@ -2069,6 +2080,379 @@ static void ath9k_get_et_stats(struct ieee80211_hw *hw,
 #endif
 
 
+#ifdef CONFIG_PM_SLEEP
+
+void ath_wow_cleanup(struct ath_softc *sc)
+{
+	struct ath9k_wow_info *wow_info = &sc->wow_info;
+	struct ath9k_wow_pattern *wow_pattern  = NULL, *tmp;
+
+	if (!(sc->wow_enabled & AH_WOW_USER_PATTERN_EN))
+		return;
+
+	list_for_each_entry_safe(wow_pattern, tmp,
+				 &wow_info->wow_patterns, list) {
+
+		list_del(&wow_pattern->list);
+		kfree(wow_pattern);
+	}
+
+}
+
+static void ath9k_wow_map_triggers(struct ath_softc *sc,
+				   struct cfg80211_wowlan *wowlan,
+				   u32 *wow_triggers)
+{
+	if (wowlan->disconnect)
+		*wow_triggers |= AH_WOW_LINK_CHANGE |
+				 AH_WOW_BEACON_MISS;
+	if (wowlan->magic_pkt)
+		*wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
+
+	if (wowlan->n_patterns)
+		*wow_triggers |= AH_WOW_USER_PATTERN_EN;
+
+	sc->wow_enabled = *wow_triggers;
+
+}
+
+static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
+{
+	struct ath_hw *ah = sc->sc_ah;
+	struct ath_common *common = ath9k_hw_common(ah);
+	struct ath9k_hw_capabilities *pcaps = &ah->caps;
+	int pattern_count = 0;
+	int i, byte_cnt;
+	u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
+	u8 dis_deauth_mask[MAX_PATTERN_SIZE];
+
+	memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
+	memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
+
+	/*
+	 * Create Dissassociate / Deauthenticate packet filter
+	 *
+	 *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
+	 *  +--------------+----------+---------+--------+--------+----
+	 *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
+	 *  +--------------+----------+---------+--------+--------+----
+	 *
+	 * The above is the management frame format for disassociate/
+	 * deauthenticate pattern, from this we need to match the first byte
+	 * of 'Frame Control' and DA, SA, and BSSID fields
+	 * (skipping 2nd byte of FC and Duration feild.
+	 *
+	 * Disassociate pattern
+	 * --------------------
+	 * Frame control = 00 00 1010
+	 * DA, SA, BSSID = x:x:x:x:x:x
+	 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
+	 *			    | x:x:x:x:x:x  -- 22 bytes
+	 *
+	 * Deauthenticate pattern
+	 * ----------------------
+	 * Frame control = 00 00 1100
+	 * DA, SA, BSSID = x:x:x:x:x:x
+	 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
+	 *			    | x:x:x:x:x:x  -- 22 bytes
+	 */
+
+	/* Create Disassociate Pattern first */
+
+	byte_cnt = 0;
+
+	/* Fill out the mask with all FF's */
+
+	for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
+		dis_deauth_mask[i] = 0xff;
+
+	/* copy the first byte of frame control field */
+	dis_deauth_pattern[byte_cnt] = 0xa0;
+	byte_cnt++;
+
+	/* skip 2nd byte of frame control and Duration field */
+	byte_cnt += 3;
+
+	/*
+	 * need not match the destination mac address, it can be a broadcast
+	 * mac address or an unicast to this station
+	 */
+	byte_cnt += 6;
+
+	/* copy the source mac address */
+	memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
+
+	byte_cnt += 6;
+
+	/* copy the bssid, its same as the source mac address */
+
+	memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
+
+	/* Create Disassociate pattern mask */
+
+	if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
+
+		if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
+			/*
+			 * for AR9280, because of hardware limitation, the
+			 * first 4 bytes have to be matched for all patterns.
+			 * the mask for disassociation and de-auth pattern
+			 * matching need to enable the first 4 bytes.
+			 * also the duration field needs to be filled.
+			 */
+			dis_deauth_mask[0] = 0xf0;
+
+			/*
+			 * fill in duration field
+			 FIXME: what is the exact value ?
+			 */
+			dis_deauth_pattern[2] = 0xff;
+			dis_deauth_pattern[3] = 0xff;
+		} else {
+			dis_deauth_mask[0] = 0xfe;
+		}
+
+		dis_deauth_mask[1] = 0x03;
+		dis_deauth_mask[2] = 0xc0;
+	} else {
+		dis_deauth_mask[0] = 0xef;
+		dis_deauth_mask[1] = 0x3f;
+		dis_deauth_mask[2] = 0x00;
+		dis_deauth_mask[3] = 0xfc;
+	}
+
+	ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
+
+	ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
+				   pattern_count, byte_cnt);
+
+	pattern_count++;
+	/*
+	 * for de-authenticate pattern, only the first byte of the frame
+	 * control field gets changed from 0xA0 to 0xC0
+	 */
+	dis_deauth_pattern[0] = 0xC0;
+
+	ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
+				   pattern_count, byte_cnt);
+
+}
+
+static void ath9k_wow_add_pattern(struct ath_softc *sc,
+				  struct cfg80211_wowlan *wowlan)
+{
+	struct ath_hw *ah = sc->sc_ah;
+	struct ath9k_wow_info *wow_info = &sc->wow_info;
+	struct ath9k_wow_pattern *wow_pattern = NULL;
+	struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
+	int mask_len;
+	s8 i = 0;
+
+	if (!wowlan->n_patterns)
+		return;
+
+	/*
+	 * Clear existing WoW patterns.
+	 */
+	ath_wow_cleanup(sc);
+
+	/*
+	 * Add the new user configured patterns
+	 */
+	for (i = 0; i < wowlan->n_patterns; i++) {
+
+		wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
+
+		if (!wow_pattern)
+			return;
+
+		mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
+		memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
+		memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
+		memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
+		       patterns[i].pattern_len);
+		memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
+		wow_pattern->pattern_len = patterns[i].pattern_len;
+
+		list_add_tail(&wow_pattern->list, &wow_info->wow_patterns);
+		wow_info->num_of_patterns = i + 2;
+		/*
+		 * just need to take care of deauth and disssoc pattern,
+		 * make sure we don't overwrite them.
+		 */
+
+		ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
+					   wow_pattern->mask_bytes,
+					   wow_info->num_of_patterns,
+					   wow_pattern->pattern_len);
+
+	}
+
+}
+
+static int ath9k_suspend(struct ieee80211_hw *hw,
+			 struct cfg80211_wowlan *wowlan)
+{
+	struct ath_softc *sc = hw->priv;
+	struct ath_hw *ah = sc->sc_ah;
+	struct ath_common *common = ath9k_hw_common(ah);
+	u32 wow_triggers_enabled = 0;
+	int ret = 0;
+
+	mutex_lock(&sc->mutex);
+
+	ath_cancel_work(sc);
+	del_timer_sync(&common->ani.timer);
+	del_timer_sync(&sc->rx_poll_timer);
+
+	if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
+		ath_dbg(common, ANY, "Device not present\n");
+		ret = -EINVAL;
+		goto fail_wow;
+	}
+
+	if (WARN_ON(!wowlan)) {
+		ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
+		ret = -EINVAL;
+		goto fail_wow;
+	}
+
+	if (!device_can_wakeup(sc->dev)) {
+		ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
+		ret = 1;
+		goto fail_wow;
+	}
+
+	/*
+	 * none of the sta vifs are associated
+	 * and we are not currently handling multivif
+	 * cases, for instance we have to seperately
+	 * configure 'keep alive frame' for each
+	 * STA.
+	 */
+
+	if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
+		ath_dbg(common, WOW, "None of the STA vifs are associated\n");
+		ret = 1;
+		goto fail_wow;
+	}
+
+	if (sc->nvifs > 1) {
+		ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
+		ret = 1;
+		goto fail_wow;
+	}
+
+	ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
+
+	ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
+		wow_triggers_enabled);
+
+	ath9k_ps_wakeup(sc);
+
+	ath9k_stop_btcoex(sc);
+
+	/*
+	 * Enable wake up on recieving disassoc/deauth
+	 * frame by default.
+	 */
+	ath9k_wow_add_disassoc_deauth_pattern(sc);
+
+	if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
+		ath9k_wow_add_pattern(sc, wowlan);
+
+	spin_lock_bh(&sc->sc_pcu_lock);
+	/*
+	 * To avoid false wake, we enable beacon miss interrupt only
+	 * when we go to sleep. We save the current interrupt mask
+	 * so we can restore it after the system wakes up
+	 */
+	sc->wow_intr_before_sleep = ah->imask;
+	ah->imask &= ~ATH9K_INT_GLOBAL;
+	ath9k_hw_disable_interrupts(ah);
+	ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
+	ath9k_hw_set_interrupts(ah);
+	ath9k_hw_enable_interrupts(ah);
+
+	spin_unlock_bh(&sc->sc_pcu_lock);
+
+	/*
+	 * we can now sync irq and kill any running tasklets, since we already
+	 * disabled interrupts and not holding a spin lock
+	 */
+	synchronize_irq(sc->irq);
+	tasklet_kill(&sc->intr_tq);
+
+	ath9k_hw_wow_enable(ah, wow_triggers_enabled);
+
+	ath9k_ps_restore(sc);
+	ath_dbg(common, ANY, "WoW enabled in ath9k\n");
+	sc->wow_sleep_proc_intr = true;
+
+fail_wow:
+	mutex_unlock(&sc->mutex);
+	return ret;
+}
+
+static int ath9k_resume(struct ieee80211_hw *hw)
+{
+	struct ath_softc *sc = hw->priv;
+	struct ath_hw *ah = sc->sc_ah;
+	struct ath_common *common = ath9k_hw_common(ah);
+	u32 wow_status;
+
+	mutex_lock(&sc->mutex);
+
+	ath9k_ps_wakeup(sc);
+
+	spin_lock_bh(&sc->sc_pcu_lock);
+
+	ath9k_hw_disable_interrupts(ah);
+	ah->imask = sc->wow_intr_before_sleep;
+	ath9k_hw_set_interrupts(ah);
+	ath9k_hw_enable_interrupts(ah);
+
+	spin_unlock_bh(&sc->sc_pcu_lock);
+
+	wow_status = ath9k_hw_wow_wakeup(ah);
+
+	if (sc->wow_got_bmiss_intr) {
+		/*
+		 * some devices may not pick beacon miss
+		 * as the reason they woke up so we add
+		 * that here for that shortcoming.
+		 */
+		wow_status |= AH_WOW_BEACON_MISS;
+		sc->wow_got_bmiss_intr = false;
+		ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep");
+	}
+
+	if (wow_status) {
+		ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
+			ath9k_hw_wow_event_to_string(wow_status), wow_status);
+	}
+
+	ath_restart_work(sc);
+	ath9k_start_btcoex(sc);
+
+	ath9k_ps_restore(sc);
+	mutex_unlock(&sc->mutex);
+
+	return 0;
+}
+
+static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
+{
+	struct ath_softc *sc = hw->priv;
+
+	mutex_lock(&sc->mutex);
+	device_init_wakeup(sc->dev, 1);
+	device_set_wakeup_enable(sc->dev, enabled);
+	mutex_unlock(&sc->mutex);
+}
+
+#endif
+
 struct ieee80211_ops ath9k_ops = {
 	.tx 		    = ath9k_tx,
 	.start 		    = ath9k_start,
@@ -2098,6 +2482,12 @@ struct ieee80211_ops ath9k_ops = {
 	.set_antenna	    = ath9k_set_antenna,
 	.get_antenna	    = ath9k_get_antenna,
 
+#ifdef CONFIG_PM_SLEEP
+	.suspend	    = ath9k_suspend,
+	.resume		    = ath9k_resume,
+	.set_wakeup	    = ath9k_set_wakeup,
+#endif
+
 #ifdef CONFIG_ATH9K_DEBUGFS
 	.get_et_sset_count  = ath9k_get_et_sset_count,
 	.get_et_stats  = ath9k_get_et_stats,
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 10/10] ath9k: do not disable hardware while wow is enabled

[Mohammed Shafi Shajakhan]

From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>

Hardware needs to be AWAKE and should maintain association
with the AP to process WoW triggers any time

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel at qca.qualcomm.com
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/pci.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index aa0e83a..87b89d5 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -313,6 +313,9 @@ static int ath_pci_suspend(struct device *device)
 	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 	struct ath_softc *sc = hw->priv;
 
+	if (sc->wow_enabled)
+		return 0;
+
 	/* The device has to be moved to FULLSLEEP forcibly.
 	 * Otherwise the chip never moved to full sleep,
 	 * when no interface is up.
-- 
1.7.0.4

[ath9k-devel] [PATCH v3 01/10] ath9k_hw: Add register definitions for WoW support

[Sujith Manoharan]

Mohammed Shafi Shajakhan wrote:
> From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
> 
> *MAC WoW registers
> 
> back-off shift, MAC interrupt enable, magic packet enable,
> pattern match enable, aifs, slot wait period, keep alive
> frame failure count, beacon fail enable, beacon timeout,
> keep alive timeout, auto keep alive disable,
> keep alive fail disable and their corresponding
> status registers. keep alive frame delay,
> pattern end/byte offsets, transmit buffers for
> keep alive frames and storing the user patterns
> 
> *Power Management Control registers
> 
> pme_d3cold_vaux, host_pme_enable, aux_pwr_detect,
> power_state_mask, wow_pme_clear

The commit log could be trimmed to just say "various WoW registers".

> +/* AR_WOW_PATTERN register values */
> +#define AR_WOW_BACK_OFF_SHIFT(x)	((x & 0xf) << 28) /* in usecs */
> +#define AR_WOW_MAC_INTR_EN		0x00040000
> +#define AR_WOW_MAGIC_EN			0x00010000
> +#define AR_WOW_PATTERN_EN(x)		(x & 0xff)
> +#define AR_WOW_PAT_FOUND_SHIFT	8
> +#define AR_WOW_PATTERN_FOUND(x)		(x & (0xff << AR_WOW_PAT_FOUND_SHIFT))
> +#define AR_WOW_PATTERN_FOUND_MASK	((0xff) << AR_WOW_PAT_FOUND_SHIFT)
> +#define AR_WOW_MAGIC_PAT_FOUND		0x00020000
> +#define AR_WOW_MAC_INTR			0x00080000
> +#define AR_WOW_KEEP_ALIVE_FAIL		0x00100000
> +#define AR_WOW_BEACON_FAIL		0x00200000
> +
> +#define AR_WOW_STATUS(x)		(x & (AR_WOW_PATTERN_FOUND_MASK | \
> +					      AR_WOW_MAGIC_PAT_FOUND	| \
> +					      AR_WOW_KEEP_ALIVE_FAIL	| \
> +					      AR_WOW_BEACON_FAIL))
> +#define AR_WOW_CLEAR_EVENTS(x)		(x & ~(AR_WOW_PATTERN_EN(0xff) | \
> +					       AR_WOW_MAGIC_EN | \
> +					       AR_WOW_MAC_INTR_EN | \
> +					       AR_WOW_BEACON_FAIL | \
> +					       AR_WOW_KEEP_ALIVE_FAIL))
> +

Indentation is off in many places, please fix it.

Sujith

[ath9k-devel] [PATCH v3 04/10] ath9k_hw: advertise WoW support for capable chipsets

[Sujith Manoharan]

Mohammed Shafi Shajakhan wrote:
> From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
> 
> support WoW for all chipsets starting from AR9280, AR9285, AR9287,
> AR9380, AR9382, AR9485, AR9462. Really all hardware may not support
> WoW even though the flag is set and the WoW working depends on
> your laptop, BIOS apart from the hardware.
> 
> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
> Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
> Cc: vadivel at qca.qualcomm.com
> Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
> ---
>  drivers/net/wireless/ath/ath9k/hw.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
> index a42c26f..041d797 100644
> --- a/drivers/net/wireless/ath/ath9k/hw.c
> +++ b/drivers/net/wireless/ath/ath9k/hw.c
> @@ -2572,6 +2572,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
>  	}
>  
>  
> +	if (AR_SREV_9280_20_OR_LATER(ah)) {
> +		pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
> +				 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
> +
> +		if (AR_SREV_9280(ah))
> +			pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
> +	}
> +

I don't think this is a good idea - please enable WoW only for cards that
we have actually tested.

Sujith

[ath9k-devel] [PATCH v3 07/10] ath9k_hw: Add hardware code for WoW

[Sujith Manoharan]

Mohammed Shafi Shajakhan wrote:
> +static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
> +{
> +	struct ath_common *common = ath9k_hw_common(ah);
> +
> +	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
> +
> +	/* set rx disable bit */
> +	REG_WRITE(ah, AR_CR, AR_CR_RXD);
> +
> +	if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
> +		ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
> +			REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
> +		return;
> +	} else {
> +		if (!AR_SREV_9300_20_OR_LATER(ah))
> +			REG_WRITE(ah, AR_RXDP, 0x0);
> +	}
> +
> +	/* AR9280 WoW has sleep issue, do not set it to sleep */
> +	if (AR_SREV_9280_20(ah))
> +		return;
> +
> +	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
> +}

This function needs proper error handling.

> +#define KAL_FRAME_LEN		28
> +#define KAL_FRAME_TYPE		0x2 /* data frame */
> +#define KAL_FRAME_SUB_TYPE	0x4 /* null data frame */
> +#define KAL_DURATION_ID		0x3d
> +#define KAL_NUM_DATA_WORDS	6
> +#define KAL_NUM_DESC_WORDS	12

Move these to a header file ?

> +static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
> +{
> +	struct ath_common *common = ath9k_hw_common(ah);
> +	u32 frame_len = KAL_FRAME_LEN;
> +	u32 tpc = MAX_RATE_POWER;
> +	u32 antenna_mode = 1;
> +	u32 transmit_rate;
> +	u32 frame_type = KAL_FRAME_TYPE; /* frame type -> data */
> +	u32 sub_type = KAL_FRAME_SUB_TYPE; /* subtype -> NULL data */
> +	u32 to_ds = 1;
> +	u32 duration_id = KAL_DURATION_ID;
> +	u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
> +	u32 ctl[13] = {0};
> +	u32 data_word[KAL_NUM_DATA_WORDS];
> +	u8 i;
> +	u32 wow_ka_data_word0;

Most of the variables can be replaced by direct usage of the macros.

> +	memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
> +	memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);

These too, the variables from 'common' can be used directly.

> +	if (ah->curchan->channelFlags & CHANNEL_CCK)
> +		transmit_rate = 0x1b; /* CCK_1M hardware value for this rate */
> +	else
> +		transmit_rate = 0xb; /* OFDM_6M hardware value for this rate */

We don't use CHANNEL_CCK, so this can be trimmed and 'transmit_rate' removed.

> +void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
> +				u8 *user_mask, int pattern_count,
> +				int pattern_len)
> +{
> +	int i;
> +	u32 pattern_val, mask_val;
> +	u32 set, clr;
> +
> +	/* FIXME: should check count by querying the hardware capability */
> +	if (pattern_count >= MAX_NUM_PATTERN)
> +		return;
> +
> +	REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
> +
> +	/* set the registers for pattern */
> +	for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
> +		memcpy(&pattern_val, user_pattern, 4);
> +		REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
> +			  pattern_val);
> +		user_pattern += 4;
> +	}
> +
> +	/* set the registers for mask */
> +	for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
> +		memcpy(&mask_val, user_mask, 4);
> +		REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
> +		user_mask += 4;
> +	}

Shouldn't this use MAX_PATTERN_MASK_SIZE ? Also, better error checking for this
function.

> +	set = AR_PMCTRL_WOW_PME_CLR;
> +	clr = AR_PMCTRL_PWR_STATE_D1D3;
> +	/* do we need to check the bit value 0x01000000 (7-10) ?? */
> +	REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
> +
> +	/*
> +	 * clear all events
> +	 */
> +	REG_WRITE(ah, AR_WOW_PATTERN,
> +		  AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
> +
> +	/*
> +	 * tie reset register for AR9002 family of chipsets
> +	 * NB: not tieing it back might have some repurcussions.
> +	 */
> +
> +	if (!AR_SREV_9300_20_OR_LATER(ah)) {
> +		set = AR_WA_UNTIE_RESET_EN |
> +		      AR_WA_POR_SHORT |
> +		      AR_WA_RESET_EN;
> +		REG_SET_BIT(ah, AR_WA, set);
> +	}

What's the point in the set/clr variables ?

> +	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

This doesn't seem right, you are overwriting the value that is set when a
station is associated.

> +void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
> +{
> +	/*
> +	 * set the power states appropriately and enable PME
> +	 */
> +	set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
> +	      AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
> +
> +	/*
> +	 * set and clear WOW_PME_CLEAR registers for the chip
> +	 * to generate next wow signal.
> +	 */
> +	REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
> +	clr = AR_PMCTRL_WOW_PME_CLR;
> +	REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
> +
> +	/*
> +	 * Setup for:
> +	 *	- beacon misses
> +	 *	- magic pattern
> +	 *	- keep alive timeout
> +	 *	- pattern matching
> +	 */
> +
> +	/*
> +	 * Program default values for pattern backoff, aifs/slot/KAL count,
> +	 * beacon miss timeout, KAL timeout, etc.
> +	 */
> +
> +	set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
> +	REG_SET_BIT(ah, AR_WOW_PATTERN, set);
> +
> +	set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
> +	      AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
> +	      AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
> +	REG_SET_BIT(ah, AR_WOW_COUNT, set);
> +
> +	if (pattern_enable & AH_WOW_BEACON_MISS)
> +		set = AR_WOW_BEACON_TIMO;
> +	/* We are not using beacon miss, program a large value */
> +	else
> +		set = AR_WOW_BEACON_TIMO_MAX;
> +
> +	REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
> +
> +	/*
> +	 * Keep alive timo in ms except AR9280
> +	 */
> +	if (!pattern_enable || AR_SREV_9280(ah))
> +		set = AR_WOW_KEEP_ALIVE_NEVER;
> +	else
> +		set = KAL_TIMEOUT * 32;
> +
> +	REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
> +
> +	/*
> +	 * Keep alive delay in us. based on 'power on clock',
> +	 * therefore in usec
> +	 */
> +	set = KA_DELAY * 1000;
> +	REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
> +
> +	/*
> +	 * Create keep alive pattern to respond to beacons
> +	 */
> +	ath9k_wow_create_keep_alive_pattern(ah);
> +
> +	/*
> +	 * Configure MAC WoW Registers
> +	 */
> +
> +	set = 0;
> +	/* Send keep alive timeouts anyway */
> +	clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
> +
> +	if (pattern_enable & AH_WOW_LINK_CHANGE)
> +		wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
> +	else
> +		set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
> +
> +	/*
> +	 * FIXME: For now disable keep alive frame
> +	 * failure. This seems to sometimes trigger
> +	 * unnecessary wake up with AR9485 chipsets.
> +	 */
> +	set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
> +
> +	REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
> +
> +
> +	/*
> +	 * we are relying on a bmiss failure. ensure we have
> +	 * enough threshold to prevent false positives
> +	 */
> +	REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
> +		      AR_WOW_BMISSTHRESHOLD);
> +
> +	set = 0;
> +	clr = 0;
> +
> +	if (pattern_enable & AH_WOW_BEACON_MISS) {
> +		set = AR_WOW_BEACON_FAIL_EN;
> +		wow_event_mask |= AR_WOW_BEACON_FAIL;
> +	} else {
> +		clr = AR_WOW_BEACON_FAIL_EN;
> +	}
> +
> +	REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
> +
> +	set = 0;
> +	clr = 0;
> +	/*
> +	 * Enable the magic packet registers
> +	 */
> +	if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
> +		set = AR_WOW_MAGIC_EN;
> +		wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
> +	} else {
> +		clr = AR_WOW_MAGIC_EN;
> +	}
> +	set |= AR_WOW_MAC_INTR_EN;
> +	REG_RMW(ah, AR_WOW_PATTERN, set, clr);
> +
> +	/*
> +	 * For AR9285 and later version of chipsets
> +	 * enable WoW pattern match for packets less
> +	 * than 256 bytes for all patterns
> +	 */
> +	if (AR_SREV_9285_12_OR_LATER(ah))
> +		REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
> +			  AR_WOW_PATTERN_SUPPORTED);
> +
> +	/*
> +	 * Set the power states appropriately and enable PME
> +	 */
> +	clr = 0;
> +	set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
> +	      AR_PMCTRL_PWR_PM_CTRL_ENA;
> +	/*
> +	 * This is needed for AR9300 chipsets to wake-up
> +	 * the host.
> +	 */
> +	if (AR_SREV_9300_20_OR_LATER(ah))
> +		clr = AR_PCIE_PM_CTRL_ENA;
> +
> +	REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
> +
> +	if (AR_SREV_9462(ah)) {
> +		/*
> +		 * this is needed to prevent the chip waking up
> +		 * the host within 3-4 seconds with certain
> +		 * platform/BIOS. the fix it to enable
> +		 * D1 & D3 to match original definition and
> +		 * also match the OTP value. Anyway this
> +		 * is more related to SW WOW.
> +		 */
> +		clr = AR_PMCTRL_PWR_STATE_D1D3;
> +		REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
> +
> +		set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
> +		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
> +	}
> +
> +
> +
> +	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
> +
> +	if (AR_SREV_9300_20_OR_LATER(ah)) {
> +		/* to bring down WOW power low margin */
> +		set = BIT(13);
> +		REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
> +		/* HW WoW */
> +		clr = BIT(5);
> +		REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
> +	}
> +
> +	ath9k_hw_set_powermode_wow_sleep(ah);
> +	ah->wow_event_mask = wow_event_mask;
> +}
> +EXPORT_SYMBOL(ath9k_hw_wow_enable);

This function badly needs a cleanup. The set/clr variables are kinda ugly and
the routine would become quite simpler if the various registers are programmed
directly.

Sujith

[ath9k-devel] [PATCH v3 09/10] ath9k: Add WoW related mac80211 callbacks

[Sujith Manoharan]

Mohammed Shafi Shajakhan wrote:
> +#ifdef CONFIG_PM_SLEEP
> +
> +void ath_wow_cleanup(struct ath_softc *sc)
> +{
> +	struct ath9k_wow_info *wow_info = &sc->wow_info;
> +	struct ath9k_wow_pattern *wow_pattern  = NULL, *tmp;
> +
> +	if (!(sc->wow_enabled & AH_WOW_USER_PATTERN_EN))
> +		return;
> +
> +	list_for_each_entry_safe(wow_pattern, tmp,
> +				 &wow_info->wow_patterns, list) {
> +
> +		list_del(&wow_pattern->list);
> +		kfree(wow_pattern);
> +	}
> +
> +}

I am slightly unclear about this...

> +	u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
> +	u8 dis_deauth_mask[MAX_PATTERN_SIZE];
> +
> +	memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
> +	memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);

MAX_PATTERN_MASK_SIZE ?

> +		memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
> +		memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);

The memset() calls are not needed, but maybe I am missing something -
why exactly are we maintaining a list of patterns in the driver ?
Can't the patterns be retrieved as part of the suspend() callback
and just programmed in the HW ?

> +
> +	if (!device_can_wakeup(sc->dev)) {
> +		ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
> +		ret = 1;
> +		goto fail_wow;
> +	}

Can this happen ?

> +	/*
> +	 * we can now sync irq and kill any running tasklets, since we already
> +	 * disabled interrupts and not holding a spin lock
> +	 */
> +	synchronize_irq(sc->irq);
> +	tasklet_kill(&sc->intr_tq);
> +
> +	ath9k_hw_wow_enable(ah, wow_triggers_enabled);
> +
> +	ath9k_ps_restore(sc);
> +	ath_dbg(common, ANY, "WoW enabled in ath9k\n");
> +	sc->wow_sleep_proc_intr = true;

This is racy with the ISR, atomic ops can be used instead, since this
(along with wow_got_bmiss_intr) are just boolean variables.

> +static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
> +{
> +	struct ath_softc *sc = hw->priv;
> +
> +	mutex_lock(&sc->mutex);
> +	device_init_wakeup(sc->dev, 1);
> +	device_set_wakeup_enable(sc->dev, enabled);
> +	mutex_unlock(&sc->mutex);
> +}

device_init_wakeup() should be part of the probe sequence, I think.

Sujith

[ath9k-devel] [PATCH v3 01/10] ath9k_hw: Add register definitions for WoW support

[Mohammed Shafi Shajakhan]

Hi Sujith,

On Monday 25 June 2012 10:49 PM, Sujith Manoharan wrote:
> Mohammed Shafi Shajakhan wrote:
>> From: Mohammed Shafi Shajakhan<mohammed@qca.qualcomm.com>
>>
>> *MAC WoW registers
>>
>> back-off shift, MAC interrupt enable, magic packet enable,
>> pattern match enable, aifs, slot wait period, keep alive
>> frame failure count, beacon fail enable, beacon timeout,
>> keep alive timeout, auto keep alive disable,
>> keep alive fail disable and their corresponding
>> status registers. keep alive frame delay,
>> pattern end/byte offsets, transmit buffers for
>> keep alive frames and storing the user patterns
>>
>> *Power Management Control registers
>>
>> pme_d3cold_vaux, host_pme_enable, aux_pwr_detect,
>> power_state_mask, wow_pme_clear
>
> The commit log could be trimmed to just say "various WoW registers".
>
>> +/* AR_WOW_PATTERN register values */
>> +#define AR_WOW_BACK_OFF_SHIFT(x)	((x&  0xf)<<  28) /* in usecs */
>> +#define AR_WOW_MAC_INTR_EN		0x00040000
>> +#define AR_WOW_MAGIC_EN			0x00010000
>> +#define AR_WOW_PATTERN_EN(x)		(x&  0xff)
>> +#define AR_WOW_PAT_FOUND_SHIFT	8
>> +#define AR_WOW_PATTERN_FOUND(x)		(x&  (0xff<<  AR_WOW_PAT_FOUND_SHIFT))
>> +#define AR_WOW_PATTERN_FOUND_MASK	((0xff)<<  AR_WOW_PAT_FOUND_SHIFT)
>> +#define AR_WOW_MAGIC_PAT_FOUND		0x00020000
>> +#define AR_WOW_MAC_INTR			0x00080000
>> +#define AR_WOW_KEEP_ALIVE_FAIL		0x00100000
>> +#define AR_WOW_BEACON_FAIL		0x00200000
>> +
>> +#define AR_WOW_STATUS(x)		(x&  (AR_WOW_PATTERN_FOUND_MASK | \
>> +					      AR_WOW_MAGIC_PAT_FOUND	| \
>> +					      AR_WOW_KEEP_ALIVE_FAIL	| \
>> +					      AR_WOW_BEACON_FAIL))
>> +#define AR_WOW_CLEAR_EVENTS(x)		(x&  ~(AR_WOW_PATTERN_EN(0xff) | \
>> +					       AR_WOW_MAGIC_EN | \
>> +					       AR_WOW_MAC_INTR_EN | \
>> +					       AR_WOW_BEACON_FAIL | \
>> +					       AR_WOW_KEEP_ALIVE_FAIL))
>> +
>
> Indentation is off in many places, please fix it.
>

thanks, i will check this out.

-- 
thanks,
shafi

[ath9k-devel] [PATCH v3 04/10] ath9k_hw: advertise WoW support for capable chipsets

[Mohammed Shafi Shajakhan]

Hi Sujith,

On Monday 25 June 2012 10:54 PM, Sujith Manoharan wrote:
> Mohammed Shafi Shajakhan wrote:
>> From: Mohammed Shafi Shajakhan<mohammed@qca.qualcomm.com>
>>
>> support WoW for all chipsets starting from AR9280, AR9285, AR9287,
>> AR9380, AR9382, AR9485, AR9462. Really all hardware may not support
>> WoW even though the flag is set and the WoW working depends on
>> your laptop, BIOS apart from the hardware.
>>
>> Cc: Senthil Balasubramanian<senthilb@qca.qualcomm.com>
>> Cc: Rajkumar Manoharan<rmanohar@qca.qualcomm.com>
>> Cc: vadivel at qca.qualcomm.com
>> Signed-off-by: Luis R. Rodriguez<mcgrof@qca.qualcomm.com>
>> Signed-off-by: Mohammed Shafi Shajakhan<mohammed@qca.qualcomm.com>
>> ---
>>   drivers/net/wireless/ath/ath9k/hw.c |    8 ++++++++
>>   1 files changed, 8 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
>> index a42c26f..041d797 100644
>> --- a/drivers/net/wireless/ath/ath9k/hw.c
>> +++ b/drivers/net/wireless/ath/ath9k/hw.c
>> @@ -2572,6 +2572,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
>>   	}
>>
>>
>> +	if (AR_SREV_9280_20_OR_LATER(ah)) {
>> +		pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
>> +				 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
>> +
>> +		if (AR_SREV_9280(ah))
>> +			pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
>> +	}
>> +
>
> I don't think this is a good idea - please enable WoW only for cards that
> we have actually tested.
>

I had tested it in quite a few of cards like AR9280, AR9285,AR9485 with 
wow enabled. Further the hardware was generic, with only quite a few 
changes needed between AR9002 and AR9003. thank you.

-- 
thanks,
shafi

[ath9k-devel] [PATCH v3 07/10] ath9k_hw: Add hardware code for WoW

[Mohammed Shafi Shajakhan]

Hi Sujith,

On Tuesday 26 June 2012 12:14 AM, Sujith Manoharan wrote:
> Mohammed Shafi Shajakhan wrote:
>> +static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
>> +{
>> +	struct ath_common *common = ath9k_hw_common(ah);
>> +
>> +	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
>> +
>> +	/* set rx disable bit */
>> +	REG_WRITE(ah, AR_CR, AR_CR_RXD);
>> +
>> +	if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
>> +		ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
>> +			REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
>> +		return;
>> +	} else {
>> +		if (!AR_SREV_9300_20_OR_LATER(ah))
>> +			REG_WRITE(ah, AR_RXDP, 0x0);
>> +	}
>> +
>> +	/* AR9280 WoW has sleep issue, do not set it to sleep */
>> +	if (AR_SREV_9280_20(ah))
>> +		return;
>> +
>> +	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
>> +}
>
> This function needs proper error handling.

not sure, this seem to be ok while I was reviewing. thanks will check it 
out.


>
>> +#define KAL_FRAME_LEN		28
>> +#define KAL_FRAME_TYPE		0x2 /* data frame */
>> +#define KAL_FRAME_SUB_TYPE	0x4 /* null data frame */
>> +#define KAL_DURATION_ID		0x3d
>> +#define KAL_NUM_DATA_WORDS	6
>> +#define KAL_NUM_DESC_WORDS	12
>
> Move these to a header file ?

thought this was going to be used to the below function alone, will 
check it out. thanks.

>
>> +static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
>> +{
>> +	struct ath_common *common = ath9k_hw_common(ah);
>> +	u32 frame_len = KAL_FRAME_LEN;
>> +	u32 tpc = MAX_RATE_POWER;
>> +	u32 antenna_mode = 1;
>> +	u32 transmit_rate;
>> +	u32 frame_type = KAL_FRAME_TYPE; /* frame type ->  data */
>> +	u32 sub_type = KAL_FRAME_SUB_TYPE; /* subtype ->  NULL data */
>> +	u32 to_ds = 1;
>> +	u32 duration_id = KAL_DURATION_ID;
>> +	u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
>> +	u32 ctl[13] = {0};
>> +	u32 data_word[KAL_NUM_DATA_WORDS];
>> +	u8 i;
>> +	u32 wow_ka_data_word0;
>
> Most of the variables can be replaced by direct usage of the macros.

thanks will check it out.

>
>> +	memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
>> +	memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
>
> These too, the variables from 'common' can be used directly.

ok. i thought it would be more readable by using the sta_mac_addr, 
ap_mac_addr, where these are used in data words, for constructing keep 
alive frames(source address, destination address).

>
>> +	if (ah->curchan->channelFlags&  CHANNEL_CCK)
>> +		transmit_rate = 0x1b; /* CCK_1M hardware value for this rate */
>> +	else
>> +		transmit_rate = 0xb; /* OFDM_6M hardware value for this rate */
>
> We don't use CHANNEL_CCK, so this can be trimmed and 'transmit_rate' removed.

ok will check this out.

>
>> +void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
>> +				u8 *user_mask, int pattern_count,
>> +				int pattern_len)
>> +{
>> +	int i;
>> +	u32 pattern_val, mask_val;
>> +	u32 set, clr;
>> +
>> +	/* FIXME: should check count by querying the hardware capability */
>> +	if (pattern_count>= MAX_NUM_PATTERN)
>> +		return;
>> +
>> +	REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
>> +
>> +	/* set the registers for pattern */
>> +	for (i = 0; i<  MAX_PATTERN_SIZE; i += 4) {
>> +		memcpy(&pattern_val, user_pattern, 4);
>> +		REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
>> +			  pattern_val);
>> +		user_pattern += 4;
>> +	}
>> +
>> +	/* set the registers for mask */
>> +	for (i = 0; i<  MAX_PATTERN_SIZE; i += 4) {
>> +		memcpy(&mask_val, user_mask, 4);
>> +		REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
>> +		user_mask += 4;
>> +	}
>
> Shouldn't this use MAX_PATTERN_MASK_SIZE ? Also, better error checking for this
> function.

thanks, i missed it. will change this.

>
>> +	set = AR_PMCTRL_WOW_PME_CLR;
>> +	clr = AR_PMCTRL_PWR_STATE_D1D3;
>> +	/* do we need to check the bit value 0x01000000 (7-10) ?? */
>> +	REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
>> +
>> +	/*
>> +	 * clear all events
>> +	 */
>> +	REG_WRITE(ah, AR_WOW_PATTERN,
>> +		  AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
>> +
>> +	/*
>> +	 * tie reset register for AR9002 family of chipsets
>> +	 * NB: not tieing it back might have some repurcussions.
>> +	 */
>> +
>> +	if (!AR_SREV_9300_20_OR_LATER(ah)) {
>> +		set = AR_WA_UNTIE_RESET_EN |
>> +		      AR_WA_POR_SHORT |
>> +		      AR_WA_RESET_EN;
>> +		REG_SET_BIT(ah, AR_WA, set);
>> +	}
>
> What's the point in the set/clr variables ?

this is being to done to use REG_RMW_* and REG_SET_BIT* with a quite
few of values being set or cleared. I would just see if i have a better 
option.

>
>> +	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
>
> This doesn't seem right, you are overwriting the value that is set when a
> station is associated.


thanks, i was thinking how can i bring in
  REG_RMW_FIELD(ah, AR_RSSI_THR,
                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
i believe we would do a re-connection and update the same value. will 
check it out. i think it would be 7 or 5.

>
>> +void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
>> +{
>> +	/*
>> +	 * set the power states appropriately and enable PME
>> +	 */
>> +	set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
>> +	      AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
>> +
>> +	/*
>> +	 * set and clear WOW_PME_CLEAR registers for the chip
>> +	 * to generate next wow signal.
>> +	 */
>> +	REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
>> +	clr = AR_PMCTRL_WOW_PME_CLR;
>> +	REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
>> +
>> +	/*
>> +	 * Setup for:
>> +	 *	- beacon misses
>> +	 *	- magic pattern
>> +	 *	- keep alive timeout
>> +	 *	- pattern matching
>> +	 */
>> +
>> +	/*
>> +	 * Program default values for pattern backoff, aifs/slot/KAL count,
>> +	 * beacon miss timeout, KAL timeout, etc.
>> +	 */
>> +
>> +	set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
>> +	REG_SET_BIT(ah, AR_WOW_PATTERN, set);
>> +
>> +	set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
>> +	      AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
>> +	      AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
>> +	REG_SET_BIT(ah, AR_WOW_COUNT, set);
>> +
>> +	if (pattern_enable&  AH_WOW_BEACON_MISS)
>> +		set = AR_WOW_BEACON_TIMO;
>> +	/* We are not using beacon miss, program a large value */
>> +	else
>> +		set = AR_WOW_BEACON_TIMO_MAX;
>> +
>> +	REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
>> +
>> +	/*
>> +	 * Keep alive timo in ms except AR9280
>> +	 */
>> +	if (!pattern_enable || AR_SREV_9280(ah))
>> +		set = AR_WOW_KEEP_ALIVE_NEVER;
>> +	else
>> +		set = KAL_TIMEOUT * 32;
>> +
>> +	REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
>> +
>> +	/*
>> +	 * Keep alive delay in us. based on 'power on clock',
>> +	 * therefore in usec
>> +	 */
>> +	set = KA_DELAY * 1000;
>> +	REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
>> +
>> +	/*
>> +	 * Create keep alive pattern to respond to beacons
>> +	 */
>> +	ath9k_wow_create_keep_alive_pattern(ah);
>> +
>> +	/*
>> +	 * Configure MAC WoW Registers
>> +	 */
>> +
>> +	set = 0;
>> +	/* Send keep alive timeouts anyway */
>> +	clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
>> +
>> +	if (pattern_enable&  AH_WOW_LINK_CHANGE)
>> +		wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
>> +	else
>> +		set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
>> +
>> +	/*
>> +	 * FIXME: For now disable keep alive frame
>> +	 * failure. This seems to sometimes trigger
>> +	 * unnecessary wake up with AR9485 chipsets.
>> +	 */
>> +	set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
>> +
>> +	REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
>> +
>> +
>> +	/*
>> +	 * we are relying on a bmiss failure. ensure we have
>> +	 * enough threshold to prevent false positives
>> +	 */
>> +	REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
>> +		      AR_WOW_BMISSTHRESHOLD);
>> +
>> +	set = 0;
>> +	clr = 0;
>> +
>> +	if (pattern_enable&  AH_WOW_BEACON_MISS) {
>> +		set = AR_WOW_BEACON_FAIL_EN;
>> +		wow_event_mask |= AR_WOW_BEACON_FAIL;
>> +	} else {
>> +		clr = AR_WOW_BEACON_FAIL_EN;
>> +	}
>> +
>> +	REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
>> +
>> +	set = 0;
>> +	clr = 0;
>> +	/*
>> +	 * Enable the magic packet registers
>> +	 */
>> +	if (pattern_enable&  AH_WOW_MAGIC_PATTERN_EN) {
>> +		set = AR_WOW_MAGIC_EN;
>> +		wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
>> +	} else {
>> +		clr = AR_WOW_MAGIC_EN;
>> +	}
>> +	set |= AR_WOW_MAC_INTR_EN;
>> +	REG_RMW(ah, AR_WOW_PATTERN, set, clr);
>> +
>> +	/*
>> +	 * For AR9285 and later version of chipsets
>> +	 * enable WoW pattern match for packets less
>> +	 * than 256 bytes for all patterns
>> +	 */
>> +	if (AR_SREV_9285_12_OR_LATER(ah))
>> +		REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
>> +			  AR_WOW_PATTERN_SUPPORTED);
>> +
>> +	/*
>> +	 * Set the power states appropriately and enable PME
>> +	 */
>> +	clr = 0;
>> +	set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
>> +	      AR_PMCTRL_PWR_PM_CTRL_ENA;
>> +	/*
>> +	 * This is needed for AR9300 chipsets to wake-up
>> +	 * the host.
>> +	 */
>> +	if (AR_SREV_9300_20_OR_LATER(ah))
>> +		clr = AR_PCIE_PM_CTRL_ENA;
>> +
>> +	REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
>> +
>> +	if (AR_SREV_9462(ah)) {
>> +		/*
>> +		 * this is needed to prevent the chip waking up
>> +		 * the host within 3-4 seconds with certain
>> +		 * platform/BIOS. the fix it to enable
>> +		 * D1&  D3 to match original definition and
>> +		 * also match the OTP value. Anyway this
>> +		 * is more related to SW WOW.
>> +		 */
>> +		clr = AR_PMCTRL_PWR_STATE_D1D3;
>> +		REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
>> +
>> +		set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
>> +		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
>> +	}
>> +
>> +
>> +
>> +	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
>> +
>> +	if (AR_SREV_9300_20_OR_LATER(ah)) {
>> +		/* to bring down WOW power low margin */
>> +		set = BIT(13);
>> +		REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
>> +		/* HW WoW */
>> +		clr = BIT(5);
>> +		REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
>> +	}
>> +
>> +	ath9k_hw_set_powermode_wow_sleep(ah);
>> +	ah->wow_event_mask = wow_event_mask;
>> +}
>> +EXPORT_SYMBOL(ath9k_hw_wow_enable);
>
> This function badly needs a cleanup. The set/clr variables are kinda ugly and
> the routine would become quite simpler if the various registers are programmed
> directly.

will check it out if it can be done better.


>
> Sujith


-- 
thanks,
shafi

[ath9k-devel] [PATCH v3 09/10] ath9k: Add WoW related mac80211 callbacks

[Mohammed Shafi Shajakhan]

Hi Sujith,

On Tuesday 26 June 2012 12:51 AM, Sujith Manoharan wrote:
> Mohammed Shafi Shajakhan wrote:
>> +#ifdef CONFIG_PM_SLEEP
>> +
>> +void ath_wow_cleanup(struct ath_softc *sc)
>> +{
>> +	struct ath9k_wow_info *wow_info =&sc->wow_info;
>> +	struct ath9k_wow_pattern *wow_pattern  = NULL, *tmp;
>> +
>> +	if (!(sc->wow_enabled&  AH_WOW_USER_PATTERN_EN))
>> +		return;
>> +
>> +	list_for_each_entry_safe(wow_pattern, tmp,
>> +				&wow_info->wow_patterns, list) {
>> +
>> +		list_del(&wow_pattern->list);
>> +		kfree(wow_pattern);
>> +	}
>> +
>> +}
>
> I am slightly unclear about this...
>
>> +	u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
>> +	u8 dis_deauth_mask[MAX_PATTERN_SIZE];
>> +
>> +	memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
>> +	memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
>
> MAX_PATTERN_MASK_SIZE ?

thanks, filling up 0xff requires MAX_PATTERN_MASK_SIZE.

>
>> +		memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
>> +		memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
>
> The memset() calls are not needed, but maybe I am missing something -
> why exactly are we maintaining a list of patterns in the driver ?
> Can't the patterns be retrieved as part of the suspend() callback
> and just programmed in the HW ?

the user pattern needs bit more stuff, we need to convert it to our chip 
specific format(ie proper 802.11 format), previously there was
a logic of duplicate patterns before programming to HW, where a list in 
the driver was necessary, i removed it to simplify few things.
will check it out if its really needed for any enhancements in future.

>
>> +
>> +	if (!device_can_wakeup(sc->dev)) {
>> +		ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
>> +		ret = 1;
>> +		goto fail_wow;
>> +	}
>
> Can this happen ?

the wow capabilities are initialized only if
device_can_wakeup passes. would check it out if this is needed.

>
>> +	/*
>> +	 * we can now sync irq and kill any running tasklets, since we already
>> +	 * disabled interrupts and not holding a spin lock
>> +	 */
>> +	synchronize_irq(sc->irq);
>> +	tasklet_kill(&sc->intr_tq);
>> +
>> +	ath9k_hw_wow_enable(ah, wow_triggers_enabled);
>> +
>> +	ath9k_ps_restore(sc);
>> +	ath_dbg(common, ANY, "WoW enabled in ath9k\n");
>> +	sc->wow_sleep_proc_intr = true;
>
> This is racy with the ISR, atomic ops can be used instead, since this
> (along with wow_got_bmiss_intr) are just boolean variables.

thanks, will check this out.

>
>> +static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
>> +{
>> +	struct ath_softc *sc = hw->priv;
>> +
>> +	mutex_lock(&sc->mutex);
>> +	device_init_wakeup(sc->dev, 1);
>> +	device_set_wakeup_enable(sc->dev, enabled);
>> +	mutex_unlock(&sc->mutex);
>> +}
>
> device_init_wakeup() should be part of the probe sequence, I think.
>

in v2 i had it in my pci_probe only, but device_init_wakeup seems to 
call device_set_wakeup_enable. we actually set device_set_wakeup_enable 
explicitly to 'true' only when wow triggers are enabled, otherwise
we would set our chip to wakeup capable during pci_probe.

-- 
thanks,
shafi

[ath9k-devel] [PATCH v3 09/10] ath9k: Add WoW related mac80211 callbacks

[Johannes Berg]

On Tue, 2012-06-26 at 10:54 +0530, Mohammed Shafi Shajakhan wrote:

> the user pattern needs bit more stuff, we need to convert it to our chip 
> specific format(ie proper 802.11 format), previously there was
> a logic of duplicate patterns before programming to HW, where a list in 
> the driver was necessary, i removed it to simplify few things.

You might consider adding new API for 802.11-based patterns as the 802.3
patterns could match multiple 802.11 frames etc.

johannes

[ath9k-devel] [PATCH v3 09/10] ath9k: Add WoW related mac80211 callbacks

[Mohammed Shafi Shajakhan]

Hi Johannes,

On Tuesday 26 June 2012 12:20 PM, Johannes Berg wrote:
> On Tue, 2012-06-26 at 10:54 +0530, Mohammed Shafi Shajakhan wrote:
>
>> the user pattern needs bit more stuff, we need to convert it to our chip
>> specific format(ie proper 802.11 format), previously there was
>> a logic of duplicate patterns before programming to HW, where a list in
>> the driver was necessary, i removed it to simplify few things.
>
> You might consider adding new API for 802.11-based patterns as the 802.3
> patterns could match multiple 802.11 frames etc.
>

thanks for your suggestion, i shall come with an API to do this.

-- 
thanks,
shafi

[ath9k-devel] [PATCH v3 00/10] Add support for WOW in ath9k

[John W. Linville]

Is there going to be a repost of this series?  It looked like Sujith
had a number of concerns.

On Mon, Jun 25, 2012 at 07:42:49PM +0530, Mohammed Shafi Shajakhan wrote:
> From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
> 
> Add support for hardware WoW in ath9k. Magic-packet,
> beacon loss triggers, deauth/disassoc patterns
> (a special case of user pattern) are tested with 
> AR9485. User pattern needs a bit of investigation
> on parsing to appropriate 802.11 format.
> we will do more rigorous testing and address bugs.
> Also we will quickly validate with chipsets like
> AR9462, AR9280, AR9285, AR9287 for any bugs.
> 
> Thanks a lot to Vadivel for providing me the hardware and
> inputs to test. Thanks to Rajkumar, Russell for
> their invaluable help. Thanks to Aeolous, Senthil and
> Sujith, Raja. Thanks a lot to Luis for providing the complete
> frame work for WoW in his initial wow patches.
> 
> Mohammed Shafi Shajakhan (10):
>   ath9k_hw: Add register definitions for WoW support
>   ath9k: Add definitions and structures to support WoW
>   ath9k_hw: Add WoW hardware capability flags
>   ath9k_hw: advertise WoW support for capable chipsets
>   ath9k: advertise supported WoW flags to upper layer
>   ath9k_hw: INI changes for WoW for AR9002 chipsets
>   ath9k_hw: Add hardware code for WoW
>   ath: Add Wake-on-Wireless debug mask
>   ath9k: Add WoW related mac80211 callbacks
>   ath9k: do not disable hardware while wow is enabled
> 
>  drivers/net/wireless/ath/ath.h                   |    2 +
>  drivers/net/wireless/ath/ath9k/Makefile          |    1 +
>  drivers/net/wireless/ath/ath9k/ar9002_hw.c       |    5 +
>  drivers/net/wireless/ath/ath9k/ar9002_initvals.h |   14 +
>  drivers/net/wireless/ath/ath9k/ath9k.h           |   28 ++
>  drivers/net/wireless/ath/ath9k/hw.c              |    8 +
>  drivers/net/wireless/ath/ath9k/hw.h              |   68 +++
>  drivers/net/wireless/ath/ath9k/init.c            |   17 +
>  drivers/net/wireless/ath/ath9k/main.c            |  390 +++++++++++++++
>  drivers/net/wireless/ath/ath9k/pci.c             |    3 +
>  drivers/net/wireless/ath/ath9k/reg.h             |  145 ++++++-
>  drivers/net/wireless/ath/ath9k/wow.c             |  560 ++++++++++++++++++++++
>  12 files changed, 1240 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/net/wireless/ath/ath9k/wow.c
> 
> 

-- 
John W. Linville		Someday the world will need a hero, and you
linville at tuxdriver.com			might be all we have.  Be ready.

[ath9k-devel] [PATCH v3 00/10] Add support for WOW in ath9k

[Mohammed Shafi Shajakhan]

Hi John,

On Saturday 07 July 2012 01:05 AM, John W. Linville wrote:
> Is there going to be a repost of this series?  It looked like Sujith
> had a number of concerns.

yes, need to send a v4, that should address most of his concerns.
never got some time to look back, should start now! thanks.

>
> On Mon, Jun 25, 2012 at 07:42:49PM +0530, Mohammed Shafi Shajakhan wrote:
>> From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
>>
>> Add support for hardware WoW in ath9k. Magic-packet,
>> beacon loss triggers, deauth/disassoc patterns
>> (a special case of user pattern) are tested with
>> AR9485. User pattern needs a bit of investigation
>> on parsing to appropriate 802.11 format.
>> we will do more rigorous testing and address bugs.
>> Also we will quickly validate with chipsets like
>> AR9462, AR9280, AR9285, AR9287 for any bugs.
>>
>> Thanks a lot to Vadivel for providing me the hardware and
>> inputs to test. Thanks to Rajkumar, Russell for
>> their invaluable help. Thanks to Aeolous, Senthil and
>> Sujith, Raja. Thanks a lot to Luis for providing the complete
>> frame work for WoW in his initial wow patches.
>>
>> Mohammed Shafi Shajakhan (10):
>>    ath9k_hw: Add register definitions for WoW support
>>    ath9k: Add definitions and structures to support WoW
>>    ath9k_hw: Add WoW hardware capability flags
>>    ath9k_hw: advertise WoW support for capable chipsets
>>    ath9k: advertise supported WoW flags to upper layer
>>    ath9k_hw: INI changes for WoW for AR9002 chipsets
>>    ath9k_hw: Add hardware code for WoW
>>    ath: Add Wake-on-Wireless debug mask
>>    ath9k: Add WoW related mac80211 callbacks
>>    ath9k: do not disable hardware while wow is enabled
>>
>>   drivers/net/wireless/ath/ath.h                   |    2 +
>>   drivers/net/wireless/ath/ath9k/Makefile          |    1 +
>>   drivers/net/wireless/ath/ath9k/ar9002_hw.c       |    5 +
>>   drivers/net/wireless/ath/ath9k/ar9002_initvals.h |   14 +
>>   drivers/net/wireless/ath/ath9k/ath9k.h           |   28 ++
>>   drivers/net/wireless/ath/ath9k/hw.c              |    8 +
>>   drivers/net/wireless/ath/ath9k/hw.h              |   68 +++
>>   drivers/net/wireless/ath/ath9k/init.c            |   17 +
>>   drivers/net/wireless/ath/ath9k/main.c            |  390 +++++++++++++++
>>   drivers/net/wireless/ath/ath9k/pci.c             |    3 +
>>   drivers/net/wireless/ath/ath9k/reg.h             |  145 ++++++-
>>   drivers/net/wireless/ath/ath9k/wow.c             |  560 ++++++++++++++++++++++
>>   12 files changed, 1240 insertions(+), 1 deletions(-)
>>   create mode 100644 drivers/net/wireless/ath/ath9k/wow.c
>>
>>
>


-- 
thanks,
shafi

[ath9k-devel] [PATCH v3 01/10] ath9k_hw: Add register definitions for WoW support

[Mohammed Shafi]

On Tue, Jun 26, 2012 at 9:58 AM, Mohammed Shafi Shajakhan
<mohammed@qca.qualcomm.com> wrote:
> Hi Sujith,
>
>
> On Monday 25 June 2012 10:49 PM, Sujith Manoharan wrote:
>>
>> Mohammed Shafi Shajakhan wrote:
>>>
>>> From: Mohammed Shafi Shajakhan<mohammed@qca.qualcomm.com>
>>>
>>> *MAC WoW registers
>>>
>>> back-off shift, MAC interrupt enable, magic packet enable,
>>> pattern match enable, aifs, slot wait period, keep alive
>>> frame failure count, beacon fail enable, beacon timeout,
>>> keep alive timeout, auto keep alive disable,
>>> keep alive fail disable and their corresponding
>>> status registers. keep alive frame delay,
>>> pattern end/byte offsets, transmit buffers for
>>> keep alive frames and storing the user patterns
>>>
>>> *Power Management Control registers
>>>
>>> pme_d3cold_vaux, host_pme_enable, aux_pwr_detect,
>>> power_state_mask, wow_pme_clear
>>
>>
>> The commit log could be trimmed to just say "various WoW registers".
>>
>>> +/* AR_WOW_PATTERN register values */
>>> +#define AR_WOW_BACK_OFF_SHIFT(x)       ((x&  0xf)<<  28) /* in usecs */
>>>
>>> +#define AR_WOW_MAC_INTR_EN             0x00040000
>>> +#define AR_WOW_MAGIC_EN                        0x00010000
>>> +#define AR_WOW_PATTERN_EN(x)           (x&  0xff)
>>> +#define AR_WOW_PAT_FOUND_SHIFT 8
>>> +#define AR_WOW_PATTERN_FOUND(x)                (x&  (0xff<<
>>> AR_WOW_PAT_FOUND_SHIFT))
>>>
>>> +#define AR_WOW_PATTERN_FOUND_MASK      ((0xff)<<
>>> AR_WOW_PAT_FOUND_SHIFT)
>>> +#define AR_WOW_MAGIC_PAT_FOUND         0x00020000
>>> +#define AR_WOW_MAC_INTR                        0x00080000
>>> +#define AR_WOW_KEEP_ALIVE_FAIL         0x00100000
>>> +#define AR_WOW_BEACON_FAIL             0x00200000
>>> +
>>> +#define AR_WOW_STATUS(x)               (x&  (AR_WOW_PATTERN_FOUND_MASK |
>>> \
>>>
>>> +                                             AR_WOW_MAGIC_PAT_FOUND    |
>>> \
>>> +                                             AR_WOW_KEEP_ALIVE_FAIL    |
>>> \
>>> +                                             AR_WOW_BEACON_FAIL))
>>> +#define AR_WOW_CLEAR_EVENTS(x)         (x&  ~(AR_WOW_PATTERN_EN(0xff) |
>>> \
>>>
>>> +                                              AR_WOW_MAGIC_EN | \
>>> +                                              AR_WOW_MAC_INTR_EN | \
>>> +                                              AR_WOW_BEACON_FAIL | \
>>> +                                              AR_WOW_KEEP_ALIVE_FAIL))
>>> +
>>
>>
>> Indentation is off in many places, please fix it.
>>
>

Lindent seems to complain about few of the comments after macros,
fixing them causes above 80 line stuff
will check this out if there is anything else missing

>
> --
> thanks,
> shafi
>
> --
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-- 
thanks,
shafi