From: Michael Buesch <mb@bu3sch.de>
To: b43-dev@lists.infradead.org
Subject: [14e4:4315] Fatal DMA errors on Dell Vostro 1310 (Celeron M540)
Date: Sun, 4 Apr 2010 18:22:03 +0100 [thread overview]
Message-ID: <201004041922.03439.mb@bu3sch.de> (raw)
In-Reply-To: <4BB8C93C.1050807@lwfinger.net>
On Sunday 04 April 2010 19:15:40 Larry Finger wrote:
> On 04/04/2010 03:24 AM, Michael Buesch wrote:
> > On Sunday 04 April 2010 06:59:25 Larry Finger wrote:
> >> If (chip id is 0x4311 AND chip revision is 2) OR chip id is 0x4312
> >> Maskset SSB_IMCFGLO with mask ~(SSB_IMCFGLO_SERTO |
> >> SSB_IMCFGLO_REQTO) and set with 3
> >
> > Note that we do the IMCFGLO timeout fixups in b43. So I think the fixup
> > should be implemented there.
>
> As the change only affecxts b43, your suggestion is good.
>
> Any idea what IM and TM stand for in the backplane register names?
I don't know. The values are timeout values for data transactions on the SSB
bus between the cores. So these values certainly are related to MMIO and/or
DMA timeouts.
--
Greetings, Michael.
next prev parent reply other threads:[~2010-04-04 17:22 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-02 17:11 [14e4:4315] Fatal DMA errors on Dell Vostro 1310 (Celeron M540) Myhailo Danylenko
2010-04-02 18:04 ` Larry Finger
2010-04-03 9:57 ` Myhailo Danylenko
2010-04-03 16:03 ` Larry Finger
2010-04-03 16:15 ` Gábor Stefanik
2010-04-03 16:15 ` Gábor Stefanik
2010-04-03 18:00 ` Michael Buesch
2010-04-03 22:35 ` Gábor Stefanik
2010-04-04 4:59 ` Larry Finger
2010-04-04 7:03 ` richardvoigt at gmail.com
2010-04-04 14:51 ` Larry Finger
2010-04-04 8:24 ` Michael Buesch
2010-04-04 17:15 ` Larry Finger
2010-04-04 17:22 ` Michael Buesch [this message]
2011-04-19 10:18 ` Rafał Miłecki
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