From mboxrd@z Thu Jan  1 00:00:00 1970
From: Larry Finger <Larry.Finger@lwfinger.net>
Date: Tue, 19 Oct 2010 12:02:37 -0500
Subject: PIO mode
In-Reply-To: <20101019162258.GO1593@home.pavel.comp>
References: <20101010072158.GV1593@home.pavel.comp>
	<AANLkTinYvvk0mYTgKu2gJziLSEoZnMm491wUbZ4BO_Sf@mail.gmail.com>
	<20101010170311.GW1593@home.pavel.comp>
	<AANLkTinQiguGK3YaVb=bqt9n3gCZ-=pgLoc40vRqrN=Q@mail.gmail.com>
	<20101013065845.GG1593@home.pavel.comp>
	<4CBB7A46.6040507@lwfinger.net>
	<20101018041103.GK1593@home.pavel.comp>
	<4CBCA6BC.6080605@lwfinger.net>
	<20101019004331.GN1593@home.pavel.comp>
	<4CBDC183.9020101@lwfinger.net>
	<20101019162258.GO1593@home.pavel.comp>
Message-ID: <4CBDCF2D.60900@lwfinger.net>
List-Id: <b43-dev.lists.infradead.org>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: b43-dev@lists.infradead.org

Paul,

On 10/19/2010 11:22 AM, Paul Fertser wrote:

I do have all the logs you posted.

> MARK 680.950958 Read dword 0xCE035801 from 0x40, devfn: 0
> MARK 680.950966 Wrote dword 0xCE030001 to 0x40, devfn: 0
> 
> And indeed there's code (in the free part of the wl driver) responsible for
> that. Adding that to ssb right after pci_set_master doesn't help though :|

Byte 0x41 of the configuration space is the RETRY_TIMEOUT register. Clearing it
is supposed to keep PCI Tx retries from interfering with C3 CPU state. Similar
code appears in ath9k, ipw2100 and ipw2200 drivers. I think we have tried that
patch in the past, but perhaps the code should be added just in case it might
affect some CPU/device combinations.

Larry