* Re: USB On PCM043?
From: Jerry Kirk @ 2012-07-19 20:56 UTC (permalink / raw)
To: barebox
In-Reply-To: <20120719161139.GB30009@pengutronix.de>
> > We have been attempting to get USB Host mode working under Barebox(2012-07-0)
> > a PCM043 platform (i.mx35), but we are having a bit of trouble.
>
> Could it be that the USB clock operates at the wrong rate? I think it
> should be 60MHz.
We're not certain how to verify the clock setting for USB in Barebox.
We have used "dump_clocks" but are not certain which of these clocks
the USB clock is derived from. We think we have it set to the same
settings as the Eukrea board.
Do you know of anyone that has used USB on the pcm043 board?
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* [PATCH] serial_ns16550: change the driver's name
From: Antony Pavlov @ 2012-07-20 5:46 UTC (permalink / raw)
To: barebox
The name "serial_ns16550" is not handy because the devices
will have the names like "serial_ns165500", "serial_ns165501",
"serial_ns165502" etc.
The names like "ns16550_serial0" and "ns16550_serial1" look
much better.
Also it is reasonable to make serial driver's names unification.
E.g. see the names for drivers in drivers/serial directory:
"netx_serial",
"mpc5xxx_serial",
"altera_serial",
"s3c_serial",
"imx_serial",
"pxa_serial",
"blackfin_serial",
"stm_serial",
"pl010_serial",
and even "g_serial" in ./drivers/usb/gadget/serial.c
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
drivers/serial/serial_ns16550.c | 2 +-
include/driver.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 820aac5..1248bd6 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -263,7 +263,7 @@ static int ns16550_probe(struct device_d *dev)
* @brief Driver registration structure
*/
static struct driver_d ns16550_serial_driver = {
- .name = "serial_ns16550",
+ .name = "ns16550_serial",
.probe = ns16550_probe,
};
diff --git a/include/driver.h b/include/driver.h
index 7d597b4..0a8dc8e 100644
--- a/include/driver.h
+++ b/include/driver.h
@@ -226,7 +226,7 @@ struct NS16550_plat;
static inline struct device_d *add_ns16550_device(int id, resource_size_t start,
resource_size_t size, int flags, struct NS16550_plat *pdata)
{
- return add_generic_device("serial_ns16550", id, NULL, start, size,
+ return add_generic_device("ns16550_serial", id, NULL, start, size,
IORESOURCE_MEM | flags, pdata);
}
--
1.7.10
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [PATCH 1/3] ARM/Samsung: be able to include the nand header multiple times
From: Juergen Beisert @ 2012-07-20 6:56 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342767377-24735-1-git-send-email-jbe@pengutronix.de>
This is required in preparation for the following patches.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/include/mach/s3c24xx-nand.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
index acd78b8..fa88da1 100644
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
@@ -18,6 +18,9 @@
*
*/
+#ifndef MACH_S3C24XX_NAND_H
+# define MACH_S3C24XX_NAND_H
+
#ifdef CONFIG_S3C_NAND_BOOT
extern void s3c24x0_nand_load_image(void*, int, int);
#endif
@@ -52,3 +55,5 @@ struct s3c24x0_nand_platform_data {
* @file
* @brief Basic declaration to use the s3c24x0 NAND driver
*/
+
+#endif /* MACH_S3C24XX_NAND_H */
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [PATCH 3/3] NAND/Samsung: remove a leftover from architeture clean ups
From: Juergen Beisert @ 2012-07-20 6:56 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342767377-24735-1-git-send-email-jbe@pengutronix.de>
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
drivers/mtd/nand/Makefile | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 4179618..1dcfb76 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -15,5 +15,4 @@ obj-$(CONFIG_NAND_IMX) += nand_imx.o
obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
-obj-$(CONFIG_NAND_S3C24X0) += nand_s3c2410.o
obj-$(CONFIG_NAND_MXS) += nand_mxs.o
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [PATCH/master] ARM/Samsung: A required fix and a cleanup
From: Juergen Beisert @ 2012-07-20 6:56 UTC (permalink / raw)
To: barebox
Some fixes and cleanups for master related to boards based on the Samsung
S3C24XX CPU.
The following changes since commit b78e5fe9f3ce155065831d3aa8a480656a8f53c5:
commands/crc: assert newline after output with big offsets (2012-07-17 20:41:17 +0200)
are available in the git repository at:
git://git.pengutronix.de/git/jbe/barebox.git for_master_s3c24xx_runtime_fix_and_cleanup
for you to fetch changes up to b47220d7f70df9191fc456dbcaeaa6ead72c6c02:
NAND/Samsung: remove a leftover from architeture clean ups (2012-07-20 08:41:35 +0200)
----------------------------------------------------------------
Juergen Beisert (3):
ARM/Samsung: be able to include the nand header multiple times
ARM/Samsung: unify device registration for the S3C24XX SoCs
NAND/Samsung: remove a leftover from architeture clean ups
arch/arm/boards/a9m2410/a9m2410.c | 7 ++-
arch/arm/boards/a9m2440/a9m2440.c | 7 ++-
arch/arm/boards/mini2440/mini2440.c | 16 +++---
.../mach-samsung/include/mach/devices-s3c24xx.h | 55 ++++++++++++++++++++
arch/arm/mach-samsung/include/mach/s3c24xx-nand.h | 5 ++
drivers/mtd/nand/Makefile | 1 -
6 files changed, 72 insertions(+), 19 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* [PATCH 2/3] ARM/Samsung: unify device registration for the S3C24XX SoCs
From: Juergen Beisert @ 2012-07-20 6:56 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342767377-24735-1-git-send-email-jbe@pengutronix.de>
Barebox crashes since it has trouble with a resource size of 0. Most of the
S3C24XX based platforms crashes at runtime and can't use devices with resource
sizes of 0 anymore. This patch fix it by unifying the device registration for
all current Barebox's S3C24XX based platforms.
- A9M2410 and A9M2440 compile time tested only.
- Mini2440 also runtime tested.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 7 ++-
arch/arm/boards/a9m2440/a9m2440.c | 7 ++-
arch/arm/boards/mini2440/mini2440.c | 16 +++---
.../mach-samsung/include/mach/devices-s3c24xx.h | 55 ++++++++++++++++++++
4 files changed, 67 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index eaafdbd..e2044a9 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -32,6 +32,7 @@
#include <partition.h>
#include <nand.h>
#include <io.h>
+#include <mach/devices-s3c24xx.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
@@ -109,8 +110,7 @@ static int a9m2410_devices_init(void)
writel(reg, S3C_MISCCR);
/* ----------- the devices the boot loader should work with -------- */
- add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
- 0, IORESOURCE_MEM, &nand_info);
+ s3c24xx_add_nand(&nand_info);
/*
* SMSC 91C111 network controller on the baseboard
* connected to CS line 1 and interrupt line
@@ -145,8 +145,7 @@ void __bare_init nand_boot(void)
static int a9m2410_console_init(void)
{
- add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
- S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+ s3c24xx_add_uart1();
return 0;
}
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 1d20248..8975c15 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -32,6 +32,7 @@
#include <partition.h>
#include <nand.h>
#include <io.h>
+#include <mach/devices-s3c24xx.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
@@ -129,8 +130,7 @@ static int a9m2440_devices_init(void)
writel(reg, S3C_MISCCR);
/* ----------- the devices the boot loader should work with -------- */
- add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE, 0,
- IORESOURCE_MEM, &nand_info);
+ s3c24xx_add_nand(&nand_info);
/*
* cs8900 network controller onboard
* Connected to CS line 5 + A24 and interrupt line EINT9,
@@ -164,8 +164,7 @@ void __bare_init nand_boot(void)
static int a9m2440_console_init(void)
{
- add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
- S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+ s3c24xx_add_uart1();
return 0;
}
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 3d3b820..3523949 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -39,6 +39,7 @@
#include <io.h>
#include <mach/gpio.h>
#include <mach/s3c-iomap.h>
+#include <mach/devices-s3c24xx.h>
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-mci.h>
@@ -297,8 +298,7 @@ static int mini2440_devices_init(void)
reg |= 0x10000;
writel(reg, S3C_MISCCR);
- add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
- 0, IORESOURCE_MEM, &nand_info);
+ s3c24xx_add_nand(&nand_info);
add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
IORESOURCE_MEM_16BIT, &dm9000_data);
@@ -312,12 +312,9 @@ static int mini2440_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
- add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0,
- IORESOURCE_MEM, &mci_data);
- add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0,
- IORESOURCE_MEM, &s3c24x0_fb_data);
- add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
- IORESOURCE_MEM, NULL);
+ s3c24xx_add_mci(&mci_data);
+ s3c24xx_add_fb(&s3c24x0_fb_data);
+ s3c24xx_add_ohci();
armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);
@@ -344,8 +341,7 @@ static int mini2440_console_init(void)
s3c_gpio_mode(GPH2_TXD0);
s3c_gpio_mode(GPH3_RXD0);
- add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
- S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+ s3c24xx_add_uart1();
return 0;
}
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
new file mode 100644
index 0000000..51fd9a1
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef INCLUDE_MACH_DEVICES_S3C24XX_H
+# define INCLUDE_MACH_DEVICES_S3C24XX_H
+
+#include <driver.h>
+#include <mach/s3c24xx-iomap.h>
+#include <mach/s3c24xx-nand.h>
+#include <mach/s3c-mci.h>
+#include <mach/s3c24xx-fb.h>
+
+static inline void s3c24xx_add_nand(struct s3c24x0_nand_platform_data *d)
+{
+ add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL,
+ S3C24X0_NAND_BASE, 0x80, IORESOURCE_MEM, d);
+}
+
+static inline void s3c24xx_add_mci(struct s3c_mci_platform_data *d)
+{
+ add_generic_device("s3c_mci", DEVICE_ID_DYNAMIC, NULL,
+ S3C2410_SDI_BASE, 0x80, IORESOURCE_MEM, d);
+}
+
+static inline void s3c24xx_add_fb(struct s3c_fb_platform_data *d)
+{
+ add_generic_device("s3c_fb", DEVICE_ID_DYNAMIC, NULL,
+ S3C2410_LCD_BASE, 0x80, IORESOURCE_MEM, d);
+}
+
+static inline void s3c24xx_add_ohci(void)
+{
+ add_generic_device("ohci", DEVICE_ID_DYNAMIC, NULL,
+ S3C2410_USB_HOST_BASE, 0x100, IORESOURCE_MEM, NULL);
+}
+
+static inline void s3c24xx_add_uart1(void)
+{
+ add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
+ S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+}
+
+#endif /* INCLUDE_MACH_DEVICES_S3C24XX_H */
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* Re: [PATCH 2/3 v2] gpmc: Add reset to gpmc_generic_init
From: Sascha Hauer @ 2012-07-20 7:20 UTC (permalink / raw)
To: Jan Weitzel; +Cc: barebox
In-Reply-To: <1342684698-3123-1-git-send-email-j.weitzel@phytec.de>
Hi Jan,
On Thu, Jul 19, 2012 at 09:58:18AM +0200, Jan Weitzel wrote:
> Add reset to gpmc_generic_init as proposed by TRM.
> This also fixes some strange timing issue while GPMC Initialization for
> NAND OMAP4460
>
> Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Applied this one. I think the rest needs another round.
Sascha
> ---
> v2: fix timeout endless loop
>
> arch/arm/mach-omap/gpmc.c | 12 +++++++++++-
> 1 files changed, 11 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c
> index 399f68a..b3fa56c 100644
> --- a/arch/arm/mach-omap/gpmc.c
> +++ b/arch/arm/mach-omap/gpmc.c
> @@ -28,6 +28,7 @@
> * MA 02111-1307 USA
> */
> #include <common.h>
> +#include <clock.h>
> #include <init.h>
> #include <io.h>
> #include <mach/silicon.h>
> @@ -48,13 +49,22 @@
> */
> void gpmc_generic_init(unsigned int cfg)
> {
> + uint64_t start;
> unsigned int reg = GPMC_REG(CONFIG7_0);
> char x = 0;
>
> debug("gpmccfg=%x\n", cfg);
> /* Generic Configurations */
> + /* reset gpmc */
> + start = get_time_ns();
> /* No idle, L3 clock free running */
> - writel(0x10, GPMC_REG(SYS_CONFIG));
> + writel(0x12, GPMC_REG(SYS_CONFIG));
> + while (!readl(GPMC_REG(SYS_STATUS)))
> + if (is_timeout(start, MSECOND)) {
> + printf("timeout on gpmc reset\n");
> + break;
> + }
> +
> /* No Timeout */
> writel(0x00, GPMC_REG(TIMEOUT_CONTROL));
> /* No IRQs */
> --
> 1.7.0.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: [PATCH] Added SDR-size auto detection.
From: Sascha Hauer @ 2012-07-20 7:24 UTC (permalink / raw)
To: Juergen Kilb; +Cc: barebox
In-Reply-To: <1342616327-2765-1-git-send-email-J.Kilb@phytec.de>
Hi Jürgen,
Applied this series except the hack alert.
Sascha
On Wed, Jul 18, 2012 at 02:58:44PM +0200, Juergen Kilb wrote:
>
> Signed-off-by: Juergen Kilb <J.Kilb@phytec.de>
> ---
> arch/arm/boards/phycard-a-l1/pca-a-l1.c | 169 +++++++++++++++++++++++--------
> 1 files changed, 125 insertions(+), 44 deletions(-)
>
> diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
> index a388f63..1dc7678 100644
> --- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c
> +++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
> @@ -73,10 +73,82 @@
>
> #define SMC911X_BASE 0x2c000000
>
> +/* Slower full frequency range default timings for x32 operation */
> +#define SDP_SDRC_SHARING 0x00000100
> +/* Diabling power down mode using CKE pin */
> +#define SDP_SDRC_POWER_POP 0x00000081
> +/* rkw - need to find of 90/72 degree recommendation for speed like before. */
> +#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
> + (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
> +
> +/* used to create an array of memory configuartions. */
> +struct sdrc_config {
> + u32 cs_cfg;
> + u32 mcfg;
> + u32 mr;
> + u32 actim_ctrla;
> + u32 actim_ctrlb;
> + u32 rfr_ctrl;
> +} const sdrc_config[] = {
> +/* max cs_size for autodetection, common timing */
> +/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
> +{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
> +/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
> +{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
> +/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
> +{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
> +/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
> +{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
> +};
> +
> /*
> * Boot-time initialization(s)
> */
>
> +/*********************************************************************
> + * init_sdram_ddr() - Init DDR controller.
> + *********************************************************************/
> +void init_sdram_ddr(void)
> +{
> + /* reset sdrc controller */
> + writel(SOFTRESET, SDRC_REG(SYSCONFIG));
> + wait_on_value(1<<0, 1<<0, SDRC_REG(STATUS), 12000000);
> + writel(0, SDRC_REG(SYSCONFIG));
> +
> + /* setup sdrc to ball mux */
> + writel(SDP_SDRC_SHARING, SDRC_REG(SHARING));
> + writel(SDP_SDRC_POWER_POP, SDRC_REG(POWER));
> +
> + /* set up dll */
> + writel(SDP_SDRC_DLLAB_CTRL, SDRC_REG(DLLA_CTRL));
> + sdelay(0x2000); /* give time to lock */
> +
> +}
> +/*********************************************************************
> + * config_sdram_ddr() - Init DDR on dev board.
> + *********************************************************************/
> +void config_sdram_ddr(u8 cs, u8 cfg)
> +{
> +
> + writel(sdrc_config[cfg].mcfg, SDRC_REG(MCFG_0) + (0x30 * cs));
> + writel(sdrc_config[cfg].actim_ctrla, SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
> + writel(sdrc_config[cfg].actim_ctrlb, SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
> + writel(sdrc_config[cfg].rfr_ctrl, SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
> +
> + writel(CMD_NOP, SDRC_REG(MANUAL_0) + (0x30 * cs));
> +
> + sdelay(5000);
> +
> + writel(CMD_PRECHARGE, SDRC_REG(MANUAL_0) + (0x30 * cs));
> + writel(CMD_AUTOREFRESH, SDRC_REG(MANUAL_0) + (0x30 * cs));
> + writel(CMD_AUTOREFRESH, SDRC_REG(MANUAL_0) + (0x30 * cs));
> +
> + /* set mr0 */
> + writel(sdrc_config[cfg].mr, SDRC_REG(MR_0) + (0x30 * cs));
> +
> + sdelay(2000);
> +}
> +
> /**
> * @brief Initialize the SDRC module
> * Initialisation for 1x256MByte but normally
> @@ -85,49 +157,55 @@
> */
> static void pcaal1_sdrc_init(void)
> {
> - /* SDRAM software reset */
> - /* No idle ack and RESET enable */
> - writel(0x1A, SDRC_REG(SYSCONFIG));
> - sdelay(100);
> - /* No idle ack and RESET disable */
> - writel(0x18, SDRC_REG(SYSCONFIG));
> -
> - /* SDRC Sharing register */
> - /* 32-bit SDRAM on data lane [31:0] - CS0 */
> - /* pin tri-stated = 1 */
> - writel(0x00000100, SDRC_REG(SHARING));
> -
> - /* ----- SDRC Registers Configuration --------- */
> - /* SDRC_MCFG0 register */
> - writel(0x03588099, SDRC_REG(MCFG_0));
> -
> - /* SDRC_RFR_CTRL0 register */
> - writel(0x0004e201, SDRC_REG(RFR_CTRL_0));
> -
> - /* SDRC_ACTIM_CTRLA0 register */
> - writel(0x629DB4C6, SDRC_REG(ACTIM_CTRLA_0));
> -
> - /* SDRC_ACTIM_CTRLB0 register */
> - writel(0x00011113, SDRC_REG(ACTIM_CTRLB_0));
> -
> - /* Disble Power Down of CKE due to 1 CKE on combo part */
> - writel(0x00000081, SDRC_REG(POWER));
> -
> - /* SDRC_MANUAL command register */
> - /* NOP command */
> - writel(0x00000000, SDRC_REG(MANUAL_0));
> - /* Precharge command */
> - writel(0x00000001, SDRC_REG(MANUAL_0));
> - /* Auto-refresh command */
> - writel(0x00000002, SDRC_REG(MANUAL_0));
> - /* Auto-refresh command */
> - writel(0x00000002, SDRC_REG(MANUAL_0));
> -
> - /* SDRC MR0 register Burst length=4 */
> - writel(0x00000032, SDRC_REG(MR_0));
> -
> - /* SDRC DLLA control register */
> - writel(0x0000000A, SDRC_REG(DLLA_CTRL));
> + u32 test0, test1;
> + char cfg;
> +
> + init_sdram_ddr();
> +
> + config_sdram_ddr(0, 0); /* 256MByte at CS0 */
> + config_sdram_ddr(1, 0); /* 256MByte at CS1 */
> +
> + test0 = get_ram_size((long *) 0x80000000, SZ_256M);
> + test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
> +
> + /* mask out lower nible, its not tested with
> + in common/memsize.c */
> + test1 &= 0xfffffff0;
> +
> + if ((test1 > 0) && (test1 != test0))
> + hang();
> +
> + cfg = -1; /* illegal configuration found */
> +
> + if (test1 == 0) {
> + init_sdram_ddr();
> + writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), SDRC_REG(MCFG_1));
> +
> + /* 1 x 256MByte */
> + if (test0 == SZ_256M)
> + cfg = 2;
> +
> + if (cfg != -1) {
> + config_sdram_ddr(0, cfg);
> + writel(sdrc_config[(uchar) cfg].cs_cfg, SDRC_REG(CS_CFG));
> + }
> + return;
> + }
> +
> + /* reinit both cs with correct size */
> + /* 2 x 128MByte */
> + if (test0 == SZ_128M)
> + cfg = 1;
> + /* 2 x 256MByte */
> + if (test0 == SZ_256M)
> + cfg = 3;
> +
> + if (cfg != -1) {
> + init_sdram_ddr();
> + writel(sdrc_config[(uchar) cfg].cs_cfg, SDRC_REG(CS_CFG));
> + config_sdram_ddr(0, cfg);
> + config_sdram_ddr(1, cfg);
> + }
> }
>
> /**
> @@ -296,9 +374,12 @@ static int pcaal1_mem_init(void)
> IORESOURCE_MEM_WRITEABLE);
>
> arm_add_mem_device("ram0", OMAP_SDRC_CS0, get_sdr_cs_size(SDRC_CS0_OSET));
> + printf("found %s at SDCS0\n", size_human_readable(get_sdr_cs_size(SDRC_CS0_OSET)));
>
> - if ((get_sdr_cs_size(SDRC_CS1_OSET) != 0) && (get_sdr_cs1_base() != OMAP_SDRC_CS0))
> + if ((get_sdr_cs_size(SDRC_CS1_OSET) != 0) && (get_sdr_cs1_base() != OMAP_SDRC_CS0)) {
> arm_add_mem_device("ram1", get_sdr_cs1_base(), get_sdr_cs_size(SDRC_CS1_OSET));
> + printf("found %s at SDCS1\n", size_human_readable(get_sdr_cs_size(SDRC_CS1_OSET)));
> + }
>
> return 0;
> }
> --
> 1.7.0.4
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: [PATCH 1/6] mc13xxx: Define maximum SPI clock frequency global to driver
From: Sascha Hauer @ 2012-07-20 7:46 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
In-Reply-To: <1342711817-866-1-git-send-email-shc_work@mail.ru>
Hi Alexander,
Applied these except 1/6 and 3/6 which have open comments.
Sascha
On Thu, Jul 19, 2012 at 07:30:12PM +0400, Alexander Shiyan wrote:
> This patch provide setup for SPI clk frequency global to driver.
> For MC13783 maximum clock frequency is 20 MHz,
> for MC13892 maximum clock frequency is 26 MHz,
> so we define 20 MHz as a maximum SPI clk.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
> arch/arm/boards/ccxmx51/ccxmx51.c | 1 -
> arch/arm/boards/freescale-mx51-pdk/board.c | 1 -
> arch/arm/boards/pcm038/pcm038.c | 1 -
> drivers/mfd/mc13xxx.c | 1 +
> 4 files changed, 1 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
> index f494174..f309e0c 100644
> --- a/arch/arm/boards/ccxmx51/ccxmx51.c
> +++ b/arch/arm/boards/ccxmx51/ccxmx51.c
> @@ -191,7 +191,6 @@ static struct spi_imx_master ecspi_0_data = {
> static const struct spi_board_info ccxmx51_spi_board_info[] = {
> {
> .name = "mc13xxx-spi",
> - .max_speed_hz = 6000000,
> .bus_num = 0,
> .chip_select = 0,
> },
> diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
> index 3a568d0..7c2c8fe 100644
> --- a/arch/arm/boards/freescale-mx51-pdk/board.c
> +++ b/arch/arm/boards/freescale-mx51-pdk/board.c
> @@ -117,7 +117,6 @@ static struct spi_imx_master spi_0_data = {
> static const struct spi_board_info mx51_babbage_spi_board_info[] = {
> {
> .name = "mc13xxx-spi",
> - .max_speed_hz = 300000,
> .bus_num = 0,
> .chip_select = 0,
> },
> diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
> index badc978..fa82b02 100644
> --- a/arch/arm/boards/pcm038/pcm038.c
> +++ b/arch/arm/boards/pcm038/pcm038.c
> @@ -59,7 +59,6 @@ static struct spi_imx_master pcm038_spi_0_data = {
> static struct spi_board_info pcm038_spi_board_info[] = {
> {
> .name = "mc13xxx-spi",
> - .max_speed_hz = 3000000,
> .bus_num = 0,
> .chip_select = 0,
> }
> diff --git a/drivers/mfd/mc13xxx.c b/drivers/mfd/mc13xxx.c
> index 2934e9d..8bb0d00 100644
> --- a/drivers/mfd/mc13xxx.c
> +++ b/drivers/mfd/mc13xxx.c
> @@ -297,6 +297,7 @@ static int mc_probe(struct device_d *dev, enum mc13xxx_mode mode)
> mc_dev->spi = dev->type_data;
> mc_dev->spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
> mc_dev->spi->bits_per_word = 32;
> + mc_dev->spi->max_speed_hz = 20000000;
> }
> mc_dev->cdev.size = 256;
> mc_dev->cdev.dev = dev;
> --
> 1.7.3.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: [PATCH/master] ARM/Samsung: A required fix and a cleanup
From: Sascha Hauer @ 2012-07-20 7:53 UTC (permalink / raw)
To: Juergen Beisert; +Cc: barebox
In-Reply-To: <1342767377-24735-1-git-send-email-jbe@pengutronix.de>
On Fri, Jul 20, 2012 at 08:56:14AM +0200, Juergen Beisert wrote:
> Some fixes and cleanups for master related to boards based on the Samsung
> S3C24XX CPU.
>
> The following changes since commit b78e5fe9f3ce155065831d3aa8a480656a8f53c5:
>
> commands/crc: assert newline after output with big offsets (2012-07-17 20:41:17 +0200)
>
> are available in the git repository at:
>
> git://git.pengutronix.de/git/jbe/barebox.git for_master_s3c24xx_runtime_fix_and_cleanup
Pulled, thanks
Sascha
>
> for you to fetch changes up to b47220d7f70df9191fc456dbcaeaa6ead72c6c02:
>
> NAND/Samsung: remove a leftover from architeture clean ups (2012-07-20 08:41:35 +0200)
>
> ----------------------------------------------------------------
> Juergen Beisert (3):
> ARM/Samsung: be able to include the nand header multiple times
> ARM/Samsung: unify device registration for the S3C24XX SoCs
> NAND/Samsung: remove a leftover from architeture clean ups
>
> arch/arm/boards/a9m2410/a9m2410.c | 7 ++-
> arch/arm/boards/a9m2440/a9m2440.c | 7 ++-
> arch/arm/boards/mini2440/mini2440.c | 16 +++---
> .../mach-samsung/include/mach/devices-s3c24xx.h | 55 ++++++++++++++++++++
> arch/arm/mach-samsung/include/mach/s3c24xx-nand.h | 5 ++
> drivers/mtd/nand/Makefile | 1 -
> 6 files changed, 72 insertions(+), 19 deletions(-)
> create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: Compressed barebox image support
From: Sascha Hauer @ 2012-07-20 7:59 UTC (permalink / raw)
To: Robert Jarzmik; +Cc: barebox
In-Reply-To: <87fw8nv7dx.fsf@free.fr>
Hi Robert,
On Thu, Jul 19, 2012 at 10:11:06PM +0200, Robert Jarzmik wrote:
> Sascha Hauer <s.hauer@pengutronix.de> writes:
> > Nevertheless I would be happy about Tested-by (and does-not-work-for) tags.
> >
> > Sascha
>
> I tried on Xscale PXA (mioa701 board, armv5te).
> It works like a charm.
>
> Therefore, feel free to add my :
> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Thanks for testing.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: [PATCH] serial_ns16550: change the driver's name
From: Sascha Hauer @ 2012-07-20 8:02 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
In-Reply-To: <1342763209-28029-1-git-send-email-antonynpavlov@gmail.com>
On Fri, Jul 20, 2012 at 09:46:49AM +0400, Antony Pavlov wrote:
> The name "serial_ns16550" is not handy because the devices
> will have the names like "serial_ns165500", "serial_ns165501",
> "serial_ns165502" etc.
>
> The names like "ns16550_serial0" and "ns16550_serial1" look
> much better.
>
> Also it is reasonable to make serial driver's names unification.
> E.g. see the names for drivers in drivers/serial directory:
> "netx_serial",
> "mpc5xxx_serial",
> "altera_serial",
> "s3c_serial",
> "imx_serial",
> "pxa_serial",
> "blackfin_serial",
> "stm_serial",
> "pl010_serial",
> and even "g_serial" in ./drivers/usb/gadget/serial.c
Good idea. Applied.
Sascha
>
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
> drivers/serial/serial_ns16550.c | 2 +-
> include/driver.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
> index 820aac5..1248bd6 100644
> --- a/drivers/serial/serial_ns16550.c
> +++ b/drivers/serial/serial_ns16550.c
> @@ -263,7 +263,7 @@ static int ns16550_probe(struct device_d *dev)
> * @brief Driver registration structure
> */
> static struct driver_d ns16550_serial_driver = {
> - .name = "serial_ns16550",
> + .name = "ns16550_serial",
> .probe = ns16550_probe,
> };
>
> diff --git a/include/driver.h b/include/driver.h
> index 7d597b4..0a8dc8e 100644
> --- a/include/driver.h
> +++ b/include/driver.h
> @@ -226,7 +226,7 @@ struct NS16550_plat;
> static inline struct device_d *add_ns16550_device(int id, resource_size_t start,
> resource_size_t size, int flags, struct NS16550_plat *pdata)
> {
> - return add_generic_device("serial_ns16550", id, NULL, start, size,
> + return add_generic_device("ns16550_serial", id, NULL, start, size,
> IORESOURCE_MEM | flags, pdata);
> }
>
> --
> 1.7.10
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: USB On PCM043?
From: Sascha Hauer @ 2012-07-20 8:04 UTC (permalink / raw)
To: Jerry Kirk; +Cc: barebox
In-Reply-To: <loom.20120719T224910-551@post.gmane.org>
On Thu, Jul 19, 2012 at 08:56:35PM +0000, Jerry Kirk wrote:
> > > We have been attempting to get USB Host mode working under Barebox(2012-07-0)
> > > a PCM043 platform (i.mx35), but we are having a bit of trouble.
> >
> > Could it be that the USB clock operates at the wrong rate? I think it
> > should be 60MHz.
>
> We're not certain how to verify the clock setting for USB in Barebox.
> We have used "dump_clocks" but are not certain which of these clocks
> the USB clock is derived from. We think we have it set to the same
> settings as the Eukrea board.
The i.MX SoCs have a clko pin which can be muxed to different clocks. I
don't know if this is accessible on the pcm043, but if yes, you could
switch it to the USB clock and measure the clock.
Otherwise it might be good to run a current -rc kernel, you can then
see the complete clock tree in debugfs
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re[2]: [PATCH 1/6] mc13xxx: Define maximum SPI clock frequency global to driver
From: Alexander Shiyan @ 2012-07-20 8:05 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20120719175512.GD30009@pengutronix.de>
Hello.
Thu, 19 Jul 2012 19:55:12 +0200 от Sascha Hauer <s.hauer@pengutronix.de>:
> On Thu, Jul 19, 2012 at 07:30:12PM +0400, Alexander Shiyan wrote:
> > This patch provide setup for SPI clk frequency global to driver.
> > For MC13783 maximum clock frequency is 20 MHz,
> > for MC13892 maximum clock frequency is 26 MHz,
> > so we define 20 MHz as a maximum SPI clk.
> >
> > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> > ---
> > arch/arm/boards/ccxmx51/ccxmx51.c | 1 -
> > arch/arm/boards/freescale-mx51-pdk/board.c | 1 -
> > arch/arm/boards/pcm038/pcm038.c | 1 -
> > drivers/mfd/mc13xxx.c | 1 +
> > 4 files changed, 1 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
> > index f494174..f309e0c 100644
> > --- a/arch/arm/boards/ccxmx51/ccxmx51.c
> > +++ b/arch/arm/boards/ccxmx51/ccxmx51.c
> > @@ -191,7 +191,6 @@ static struct spi_imx_master ecspi_0_data = {
> > static const struct spi_board_info ccxmx51_spi_board_info[] = {
> > {
> > .name = "mc13xxx-spi",
> > - .max_speed_hz = 6000000,
> > .bus_num = 0,
> > .chip_select = 0,
> > },
> > diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
> > index 3a568d0..7c2c8fe 100644
> > --- a/arch/arm/boards/freescale-mx51-pdk/board.c
> > +++ b/arch/arm/boards/freescale-mx51-pdk/board.c
> > @@ -117,7 +117,6 @@ static struct spi_imx_master spi_0_data = {
> > static const struct spi_board_info mx51_babbage_spi_board_info[] = {
> > {
> > .name = "mc13xxx-spi",
> > - .max_speed_hz = 300000,
> > .bus_num = 0,
> > .chip_select = 0,
> > },
> > diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
> > index badc978..fa82b02 100644
> > --- a/arch/arm/boards/pcm038/pcm038.c
> > +++ b/arch/arm/boards/pcm038/pcm038.c
> > @@ -59,7 +59,6 @@ static struct spi_imx_master pcm038_spi_0_data = {
> > static struct spi_board_info pcm038_spi_board_info[] = {
> > {
> > .name = "mc13xxx-spi",
> > - .max_speed_hz = 3000000,
> > .bus_num = 0,
> > .chip_select = 0,
> > }
> > diff --git a/drivers/mfd/mc13xxx.c b/drivers/mfd/mc13xxx.c
> > index 2934e9d..8bb0d00 100644
> > --- a/drivers/mfd/mc13xxx.c
> > +++ b/drivers/mfd/mc13xxx.c
> > @@ -297,6 +297,7 @@ static int mc_probe(struct device_d *dev, enum mc13xxx_mode mode)
> > mc_dev->spi = dev->type_data;
> > mc_dev->spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
> > mc_dev->spi->bits_per_word = 32;
> > + mc_dev->spi->max_speed_hz = 20000000;
>
> The values indeed look quite arbitrary, but it may be that a hardware
> design does not support such high frequencies. Maybe better
>
> if (!mc_dev->spi->max_speed_hz)
> mc_dev->spi->max_speed_hz = 20000000
>
> ?
On my opinion, tests for supported speed, is work for SPI-driver, not for device driver.
Is not it?
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re[2]: [PATCH 3/6] mc13xxx: Added dummy definition for mc13xxx_get() if CONFIG_MFD_MC13XXX is not set
From: Alexander Shiyan @ 2012-07-20 8:08 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20120719175606.GE30009@pengutronix.de>
Hello.
Thu, 19 Jul 2012 19:56:06 +0200 от Sascha Hauer <s.hauer@pengutronix.de>:
> On Thu, Jul 19, 2012 at 07:30:14PM +0400, Alexander Shiyan wrote:
> >
> > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> > ---
> > arch/arm/boards/pcm038/pcm038.c | 2 --
> > include/mfd/mc13xxx.h | 4 ++++
> > 2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
> > index fa82b02..875081b 100644
> > --- a/arch/arm/boards/pcm038/pcm038.c
> > +++ b/arch/arm/boards/pcm038/pcm038.c
> > @@ -124,7 +124,6 @@ static inline uint32_t get_pll_spctl10(void)
> > */
> > static int pcm038_power_init(void)
> > {
> > -#ifdef CONFIG_MFD_MC13XXX
> > uint32_t spctl0 = get_pll_spctl10();
> > struct mc13xxx *mc13xxx = mc13xxx_get();
> >
> > @@ -158,7 +157,6 @@ static int pcm038_power_init(void)
> > printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
> > }
> > }
> > -#endif
> >
> > /* clock gating enable */
> > GPCR = 0x00050f08;
> > diff --git a/include/mfd/mc13xxx.h b/include/mfd/mc13xxx.h
> > index 2880307..51cfdd9 100644
> > --- a/include/mfd/mc13xxx.h
> > +++ b/include/mfd/mc13xxx.h
> > @@ -163,7 +163,11 @@ struct mc13xxx {
> > int revision;
> > };
> >
> > +#ifdef CONFIG_MFD_MC13XXX
> > extern struct mc13xxx *mc13xxx_get(void);
> > +#else
> > +#define mc13xxx_get() (NULL)
>
> Better a static inline function.
OK, modified version of patch will be sent in new thread.
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: [PATCH 1/6] mc13xxx: Define maximum SPI clock frequency global to driver
From: Sascha Hauer @ 2012-07-20 8:11 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
In-Reply-To: <1342771521.408579760@f31.mail.ru>
On Fri, Jul 20, 2012 at 12:05:21PM +0400, Alexander Shiyan wrote:
> >
> > The values indeed look quite arbitrary, but it may be that a hardware
> > design does not support such high frequencies. Maybe better
> >
> > if (!mc_dev->spi->max_speed_hz)
> > mc_dev->spi->max_speed_hz = 20000000
> >
> > ?
> On my opinion, tests for supported speed, is work for SPI-driver, not for device driver.
> Is not it?
So you mean that the i.MX spi drivers platform data should have a
maximum speed field instead of the client drivers? Sounds good.
In this case we can apply the patch.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re[2]: [PATCH 1/6] mc13xxx: Define maximum SPI clock frequency global to driver
From: Alexander Shiyan @ 2012-07-20 8:17 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20120720081136.GQ30009@pengutronix.de>
Hello.
Fri, 20 Jul 2012 10:11:36 +0200 от Sascha Hauer <s.hauer@pengutronix.de>:
> On Fri, Jul 20, 2012 at 12:05:21PM +0400, Alexander Shiyan wrote:
> > >
> > > The values indeed look quite arbitrary, but it may be that a hardware
> > > design does not support such high frequencies. Maybe better
> > >
> > > if (!mc_dev->spi->max_speed_hz)
> > > mc_dev->spi->max_speed_hz = 20000000
> > >
> > > ?
> > On my opinion, tests for supported speed, is work for SPI-driver, not for device driver.
> > Is not it?
>
> So you mean that the i.MX spi drivers platform data should have a
> maximum speed field instead of the client drivers? Sounds good.
> In this case we can apply the patch.
No additional fields required. We are pass max_speed_hz option in the SPI-driver
to clock divider, so frequency cannot be higher than possible. Fixme.
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* Re: [PATCH] ARM: add the vendor 'FriendlyARM' to its board's directory names
From: Sascha Hauer @ 2012-07-20 8:40 UTC (permalink / raw)
To: Juergen Beisert; +Cc: barebox
In-Reply-To: <1342728533-3750-1-git-send-email-jbe@pengutronix.de>
On Thu, Jul 19, 2012 at 10:08:52PM +0200, Juergen Beisert wrote:
> Since a look into "arch/arm/boards/" offers various boards starting with the
> vendor's name in their directory name (like 'eukrea' and 'freescale').
> This patch does the same with the currently existing FriendlyARM boards
> Mini2440 and Tiny210.
>
> Note: I hope I have used the '-M' parameter in a correct manner ;)
Yes, you did ;)
There is another problem though: Please do not send pull requests based
on next. next is not stable and gets remerged from the topic branches.
In this case the tiny210 is sitting in next, so you can send a rename
patch for this board. I'll squash it into the original patch adding this
board. The rename for the mini2440 should be a separate patch based on
master.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* [RFC 1/7] MIPS: move start.S code to .text_entry section
From: Antony Pavlov @ 2012-07-20 8:47 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342774059-2169-1-git-send-email-antonynpavlov@gmail.com>
This commit make possible lowlevel initialisation code
in the text_bare_init section.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boot/start.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
index dd302fc..10f7691 100644
--- a/arch/mips/boot/start.S
+++ b/arch/mips/boot/start.S
@@ -50,7 +50,7 @@ _pc: addiu \rd, ra, \label - _pc # label is assumed to be
.set noreorder
.text
- .section ".text_bare_init"
+ .section ".text_entry"
.align 4
EXPORT(_start)
--
1.7.10
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [WIP] add very basic ELF support on MIPS
From: Antony Pavlov @ 2012-07-20 8:47 UTC (permalink / raw)
To: barebox
This patch series introduces the basic ELF files support
for bootm command on MIPS based on kexec.
The goal of this work is ELF linux kernel loading for MIPS.
The patches 1-3 used to introduce per-arch low-level init for MIPS.
The patch 4 adds the nessesary low-level initialisation for
qemu-malta suitable for Linux kernel.
Just now barebox for MIPS32 has no support for cache, so
this patch series tries to overcome this disadvantage in
patch 5.
The patch 6 introduce memory region for loading ELFs on qemu-malta.
At last the patch 7 introduces kexec infrastructure for ELF loading.
Current problems:
* there is no Linux kernel cmdline support;
* the code is not clean (e.g. there are some '#if 0' and
some unused declarations);
* barebox already has ELF support for modules, but
this patch series just has no integration with it.
This patch series and one additional huge patch with sample
Linux ELF image for malta can be found at
https://github.com/frantony/barebox/tree/next.mips-malta-elf-linux.20120720
[RFC 1/7] MIPS: move start.S code to .text_entry section
[RFC 2/7] MIPS: add the initial support for lowlevel init
[RFC 3/7] MIPS: malta: add bogus lowlevel init
[RFC 4/7] MIPS: malta: add YAMON-style GT64120 memory map
[RFC 5/7] MIPS: malta: make KSEG0 uncached
[RFC 6/7] MIPS: qemu-malta: add KSEG0 memory region
[RFC 7/7] bootm: add very basic ELF support on MIPS (stealed from
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply
* [RFC 2/7] MIPS: add the initial support for lowlevel init
From: Antony Pavlov @ 2012-07-20 8:47 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342774059-2169-1-git-send-email-antonynpavlov@gmail.com>
This commit introduce the initial support for
machine specific lowlevel initialization
(e.g. RAM controller or cache memory).
To return from mach_init_lowlevel() it uses
explicit mach_init_lowlevel_return label.
This saves ra register for using inside mach_init_lowlevel()
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boot/start.S | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
index 10f7691..238e2c4 100644
--- a/arch/mips/boot/start.S
+++ b/arch/mips/boot/start.S
@@ -74,6 +74,14 @@ __start:
and k0, k1
mtc0 k0, CP0_STATUS
+#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT
+ b mach_init_lowlevel
+ nop
+
+mach_init_lowlevel_return:
+EXPORT(mach_init_lowlevel_return)
+#endif
+
/* copy barebox to link location */
ADR a0, _start, t1 /* a0 <- pc-relative position of _start */
--
1.7.10
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [RFC 3/7] MIPS: malta: add bogus lowlevel init
From: Antony Pavlov @ 2012-07-20 8:47 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342774059-2169-1-git-send-email-antonynpavlov@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/Kconfig | 1 +
arch/mips/mach-malta/Makefile | 1 +
arch/mips/mach-malta/lowlevel_init.S | 37 ++++++++++++++++++++++++++++++++++
3 files changed, 39 insertions(+)
create mode 100644 arch/mips/mach-malta/lowlevel_init.S
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7a1eeac..92dad9f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -36,6 +36,7 @@ config MACH_MIPS_MALTA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select HAS_DEBUG_LL
+ select MACH_HAS_LOWLEVEL_INIT
config MACH_MIPS_BCM47XX
bool "Broadcom BCM47xx-based boards"
diff --git a/arch/mips/mach-malta/Makefile b/arch/mips/mach-malta/Makefile
index f3cc668..f4cb8f2 100644
--- a/arch/mips/mach-malta/Makefile
+++ b/arch/mips/mach-malta/Makefile
@@ -1 +1,2 @@
obj-y += reset.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
diff --git a/arch/mips/mach-malta/lowlevel_init.S b/arch/mips/mach-malta/lowlevel_init.S
new file mode 100644
index 0000000..a34de74
--- /dev/null
+++ b/arch/mips/mach-malta/lowlevel_init.S
@@ -0,0 +1,37 @@
+/*
+ * Lowlevel init code for MIPS malta
+ *
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+ .section ".text_bare_init"
+
+LEAF(mach_init_lowlevel)
+
+ /* nothing special yet */
+
+ /* return */
+ b mach_init_lowlevel_return
+ nop
+END(mach_init_lowlevel)
--
1.7.10
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [RFC 4/7] MIPS: malta: add YAMON-style GT64120 memory map
From: Antony Pavlov @ 2012-07-20 8:47 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342774059-2169-1-git-send-email-antonynpavlov@gmail.com>
YAMON-style GT64120 memory map make move UART to the new position.
We need YAMON-style GT64120 memory for running Linux kernel from
barebox.
WARNING! WIP! We need add some more effor for compartability
with qemu embedded YAMON.
E.g. we need put special Board ID at the start of bootrom:
--- a/arch/mips/boot/start.S
+++ b/arch/mips/boot/start.S
@@ -59,6 +59,10 @@ EXPORT(_start)
nop
.org 0x10
+#if 1
+ /* Board ID = 0x420 (Malta Board with CoreLV) */
+ .word 0x00000420
+#endif
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/mach-malta/include/mach/hardware.h | 2 +-
arch/mips/mach-malta/lowlevel_init.S | 33 +++++++++++++++++++++++++-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mach-malta/include/mach/hardware.h b/arch/mips/mach-malta/include/mach/hardware.h
index ddeb1b7..fde8f22 100644
--- a/arch/mips/mach-malta/include/mach/hardware.h
+++ b/arch/mips/mach-malta/include/mach/hardware.h
@@ -21,7 +21,7 @@
#ifndef __INCLUDE_ARCH_HARDWARE_H__
#define __INCLUDE_ARCH_HARDWARE_H__
-#define DEBUG_LL_UART_ADDR 0xb00003f8
+#define DEBUG_LL_UART_ADDR 0xb80003f8
#define DEBUG_LL_UART_SHIFT 0
/*
diff --git a/arch/mips/mach-malta/lowlevel_init.S b/arch/mips/mach-malta/lowlevel_init.S
index a34de74..a0134f8 100644
--- a/arch/mips/mach-malta/lowlevel_init.S
+++ b/arch/mips/mach-malta/lowlevel_init.S
@@ -29,7 +29,38 @@
LEAF(mach_init_lowlevel)
- /* nothing special yet */
+ /*
+ * Load BAR registers of GT64120 as done by YAMON
+ *
+ * based on write_bootloader() in qemu.git/hw/mips_malta.c
+ * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
+ *
+ * This is big-endian version of code!
+ */
+
+ /* move GT64120 registers to 0x1be00000 */
+ lui t1, 0xb400
+ lui t0, 0xdf00
+ sw t0, 104(t1)
+
+ /* setup MEM-to-PCI0 mapping */
+ lui t1, 0xbbe0
+
+ /* setup PCI0 io window to 18000000-181fffff */
+ lui t0, 0xc000
+ sw t0, 72(t1) /* GT_PCI0IOLD */
+ lui t0, 0x4000
+ sw t0, 80(t1) /* GT_PCI0IOHD */
+
+ /* setup PCI0 mem windows */
+ lui t0, 0x8000
+ sw t0, 88(t1) /* GT_PCI0M0LD */
+ lui t0, 0x3f00
+ sw t0, 96(t1) /* GT_PCI0M0HD */
+ lui t0, 0xc100
+ sw t0, 128(t1) /* GT_PCI0M1LD */
+ lui t0, 0x5e00
+ sw t0, 136(t1) /* GT_PCI0M1HD */
/* return */
b mach_init_lowlevel_return
--
1.7.10
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [RFC 5/7] MIPS: malta: make KSEG0 uncached
From: Antony Pavlov @ 2012-07-20 8:47 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342774059-2169-1-git-send-email-antonynpavlov@gmail.com>
On MIPS as usual KSEG0 segment used for cached memory access,
and Linux kernel linked to KSEG0.
As just now we don't have cache memory support on MIPS,
we can change the KSEG0 mode (make it uncached) and
use it without any danger.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/mach-malta/lowlevel_init.S | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/mips/mach-malta/lowlevel_init.S b/arch/mips/mach-malta/lowlevel_init.S
index a0134f8..368c2fe 100644
--- a/arch/mips/mach-malta/lowlevel_init.S
+++ b/arch/mips/mach-malta/lowlevel_init.S
@@ -62,6 +62,10 @@ LEAF(mach_init_lowlevel)
lui t0, 0x5e00
sw t0, 136(t1) /* GT_PCI0M1HD */
+ /* make KSEG0 uncached */
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+
/* return */
b mach_init_lowlevel_return
nop
--
1.7.10
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [RFC 6/7] MIPS: qemu-malta: add KSEG0 memory region
From: Antony Pavlov @ 2012-07-20 8:47 UTC (permalink / raw)
To: barebox
In-Reply-To: <1342774059-2169-1-git-send-email-antonynpavlov@gmail.com>
As most of ELF files are linked to KSEG0,
we need declaration for memory region (KSEG0)
for loading ELF files.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boards/qemu-malta/init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/boards/qemu-malta/init.c b/arch/mips/boards/qemu-malta/init.c
index 0efc92a..1dd268f 100644
--- a/arch/mips/boards/qemu-malta/init.c
+++ b/arch/mips/boards/qemu-malta/init.c
@@ -34,6 +34,7 @@
static int malta_mem_init(void)
{
barebox_add_memory_bank("ram0", 0xa0000000, SZ_256M);
+ barebox_add_memory_bank("cram0", 0x80000000, SZ_256M);
return 0;
}
--
1.7.10
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox