Re: [PATCH v2 04/10] arm: socfpga: iossm: store size in bytes

[Michael Tretter <m.tretter@pengutronix.de>]

On Fri, 10 Apr 2026 10:13:41 +0200, Ahmad Fatoum wrote:
> On 4/9/26 3:52 PM, Michael Tretter wrote:
> > The mem_width_info is the memory size in gigabits. Convert it to bytes
> > before storing it for each bank to have a more convenient format and
> > simplify the conversion when reading the value.
> > 
> > Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> > ---
> > Changes in v2:
> > 
> > - Change memory_size in io96b_mb_ctrl to phys_size_t to prevent overflow
> 
> Thanks for addressing the concern. I looked it over and there's still a
> chance for overflow.
> 
> > diff --git a/arch/arm/mach-socfpga/iossm_mailbox.c b/arch/arm/mach-socfpga/iossm_mailbox.c
> > index 9299fee71e0b..042ea4a99e5c 100644
> > --- a/arch/arm/mach-socfpga/iossm_mailbox.c
> > +++ b/arch/arm/mach-socfpga/iossm_mailbox.c
> > @@ -9,6 +9,7 @@
> >  #include <common.h>
> >  #include <io.h>
> >  #include <linux/bitfield.h>
> > +#include <linux/sizes.h>
> >  #include "iossm_mailbox.h"
> >  #include <mach/socfpga/generic.h>
> >  #include <mach/socfpga/soc64-regs.h>
> > @@ -404,21 +405,25 @@ int io96b_get_mem_width_info(struct io96b_info *io96b_ctrl)
> >  	struct io96b_mb_resp usr_resp;
> >  	struct io96b_mb_ctrl *mb_ctrl;
> >  	int i, j;
> > -	u16 memory_size;
> > -	u16 total_memory_size = 0;
> > +	phys_size_t memory_size;
> > +	u32 mem_width_info;
> > +	phys_size_t total_memory_size = 0;
> >  
> >  	/* Get all memory interface(s) total memory size on all instance(s) */
> >  	for (i = 0; i < io96b_ctrl->num_instance; i++) {
> >  		mb_ctrl = &io96b_ctrl->io96b[i].mb_ctrl;
> >  		memory_size = 0;
> > +
> >  		for (j = 0; j < mb_ctrl->num_mem_interface; j++) {
> >  			io96b_mb_req_no_param(io96b_ctrl->io96b[i].io96b_csr_addr,
> >  					      mb_ctrl->ip_type[j],
> >  					      mb_ctrl->ip_instance_id[j],
> >  					      CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, &usr_resp);
> > +			mem_width_info = usr_resp.cmd_resp_data[1] & GENMASK(7, 0);
> 
> I assume this is the RAM memory width in bytes, e.g. 2 or 4 bytes, but
> the mask  allows it to be up to 255.

mem_width_info is in Giga bits.

> 
> >  
> > -			memory_size = memory_size +
> > -				(usr_resp.cmd_resp_data[1] & GENMASK(7, 0));
> > +			mb_ctrl->memory_size[j] = mem_width_info * (SZ_1G / SZ_8);
> 
> SZ_4G / (SZ_1G / 8) = 32
> 
> So the maximum value permitted in mem_width_info without overflowing is
> 31, but the code accepts up to 255. As all types on the left hand side
> are 32-bit only.

This driver is only available on Agilex5, which is arm64 and selects
PHYS_ADDR_T_64BIT. Thus, phys_size_t has 64 bits and doesn't result in
an overflow.

Michael

> 
> Worth a check or adaptation of the mask?
> 
> Cheers,
> Ahmad
> 
> > +
> > +			memory_size += mb_ctrl->memory_size[j];
> >  		}
> >  
> >  		if (!memory_size) {
> > diff --git a/arch/arm/mach-socfpga/iossm_mailbox.h b/arch/arm/mach-socfpga/iossm_mailbox.h
> > index bd66621d5f70..0c15c92bb867 100644
> > --- a/arch/arm/mach-socfpga/iossm_mailbox.h
> > +++ b/arch/arm/mach-socfpga/iossm_mailbox.h
> > @@ -79,6 +79,7 @@ struct io96b_mb_ctrl {
> >  	u32 num_mem_interface;
> >  	u32 ip_type[2];
> >  	u32 ip_instance_id[2];
> > +	phys_size_t memory_size[2];
> >  };
> >  
> >  /*
> > @@ -101,7 +102,7 @@ struct io96b_mb_resp {
> >   * @mb_ctrl:		IOSSM mailbox required information
> >   */
> >  struct io96b_instance {
> > -	u16 size;
> > +	phys_size_t size;
> >  	phys_addr_t io96b_csr_addr;
> >  	bool cal_status;
> >  	struct io96b_mb_ctrl mb_ctrl;
> > @@ -126,7 +127,7 @@ struct io96b_info {
> >  	bool			 overall_cal_status;
> >  	const char		*ddr_type;
> >  	bool			 ecc_status;
> > -	u16			 overall_size;
> > +	phys_size_t		 overall_size;
> >  	struct io96b_instance	 io96b[MAX_IO96B_SUPPORTED];
> >  	bool			 ckgen_lock;
> >  	u8			 num_port;
> >