* [PATCH v2 2/8] clocksource: Add rk3288 timer driver
From: Wadim Egorov @ 2016-08-24 12:49 UTC (permalink / raw)
To: barebox
In-Reply-To: <1472042970-35151-1-git-send-email-w.egorov@phytec.de>
This driver comes from the u-boot (v2016.01).
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
Changes since v1:
- moved rk_timer to drivers/clocksource
- rk_timer now binds against a DT node
---
arch/arm/mach-rockchip/Kconfig | 5 ++
arch/arm/mach-rockchip/include/mach/timer.h | 19 ++++++++
drivers/clocksource/Kconfig | 4 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/rk_timer.c | 73 +++++++++++++++++++++++++++++
5 files changed, 102 insertions(+)
create mode 100644 arch/arm/mach-rockchip/include/mach/timer.h
create mode 100644 drivers/clocksource/rk_timer.c
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e027fae..71fcbe7 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -7,6 +7,10 @@ config ARCH_TEXT_BASE
default 0x68000000 if ARCH_RK3188
default 0x0 if ARCH_RK3288
+config RK_TIMER
+ hex
+ default 1
+
choice
prompt "Select Rockchip SoC"
@@ -15,6 +19,7 @@ config ARCH_RK3188
config ARCH_RK3288
bool "Rockchip RK3288 SoCs"
+ select CLOCKSOURCE_ROCKCHIP
endchoice
comment "select Rockchip boards:"
diff --git a/arch/arm/mach-rockchip/include/mach/timer.h b/arch/arm/mach-rockchip/include/mach/timer.h
new file mode 100644
index 0000000..e6ed0e4
--- /dev/null
+++ b/arch/arm/mach-rockchip/include/mach/timer.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_TIMER_H
+#define _ASM_ARCH_TIMER_H
+
+struct rk_timer {
+ unsigned int timer_load_count0;
+ unsigned int timer_load_count1;
+ unsigned int timer_curr_value0;
+ unsigned int timer_curr_value1;
+ unsigned int timer_ctrl_reg;
+ unsigned int timer_int_status;
+};
+
+#endif
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3fb09fb..f1ab554 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -49,3 +49,7 @@ config CLOCKSOURCE_ORION
config CLOCKSOURCE_UEMD
bool
depends on ARCH_UEMD
+
+config CLOCKSOURCE_ROCKCHIP
+ bool
+ depends on ARCH_ROCKCHIP
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 4eb1656..39982ff 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_CLOCKSOURCE_MVEBU) += mvebu.o
obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o
obj-$(CONFIG_CLOCKSOURCE_ORION) += orion.o
obj-$(CONFIG_CLOCKSOURCE_UEMD) += uemd.o
+obj-$(CONFIG_CLOCKSOURCE_ROCKCHIP)+= rk_timer.o
diff --git a/drivers/clocksource/rk_timer.c b/drivers/clocksource/rk_timer.c
new file mode 100644
index 0000000..baa517c
--- /dev/null
+++ b/drivers/clocksource/rk_timer.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * (C) Copyright 2016 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <clock.h>
+#include <init.h>
+#include <io.h>
+#include <mach/timer.h>
+#include <stdio.h>
+#include <mach/hardware.h>
+#include <mach/cru_rk3288.h>
+#include <common.h>
+
+struct rk_timer *timer_ptr;
+
+static uint64_t rockchip_get_ticks(void)
+{
+ uint64_t timebase_h, timebase_l;
+
+ timebase_l = readl(&timer_ptr->timer_curr_value0);
+ timebase_h = readl(&timer_ptr->timer_curr_value1);
+
+ return timebase_h << 32 | timebase_l;
+}
+
+static struct clocksource rkcs = {
+ .read = rockchip_get_ticks,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 10,
+};
+
+static int rockchip_timer_probe(struct device_d *dev)
+{
+ struct resource *iores;
+
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
+ timer_ptr = IOMEM(iores->start) + 0x20 * CONFIG_RK_TIMER;
+
+ rkcs.mult = clocksource_hz2mult(OSC_HZ, rkcs.shift);
+
+ writel(0xffffffff, &timer_ptr->timer_load_count0);
+ writel(0xffffffff, &timer_ptr->timer_load_count1);
+ writel(1, &timer_ptr->timer_ctrl_reg);
+
+ return init_clock(&rkcs);
+}
+
+static __maybe_unused struct of_device_id rktimer_dt_ids[] = {
+ {
+ .compatible = "rockchip,rk3288-timer",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d rktimer_driver = {
+ .name = "rockchip-timer",
+ .probe = rockchip_timer_probe,
+ .of_compatible = DRV_OF_COMPAT(rktimer_dt_ids),
+};
+
+static int rktimer_init(void)
+{
+ return platform_driver_register(&rktimer_driver);
+}
+core_initcall(rktimer_init);
--
1.9.1
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^ permalink raw reply related
* [PATCH v2 1/8] ARM: rockchip: Add basic RK3288 support
From: Wadim Egorov @ 2016-08-24 12:49 UTC (permalink / raw)
To: barebox
The RK3288 SoC is a low power, high performance processor for mobile phones,
personal mobile internet devices and other digital multimedia applications.
It has an integrated quad-core cortex-A17 with separate NEON coprocessor.
Prepare mach-rockchip infrastructure for Rockchip RK3288 support.
Let's seperate the RK3188 and RK3288 SoCs. Later we will have two different
configs.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/boards/radxa-rock/board.c | 2 +-
.../{rockchip_defconfig => rk3188_defconfig} | 1 +
arch/arm/mach-rockchip/Kconfig | 20 +-
arch/arm/mach-rockchip/Makefile | 3 +-
arch/arm/mach-rockchip/include/mach/cru_rk3288.h | 184 +++++
arch/arm/mach-rockchip/include/mach/grf_rk3288.h | 768 +++++++++++++++++++++
arch/arm/mach-rockchip/include/mach/hardware.h | 18 +
.../mach/{rockchip-regs.h => rk3188-regs.h} | 12 +-
arch/arm/mach-rockchip/include/mach/rk3288-regs.h | 28 +
arch/arm/mach-rockchip/{core.c => rk3188.c} | 2 +-
arch/arm/mach-rockchip/rk3288.c | 92 +++
11 files changed, 1121 insertions(+), 9 deletions(-)
rename arch/arm/configs/{rockchip_defconfig => rk3188_defconfig} (99%)
create mode 100644 arch/arm/mach-rockchip/include/mach/cru_rk3288.h
create mode 100644 arch/arm/mach-rockchip/include/mach/grf_rk3288.h
create mode 100644 arch/arm/mach-rockchip/include/mach/hardware.h
rename arch/arm/mach-rockchip/include/mach/{rockchip-regs.h => rk3188-regs.h} (72%)
create mode 100644 arch/arm/mach-rockchip/include/mach/rk3288-regs.h
rename arch/arm/mach-rockchip/{core.c => rk3188.c} (96%)
create mode 100644 arch/arm/mach-rockchip/rk3288.c
diff --git a/arch/arm/boards/radxa-rock/board.c b/arch/arm/boards/radxa-rock/board.c
index ec053f9..d45e8a9 100644
--- a/arch/arm/boards/radxa-rock/board.c
+++ b/arch/arm/boards/radxa-rock/board.c
@@ -16,7 +16,7 @@
#include <io.h>
#include <i2c/i2c.h>
#include <i2c/i2c-gpio.h>
-#include <mach/rockchip-regs.h>
+#include <mach/rk3188-regs.h>
#include <mfd/act8846.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/configs/rockchip_defconfig b/arch/arm/configs/rk3188_defconfig
similarity index 99%
rename from arch/arm/configs/rockchip_defconfig
rename to arch/arm/configs/rk3188_defconfig
index c9bf874..1b6d4ff 100644
--- a/arch/arm/configs/rockchip_defconfig
+++ b/arch/arm/configs/rk3188_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_RK3188=y
CONFIG_CACHE_L2X0=y
CONFIG_MACH_RADXA_ROCK=y
CONFIG_THUMB2_BAREBOX=y
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ea4361d..e027fae 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -1,14 +1,28 @@
-if ARCH_ROCKCHIP
+
+menu "Rockchip Features"
+ depends on ARCH_ROCKCHIP
config ARCH_TEXT_BASE
hex
- default 0x68000000
+ default 0x68000000 if ARCH_RK3188
+ default 0x0 if ARCH_RK3288
+
+choice
+ prompt "Select Rockchip SoC"
+
+config ARCH_RK3188
+ bool "Rockchip RK3188 SoCs"
+
+config ARCH_RK3288
+ bool "Rockchip RK3288 SoCs"
+endchoice
comment "select Rockchip boards:"
config MACH_RADXA_ROCK
+ depends on ARCH_RK3188
select I2C
select MFD_ACT8846
bool "Radxa rock board"
-endif
+endmenu
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 820eb10..4ca7f17 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1 +1,2 @@
-obj-y += core.o
+obj-$(CONFIG_ARCH_RK3188) += rk3188.o
+obj-$(CONFIG_ARCH_RK3288) += rk3288.o
diff --git a/arch/arm/mach-rockchip/include/mach/cru_rk3288.h b/arch/arm/mach-rockchip/include/mach/cru_rk3288.h
new file mode 100644
index 0000000..c898514
--- /dev/null
+++ b/arch/arm/mach-rockchip/include/mach/cru_rk3288.h
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ * Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3288_H
+#define _ASM_ARCH_CRU_RK3288_H
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ (1800 * 1000000)
+#define GPLL_HZ (594 * 1000000)
+#define CPLL_HZ (384 * 1000000)
+#define NPLL_HZ (384 * 1000000)
+
+/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
+#define PD_BUS_ACLK_HZ 297000000
+#define PD_BUS_HCLK_HZ 148500000
+#define PD_BUS_PCLK_HZ 74250000
+
+#define PERI_ACLK_HZ 148500000
+#define PERI_HCLK_HZ 148500000
+#define PERI_PCLK_HZ 74250000
+
+struct rk3288_cru {
+ struct rk3288_pll {
+ u32 con0;
+ u32 con1;
+ u32 con2;
+ u32 con3;
+ } pll[5];
+ u32 cru_mode_con;
+ u32 reserved0[3];
+ u32 cru_clksel_con[43];
+ u32 reserved1[21];
+ u32 cru_clkgate_con[19];
+ u32 reserved2;
+ u32 cru_glb_srst_fst_value;
+ u32 cru_glb_srst_snd_value;
+ u32 cru_softrst_con[12];
+ u32 cru_misc_con;
+ u32 cru_glb_cnt_th;
+ u32 cru_glb_rst_con;
+ u32 reserved3;
+ u32 cru_glb_rst_st;
+ u32 reserved4;
+ u32 cru_sdmmc_con[2];
+ u32 cru_sdio0_con[2];
+ u32 cru_sdio1_con[2];
+ u32 cru_emmc_con[2];
+};
+
+/* CRU_CLKSEL11_CON */
+enum {
+ HSICPHY_DIV_SHIFT = 8,
+ HSICPHY_DIV_MASK = 0x3f,
+
+ MMC0_PLL_SHIFT = 6,
+ MMC0_PLL_MASK = 3,
+ MMC0_PLL_SELECT_CODEC = 0,
+ MMC0_PLL_SELECT_GENERAL,
+ MMC0_PLL_SELECT_24MHZ,
+
+ MMC0_DIV_SHIFT = 0,
+ MMC0_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+ EMMC_PLL_SHIFT = 0xe,
+ EMMC_PLL_MASK = 3,
+ EMMC_PLL_SELECT_CODEC = 0,
+ EMMC_PLL_SELECT_GENERAL,
+ EMMC_PLL_SELECT_24MHZ,
+
+ EMMC_DIV_SHIFT = 8,
+ EMMC_DIV_MASK = 0x3f,
+
+ SDIO0_PLL_SHIFT = 6,
+ SDIO0_PLL_MASK = 3,
+ SDIO0_PLL_SELECT_CODEC = 0,
+ SDIO0_PLL_SELECT_GENERAL,
+ SDIO0_PLL_SELECT_24MHZ,
+
+ SDIO0_DIV_SHIFT = 0,
+ SDIO0_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+ SPI1_PLL_SHIFT = 0xf,
+ SPI1_PLL_MASK = 1,
+ SPI1_PLL_SELECT_CODEC = 0,
+ SPI1_PLL_SELECT_GENERAL,
+
+ SPI1_DIV_SHIFT = 8,
+ SPI1_DIV_MASK = 0x7f,
+
+ SPI0_PLL_SHIFT = 7,
+ SPI0_PLL_MASK = 1,
+ SPI0_PLL_SELECT_CODEC = 0,
+ SPI0_PLL_SELECT_GENERAL,
+
+ SPI0_DIV_SHIFT = 0,
+ SPI0_DIV_MASK = 0x7f,
+};
+
+/* CRU_CLKSEL39_CON */
+enum {
+ ACLK_HEVC_PLL_SHIFT = 0xe,
+ ACLK_HEVC_PLL_MASK = 3,
+ ACLK_HEVC_PLL_SELECT_CODEC = 0,
+ ACLK_HEVC_PLL_SELECT_GENERAL,
+ ACLK_HEVC_PLL_SELECT_NEW,
+
+ ACLK_HEVC_DIV_SHIFT = 8,
+ ACLK_HEVC_DIV_MASK = 0x1f,
+
+ SPI2_PLL_SHIFT = 7,
+ SPI2_PLL_MASK = 1,
+ SPI2_PLL_SELECT_CODEC = 0,
+ SPI2_PLL_SELECT_GENERAL,
+
+ SPI2_DIV_SHIFT = 0,
+ SPI2_DIV_MASK = 0x7f,
+};
+
+/* CRU_MODE_CON */
+enum {
+ NPLL_WORK_SHIFT = 0xe,
+ NPLL_WORK_MASK = 3,
+ NPLL_WORK_SLOW = 0,
+ NPLL_WORK_NORMAL,
+ NPLL_WORK_DEEP,
+
+ GPLL_WORK_SHIFT = 0xc,
+ GPLL_WORK_MASK = 3,
+ GPLL_WORK_SLOW = 0,
+ GPLL_WORK_NORMAL,
+ GPLL_WORK_DEEP,
+
+ CPLL_WORK_SHIFT = 8,
+ CPLL_WORK_MASK = 3,
+ CPLL_WORK_SLOW = 0,
+ CPLL_WORK_NORMAL,
+ CPLL_WORK_DEEP,
+
+ DPLL_WORK_SHIFT = 4,
+ DPLL_WORK_MASK = 3,
+ DPLL_WORK_SLOW = 0,
+ DPLL_WORK_NORMAL,
+ DPLL_WORK_DEEP,
+
+ APLL_WORK_SHIFT = 0,
+ APLL_WORK_MASK = 3,
+ APLL_WORK_SLOW = 0,
+ APLL_WORK_NORMAL,
+ APLL_WORK_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+ CLKR_SHIFT = 8,
+ CLKR_MASK = 0x3f,
+
+ CLKOD_SHIFT = 0,
+ CLKOD_MASK = 0xf,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+ LOCK_SHIFT = 0x1f,
+ LOCK_MASK = 1,
+ LOCK_UNLOCK = 0,
+ LOCK_LOCK,
+
+ CLKF_SHIFT = 0,
+ CLKF_MASK = 0x1fff,
+};
+
+#endif
diff --git a/arch/arm/mach-rockchip/include/mach/grf_rk3288.h b/arch/arm/mach-rockchip/include/mach/grf_rk3288.h
new file mode 100644
index 0000000..0117a17
--- /dev/null
+++ b/arch/arm/mach-rockchip/include/mach/grf_rk3288.h
@@ -0,0 +1,768 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3288_H
+#define _ASM_ARCH_GRF_RK3288_H
+
+struct rk3288_grf_gpio_lh {
+ u32 l;
+ u32 h;
+};
+
+struct rk3288_grf {
+ u32 reserved[3];
+ u32 gpio1d_iomux;
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+
+ u32 gpio2c_iomux;
+ u32 reserved2;
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+
+ u32 gpio3c_iomux;
+ u32 gpio3dl_iomux;
+ u32 gpio3dh_iomux;
+ u32 gpio4al_iomux;
+
+ u32 gpio4ah_iomux;
+ u32 gpio4bl_iomux;
+ u32 reserved3;
+ u32 gpio4c_iomux;
+
+ u32 gpio4d_iomux;
+ u32 reserved4;
+ u32 gpio5b_iomux;
+ u32 gpio5c_iomux;
+
+ u32 reserved5;
+ u32 gpio6a_iomux;
+ u32 gpio6b_iomux;
+ u32 gpio6c_iomux;
+ u32 reserved6;
+ u32 gpio7a_iomux;
+ u32 gpio7b_iomux;
+ u32 gpio7cl_iomux;
+ u32 gpio7ch_iomux;
+ u32 reserved7;
+ u32 gpio8a_iomux;
+ u32 gpio8b_iomux;
+ u32 reserved8[30];
+ struct rk3288_grf_gpio_lh gpio_sr[8];
+ u32 gpio1_p[8][4];
+ u32 gpio1_e[8][4];
+ u32 gpio_smt;
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_status[22];
+ u32 reserved9[2];
+ u32 peridmac_con[4];
+ u32 ddrc0_con0;
+ u32 ddrc1_con0;
+ u32 cpu_con[5];
+ u32 reserved10[3];
+ u32 cpu_status0;
+ u32 reserved11;
+ u32 uoc0_con[5];
+ u32 uoc1_con[5];
+ u32 uoc2_con[4];
+ u32 uoc3_con[2];
+ u32 uoc4_con[2];
+ u32 pvtm_con[3];
+ u32 pvtm_status[3];
+ u32 io_vsel;
+ u32 saradc_testbit;
+ u32 tsadc_testbit_l;
+ u32 tsadc_testbit_h;
+ u32 os_reg[4];
+ u32 reserved12;
+ u32 soc_con15;
+ u32 soc_con16;
+};
+
+struct rk3288_sgrf {
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 reserved1[(0x20-0x18)/4];
+ u32 busdmac_con[2];
+ u32 reserved2[(0x40-0x28)/4];
+ u32 cpu_con[3];
+ u32 reserved3[(0x50-0x4c)/4];
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_con15;
+ u32 soc_con16;
+ u32 soc_con17;
+ u32 soc_con18;
+ u32 soc_con19;
+ u32 soc_con20;
+ u32 soc_con21;
+ u32 reserved4[(0x100-0x90)/4];
+ u32 soc_status[2];
+ u32 reserved5[(0x120-0x108)/4];
+ u32 fast_boot_addr;
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 1,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_LCDC0_DCLK,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 1,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_LCDC0_DEN,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 1,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_LCDC0_VSYNC,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 1,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_LCDC0_HSYNC,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 1,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_I2C3CAM_SDA,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 1,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_I2C3CAM_SCL,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+ GPIO3A7_SHIFT = 14,
+ GPIO3A7_MASK = 3,
+ GPIO3A7_GPIO = 0,
+ GPIO3A7_FLASH0_DATA7,
+ GPIO3A7_EMMC_DATA7,
+
+ GPIO3A6_SHIFT = 12,
+ GPIO3A6_MASK = 3,
+ GPIO3A6_GPIO = 0,
+ GPIO3A6_FLASH0_DATA6,
+ GPIO3A6_EMMC_DATA6,
+
+ GPIO3A5_SHIFT = 10,
+ GPIO3A5_MASK = 3,
+ GPIO3A5_GPIO = 0,
+ GPIO3A5_FLASH0_DATA5,
+ GPIO3A5_EMMC_DATA5,
+
+ GPIO3A4_SHIFT = 8,
+ GPIO3A4_MASK = 3,
+ GPIO3A4_GPIO = 0,
+ GPIO3A4_FLASH0_DATA4,
+ GPIO3A4_EMMC_DATA4,
+
+ GPIO3A3_SHIFT = 6,
+ GPIO3A3_MASK = 3,
+ GPIO3A3_GPIO = 0,
+ GPIO3A3_FLASH0_DATA3,
+ GPIO3A3_EMMC_DATA3,
+
+ GPIO3A2_SHIFT = 4,
+ GPIO3A2_MASK = 3,
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_FLASH0_DATA2,
+ GPIO3A2_EMMC_DATA2,
+
+ GPIO3A1_SHIFT = 2,
+ GPIO3A1_MASK = 3,
+ GPIO3A1_GPIO = 0,
+ GPIO3A1_FLASH0_DATA1,
+ GPIO3A1_EMMC_DATA1,
+
+ GPIO3A0_SHIFT = 0,
+ GPIO3A0_MASK = 3,
+ GPIO3A0_GPIO = 0,
+ GPIO3A0_FLASH0_DATA0,
+ GPIO3A0_EMMC_DATA0,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+ GPIO3B7_SHIFT = 14,
+ GPIO3B7_MASK = 1,
+ GPIO3B7_GPIO = 0,
+ GPIO3B7_FLASH0_CSN1,
+
+ GPIO3B6_SHIFT = 12,
+ GPIO3B6_MASK = 1,
+ GPIO3B6_GPIO = 0,
+ GPIO3B6_FLASH0_CSN0,
+
+ GPIO3B5_SHIFT = 10,
+ GPIO3B5_MASK = 1,
+ GPIO3B5_GPIO = 0,
+ GPIO3B5_FLASH0_WRN,
+
+ GPIO3B4_SHIFT = 8,
+ GPIO3B4_MASK = 1,
+ GPIO3B4_GPIO = 0,
+ GPIO3B4_FLASH0_CLE,
+
+ GPIO3B3_SHIFT = 6,
+ GPIO3B3_MASK = 1,
+ GPIO3B3_GPIO = 0,
+ GPIO3B3_FLASH0_ALE,
+
+ GPIO3B2_SHIFT = 4,
+ GPIO3B2_MASK = 1,
+ GPIO3B2_GPIO = 0,
+ GPIO3B2_FLASH0_RDN,
+
+ GPIO3B1_SHIFT = 2,
+ GPIO3B1_MASK = 3,
+ GPIO3B1_GPIO = 0,
+ GPIO3B1_FLASH0_WP,
+ GPIO3B1_EMMC_PWREN,
+
+ GPIO3B0_SHIFT = 0,
+ GPIO3B0_MASK = 1,
+ GPIO3B0_GPIO = 0,
+ GPIO3B0_FLASH0_RDY,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 3,
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_FLASH0_DQS,
+ GPIO3C2_EMMC_CLKOUT,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 3,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_FLASH0_CSN3,
+ GPIO3C1_EMMC_RSTNOUT,
+
+ GPIO3C0_SHIFT = 0,
+ GPIO3C0_MASK = 3,
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_FLASH0_CSN2,
+ GPIO3C0_EMMC_CMD,
+};
+
+/* GRF_GPIO4C_IOMUX */
+enum {
+ GPIO4C7_SHIFT = 14,
+ GPIO4C7_MASK = 1,
+ GPIO4C7_GPIO = 0,
+ GPIO4C7_SDIO0_DATA3,
+
+ GPIO4C6_SHIFT = 12,
+ GPIO4C6_MASK = 1,
+ GPIO4C6_GPIO = 0,
+ GPIO4C6_SDIO0_DATA2,
+
+ GPIO4C5_SHIFT = 10,
+ GPIO4C5_MASK = 1,
+ GPIO4C5_GPIO = 0,
+ GPIO4C5_SDIO0_DATA1,
+
+ GPIO4C4_SHIFT = 8,
+ GPIO4C4_MASK = 1,
+ GPIO4C4_GPIO = 0,
+ GPIO4C4_SDIO0_DATA0,
+
+ GPIO4C3_SHIFT = 6,
+ GPIO4C3_MASK = 1,
+ GPIO4C3_GPIO = 0,
+ GPIO4C3_UART0BT_RTSN,
+
+ GPIO4C2_SHIFT = 4,
+ GPIO4C2_MASK = 1,
+ GPIO4C2_GPIO = 0,
+ GPIO4C2_UART0BT_CTSN,
+
+ GPIO4C1_SHIFT = 2,
+ GPIO4C1_MASK = 1,
+ GPIO4C1_GPIO = 0,
+ GPIO4C1_UART0BT_SOUT,
+
+ GPIO4C0_SHIFT = 0,
+ GPIO4C0_MASK = 1,
+ GPIO4C0_GPIO = 0,
+ GPIO4C0_UART0BT_SIN,
+};
+
+/* GRF_GPIO5B_IOMUX */
+enum {
+ GPIO5B7_SHIFT = 14,
+ GPIO5B7_MASK = 3,
+ GPIO5B7_GPIO = 0,
+ GPIO5B7_SPI0_RXD,
+ GPIO5B7_TS0_DATA7,
+ GPIO5B7_UART4EXP_SIN,
+
+ GPIO5B6_SHIFT = 12,
+ GPIO5B6_MASK = 3,
+ GPIO5B6_GPIO = 0,
+ GPIO5B6_SPI0_TXD,
+ GPIO5B6_TS0_DATA6,
+ GPIO5B6_UART4EXP_SOUT,
+
+ GPIO5B5_SHIFT = 10,
+ GPIO5B5_MASK = 3,
+ GPIO5B5_GPIO = 0,
+ GPIO5B5_SPI0_CSN0,
+ GPIO5B5_TS0_DATA5,
+ GPIO5B5_UART4EXP_RTSN,
+
+ GPIO5B4_SHIFT = 8,
+ GPIO5B4_MASK = 3,
+ GPIO5B4_GPIO = 0,
+ GPIO5B4_SPI0_CLK,
+ GPIO5B4_TS0_DATA4,
+ GPIO5B4_UART4EXP_CTSN,
+
+ GPIO5B3_SHIFT = 6,
+ GPIO5B3_MASK = 3,
+ GPIO5B3_GPIO = 0,
+ GPIO5B3_UART1BB_RTSN,
+ GPIO5B3_TS0_DATA3,
+
+ GPIO5B2_SHIFT = 4,
+ GPIO5B2_MASK = 3,
+ GPIO5B2_GPIO = 0,
+ GPIO5B2_UART1BB_CTSN,
+ GPIO5B2_TS0_DATA2,
+
+ GPIO5B1_SHIFT = 2,
+ GPIO5B1_MASK = 3,
+ GPIO5B1_GPIO = 0,
+ GPIO5B1_UART1BB_SOUT,
+ GPIO5B1_TS0_DATA1,
+
+ GPIO5B0_SHIFT = 0,
+ GPIO5B0_MASK = 3,
+ GPIO5B0_GPIO = 0,
+ GPIO5B0_UART1BB_SIN,
+ GPIO5B0_TS0_DATA0,
+};
+
+/* GRF_GPIO5C_IOMUX */
+enum {
+ GPIO5C3_SHIFT = 6,
+ GPIO5C3_MASK = 1,
+ GPIO5C3_GPIO = 0,
+ GPIO5C3_TS0_ERR,
+
+ GPIO5C2_SHIFT = 4,
+ GPIO5C2_MASK = 1,
+ GPIO5C2_GPIO = 0,
+ GPIO5C2_TS0_CLK,
+
+ GPIO5C1_SHIFT = 2,
+ GPIO5C1_MASK = 1,
+ GPIO5C1_GPIO = 0,
+ GPIO5C1_TS0_VALID,
+
+ GPIO5C0_SHIFT = 0,
+ GPIO5C0_MASK = 3,
+ GPIO5C0_GPIO = 0,
+ GPIO5C0_SPI0_CSN1,
+ GPIO5C0_TS0_SYNC,
+};
+
+/* GRF_GPIO6B_IOMUX */
+enum {
+ GPIO6B3_SHIFT = 6,
+ GPIO6B3_MASK = 1,
+ GPIO6B3_GPIO = 0,
+ GPIO6B3_SPDIF_TX,
+
+ GPIO6B2_SHIFT = 4,
+ GPIO6B2_MASK = 1,
+ GPIO6B2_GPIO = 0,
+ GPIO6B2_I2C1AUDIO_SCL,
+
+ GPIO6B1_SHIFT = 2,
+ GPIO6B1_MASK = 1,
+ GPIO6B1_GPIO = 0,
+ GPIO6B1_I2C1AUDIO_SDA,
+
+ GPIO6B0_SHIFT = 0,
+ GPIO6B0_MASK = 1,
+ GPIO6B0_GPIO = 0,
+ GPIO6B0_I2S_CLK,
+};
+
+/* GRF_GPIO6C_IOMUX */
+enum {
+ GPIO6C6_SHIFT = 12,
+ GPIO6C6_MASK = 1,
+ GPIO6C6_GPIO = 0,
+ GPIO6C6_SDMMC0_DECTN,
+
+ GPIO6C5_SHIFT = 10,
+ GPIO6C5_MASK = 1,
+ GPIO6C5_GPIO = 0,
+ GPIO6C5_SDMMC0_CMD,
+
+ GPIO6C4_SHIFT = 8,
+ GPIO6C4_MASK = 3,
+ GPIO6C4_GPIO = 0,
+ GPIO6C4_SDMMC0_CLKOUT,
+ GPIO6C4_JTAG_TDO,
+
+ GPIO6C3_SHIFT = 6,
+ GPIO6C3_MASK = 3,
+ GPIO6C3_GPIO = 0,
+ GPIO6C3_SDMMC0_DATA3,
+ GPIO6C3_JTAG_TCK,
+
+ GPIO6C2_SHIFT = 4,
+ GPIO6C2_MASK = 3,
+ GPIO6C2_GPIO = 0,
+ GPIO6C2_SDMMC0_DATA2,
+ GPIO6C2_JTAG_TDI,
+
+ GPIO6C1_SHIFT = 2,
+ GPIO6C1_MASK = 3,
+ GPIO6C1_GPIO = 0,
+ GPIO6C1_SDMMC0_DATA1,
+ GPIO6C1_JTAG_TRSTN,
+
+ GPIO6C0_SHIFT = 0,
+ GPIO6C0_MASK = 3,
+ GPIO6C0_GPIO = 0,
+ GPIO6C0_SDMMC0_DATA0,
+ GPIO6C0_JTAG_TMS,
+};
+
+/* GRF_GPIO7A_IOMUX */
+enum {
+ GPIO7A7_SHIFT = 14,
+ GPIO7A7_MASK = 3,
+ GPIO7A7_GPIO = 0,
+ GPIO7A7_UART3GPS_SIN,
+ GPIO7A7_GPS_MAG,
+ GPIO7A7_HSADCT1_DATA0,
+
+ GPIO7A1_SHIFT = 2,
+ GPIO7A1_MASK = 1,
+ GPIO7A1_GPIO = 0,
+ GPIO7A1_PWM_1,
+
+ GPIO7A0_SHIFT = 0,
+ GPIO7A0_MASK = 3,
+ GPIO7A0_GPIO = 0,
+ GPIO7A0_PWM_0,
+ GPIO7A0_VOP0_PWM,
+ GPIO7A0_VOP1_PWM,
+};
+
+/* GRF_GPIO7B_IOMUX */
+enum {
+ GPIO7B7_SHIFT = 14,
+ GPIO7B7_MASK = 3,
+ GPIO7B7_GPIO = 0,
+ GPIO7B7_ISP_SHUTTERTRIG,
+ GPIO7B7_SPI1_TXD,
+
+ GPIO7B6_SHIFT = 12,
+ GPIO7B6_MASK = 3,
+ GPIO7B6_GPIO = 0,
+ GPIO7B6_ISP_PRELIGHTTRIG,
+ GPIO7B6_SPI1_RXD,
+
+ GPIO7B5_SHIFT = 10,
+ GPIO7B5_MASK = 3,
+ GPIO7B5_GPIO = 0,
+ GPIO7B5_ISP_FLASHTRIGOUT,
+ GPIO7B5_SPI1_CSN0,
+
+ GPIO7B4_SHIFT = 8,
+ GPIO7B4_MASK = 3,
+ GPIO7B4_GPIO = 0,
+ GPIO7B4_ISP_SHUTTEREN,
+ GPIO7B4_SPI1_CLK,
+
+ GPIO7B3_SHIFT = 6,
+ GPIO7B3_MASK = 3,
+ GPIO7B3_GPIO = 0,
+ GPIO7B3_USB_DRVVBUS1,
+ GPIO7B3_EDP_HOTPLUG,
+
+ GPIO7B2_SHIFT = 4,
+ GPIO7B2_MASK = 3,
+ GPIO7B2_GPIO = 0,
+ GPIO7B2_UART3GPS_RTSN,
+ GPIO7B2_USB_DRVVBUS0,
+
+ GPIO7B1_SHIFT = 2,
+ GPIO7B1_MASK = 3,
+ GPIO7B1_GPIO = 0,
+ GPIO7B1_UART3GPS_CTSN,
+ GPIO7B1_GPS_RFCLK,
+ GPIO7B1_GPST1_CLK,
+
+ GPIO7B0_SHIFT = 0,
+ GPIO7B0_MASK = 3,
+ GPIO7B0_GPIO = 0,
+ GPIO7B0_UART3GPS_SOUT,
+ GPIO7B0_GPS_SIG,
+ GPIO7B0_HSADCT1_DATA1,
+};
+
+/* GRF_GPIO7CL_IOMUX */
+enum {
+ GPIO7C3_SHIFT = 12,
+ GPIO7C3_MASK = 3,
+ GPIO7C3_GPIO = 0,
+ GPIO7C3_I2C5HDMI_SDA,
+ GPIO7C3_EDPHDMII2C_SDA,
+
+ GPIO7C2_SHIFT = 8,
+ GPIO7C2_MASK = 1,
+ GPIO7C2_GPIO = 0,
+ GPIO7C2_I2C4TP_SCL,
+
+ GPIO7C1_SHIFT = 4,
+ GPIO7C1_MASK = 1,
+ GPIO7C1_GPIO = 0,
+ GPIO7C1_I2C4TP_SDA,
+
+ GPIO7C0_SHIFT = 0,
+ GPIO7C0_MASK = 3,
+ GPIO7C0_GPIO = 0,
+ GPIO7C0_ISP_FLASHTRIGIN,
+ GPIO7C0_EDPHDMI_CECINOUTT1,
+};
+
+/* GRF_GPIO7CH_IOMUX */
+enum {
+ GPIO7C7_SHIFT = 12,
+ GPIO7C7_MASK = 7,
+ GPIO7C7_GPIO = 0,
+ GPIO7C7_UART2DBG_SOUT,
+ GPIO7C7_UART2DBG_SIROUT,
+ GPIO7C7_PWM_3,
+ GPIO7C7_EDPHDMI_CECINOUT,
+
+ GPIO7C6_SHIFT = 8,
+ GPIO7C6_MASK = 3,
+ GPIO7C6_GPIO = 0,
+ GPIO7C6_UART2DBG_SIN,
+ GPIO7C6_UART2DBG_SIRIN,
+ GPIO7C6_PWM_2,
+
+ GPIO7C4_SHIFT = 0,
+ GPIO7C4_MASK = 3,
+ GPIO7C4_GPIO = 0,
+ GPIO7C4_I2C5HDMI_SCL,
+ GPIO7C4_EDPHDMII2C_SCL,
+};
+
+/* GRF_GPIO8A_IOMUX */
+enum {
+ GPIO8A7_SHIFT = 14,
+ GPIO8A7_MASK = 3,
+ GPIO8A7_GPIO = 0,
+ GPIO8A7_SPI2_CSN0,
+ GPIO8A7_SC_DETECT,
+ GPIO8A7_RESERVE,
+
+ GPIO8A6_SHIFT = 12,
+ GPIO8A6_MASK = 3,
+ GPIO8A6_GPIO = 0,
+ GPIO8A6_SPI2_CLK,
+ GPIO8A6_SC_IO,
+ GPIO8A6_RESERVE,
+
+ GPIO8A5_SHIFT = 10,
+ GPIO8A5_MASK = 3,
+ GPIO8A5_GPIO = 0,
+ GPIO8A5_I2C2SENSOR_SCL,
+ GPIO8A5_SC_CLK,
+
+ GPIO8A4_SHIFT = 8,
+ GPIO8A4_MASK = 3,
+ GPIO8A4_GPIO = 0,
+ GPIO8A4_I2C2SENSOR_SDA,
+ GPIO8A4_SC_RST,
+
+ GPIO8A3_SHIFT = 6,
+ GPIO8A3_MASK = 3,
+ GPIO8A3_GPIO = 0,
+ GPIO8A3_SPI2_CSN1,
+ GPIO8A3_SC_IOT1,
+
+ GPIO8A2_SHIFT = 4,
+ GPIO8A2_MASK = 1,
+ GPIO8A2_GPIO = 0,
+ GPIO8A2_SC_DETECTT1,
+
+ GPIO8A1_SHIFT = 2,
+ GPIO8A1_MASK = 3,
+ GPIO8A1_GPIO = 0,
+ GPIO8A1_PS2_DATA,
+ GPIO8A1_SC_VCC33V,
+
+ GPIO8A0_SHIFT = 0,
+ GPIO8A0_MASK = 3,
+ GPIO8A0_GPIO = 0,
+ GPIO8A0_PS2_CLK,
+ GPIO8A0_SC_VCC18V,
+};
+
+/* GRF_GPIO8B_IOMUX */
+enum {
+ GPIO8B1_SHIFT = 2,
+ GPIO8B1_MASK = 3,
+ GPIO8B1_GPIO = 0,
+ GPIO8B1_SPI2_TXD,
+ GPIO8B1_SC_CLK,
+
+ GPIO8B0_SHIFT = 0,
+ GPIO8B0_MASK = 3,
+ GPIO8B0_GPIO = 0,
+ GPIO8B0_SPI2_RXD,
+ GPIO8B0_SC_RST,
+};
+
+/* GRF_SOC_CON0 */
+enum {
+ PAUSE_MMC_PERI_SHIFT = 0xf,
+ PAUSE_MMC_PERI_MASK = 1,
+
+ PAUSE_EMEM_PERI_SHIFT = 0xe,
+ PAUSE_EMEM_PERI_MASK = 1,
+
+ PAUSE_USB_PERI_SHIFT = 0xd,
+ PAUSE_USB_PERI_MASK = 1,
+
+ GRF_FORCE_JTAG_SHIFT = 0xc,
+ GRF_FORCE_JTAG_MASK = 1,
+
+ GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
+ GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
+
+ GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
+ GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
+
+ DDR1_16BIT_EN_SHIFT = 9,
+ DDR1_16BIT_EN_MASK = 1,
+
+ DDR0_16BIT_EN_SHIFT = 8,
+ DDR0_16BIT_EN_MASK = 1,
+
+ VCODEC_SHIFT = 7,
+ VCODEC_MASK = 1,
+ VCODEC_SELECT_VEPU_ACLK = 0,
+ VCODEC_SELECT_VDPU_ACLK,
+
+ UPCTL1_C_ACTIVE_IN_SHIFT = 6,
+ UPCTL1_C_ACTIVE_IN_MASK = 1,
+ UPCTL1_C_ACTIVE_IN_MAY = 0,
+ UPCTL1_C_ACTIVE_IN_WILL,
+
+ UPCTL0_C_ACTIVE_IN_SHIFT = 5,
+ UPCTL0_C_ACTIVE_IN_MASK = 1,
+ UPCTL0_C_ACTIVE_IN_MAY = 0,
+ UPCTL0_C_ACTIVE_IN_WILL,
+
+ MSCH1_MAINDDR3_SHIFT = 4,
+ MSCH1_MAINDDR3_MASK = 1,
+ MSCH1_MAINDDR3_DDR3 = 1,
+
+ MSCH0_MAINDDR3_SHIFT = 3,
+ MSCH0_MAINDDR3_MASK = 1,
+ MSCH0_MAINDDR3_DDR3 = 1,
+
+ MSCH1_MAINPARTIALPOP_SHIFT = 2,
+ MSCH1_MAINPARTIALPOP_MASK = 1,
+
+ MSCH0_MAINPARTIALPOP_SHIFT = 1,
+ MSCH0_MAINPARTIALPOP_MASK = 1,
+};
+
+/* GRF_SOC_CON2 */
+enum {
+ UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
+ UPCTL1_LPDDR3_ODT_EN_MASK = 1,
+ UPCTL1_LPDDR3_ODT_EN_ODT = 1,
+
+ UPCTL1_BST_DIABLE_SHIFT = 0xc,
+ UPCTL1_BST_DIABLE_MASK = 1,
+ UPCTL1_BST_DIABLE_DISABLE = 1,
+
+ LPDDR3_EN1_SHIFT = 0xb,
+ LPDDR3_EN1_MASK = 1,
+ LPDDR3_EN1_LPDDR3 = 1,
+
+ UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
+ UPCTL0_LPDDR3_ODT_EN_MASK = 1,
+ UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
+
+ UPCTL0_BST_DIABLE_SHIFT = 9,
+ UPCTL0_BST_DIABLE_MASK = 1,
+ UPCTL0_BST_DIABLE_DISABLE = 1,
+
+ LPDDR3_EN0_SHIFT = 8,
+ LPDDR3_EN0_MASK = 1,
+ LPDDR3_EN0_LPDDR3 = 1,
+
+ GRF_POC_FLASH0_CTRL_SHIFT = 7,
+ GRF_POC_FLASH0_CTRL_MASK = 1,
+ GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
+ GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
+
+ SIMCARD_MUX_SHIFT = 6,
+ SIMCARD_MUX_MASK = 1,
+ SIMCARD_MUX_USE_A = 1,
+ SIMCARD_MUX_USE_B = 0,
+
+ GRF_SPDIF_2CH_EN_SHIFT = 1,
+ GRF_SPDIF_2CH_EN_MASK = 1,
+ GRF_SPDIF_2CH_EN_8CH = 0,
+ GRF_SPDIF_2CH_EN_2CH,
+
+ PWM_SHIFT = 0,
+ PWM_MASK = 1,
+ PWM_RK = 1,
+ PWM_PWM = 0,
+};
+
+#endif
diff --git a/arch/arm/mach-rockchip/include/mach/hardware.h b/arch/arm/mach-rockchip/include/mach/hardware.h
new file mode 100644
index 0000000..b0afd1f
--- /dev/null
+++ b/arch/arm/mach-rockchip/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set)
+#define RK_SETBITS(set) RK_CLRSETBITS(0, set)
+#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
+
+#define rk_clrsetreg(addr, clr, set) writel((clr) << 16 | (set), addr)
+#define rk_clrreg(addr, clr) writel((clr) << 16, addr)
+#define rk_setreg(addr, set) writel(set, addr)
+
+#endif
diff --git a/arch/arm/mach-rockchip/include/mach/rockchip-regs.h b/arch/arm/mach-rockchip/include/mach/rk3188-regs.h
similarity index 72%
rename from arch/arm/mach-rockchip/include/mach/rockchip-regs.h
rename to arch/arm/mach-rockchip/include/mach/rk3188-regs.h
index a6a1c64..f147fe2 100644
--- a/arch/arm/mach-rockchip/include/mach/rockchip-regs.h
+++ b/arch/arm/mach-rockchip/include/mach/rk3188-regs.h
@@ -11,8 +11,8 @@
* GNU General Public License for more details.
*/
-#ifndef __MACH_ROCKCHIP_REGS_H
-#define __MACH_ROCKCHIP_REGS_H
+#ifndef __MACH_RK3188_REGS_H
+#define __MACH_RK3188_REGS_H
#define RK_CRU_BASE 0x20000000
#define RK_GRF_BASE 0x20008000
@@ -22,4 +22,10 @@
#define RK_SOC_CON0_REMAP (1 << 12)
-#endif /* __MACH_ROCKCHIP_REGS_H */
+/* UART */
+#define RK3188_UART0_BASE 0x10124000
+#define RK3188_UART1_BASE 0x10126000
+#define RK3188_UART2_BASE 0x20064000
+#define RK3188_UART3_BASE 0x20068000
+
+#endif /* __MACH_RK3188_REGS_H */
diff --git a/arch/arm/mach-rockchip/include/mach/rk3288-regs.h b/arch/arm/mach-rockchip/include/mach/rk3288-regs.h
new file mode 100644
index 0000000..a83a3a8
--- /dev/null
+++ b/arch/arm/mach-rockchip/include/mach/rk3288-regs.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_RK3288_REGS_H
+#define __MACH_RK3288_REGS_H
+
+#define RK3288_CRU_BASE 0xff760000
+#define RK3288_GRF_BASE 0xff770000
+
+/* UART */
+#define RK3288_UART0_BASE 0xff180000
+#define RK3288_UART1_BASE 0xff190000
+#define RK3288_UART2_BASE 0xff690000
+#define RK3288_UART3_BASE 0xff1b0000
+#define RK3288_UART4_BASE 0xff1c0000
+
+#endif /* __MACH_RK3288_REGS_H */
diff --git a/arch/arm/mach-rockchip/core.c b/arch/arm/mach-rockchip/rk3188.c
similarity index 96%
rename from arch/arm/mach-rockchip/core.c
rename to arch/arm/mach-rockchip/rk3188.c
index 2428fee..e7cbf36 100644
--- a/arch/arm/mach-rockchip/core.c
+++ b/arch/arm/mach-rockchip/rk3188.c
@@ -15,7 +15,7 @@
#include <common.h>
#include <init.h>
#include <restart.h>
-#include <mach/rockchip-regs.h>
+#include <mach/rk3188-regs.h>
static void __noreturn rockchip_restart_soc(struct restart_handler *rst)
{
diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c
new file mode 100644
index 0000000..4e8fb4a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <init.h>
+#include <restart.h>
+#include <reset_source.h>
+#include <bootsource.h>
+#include <mach/rk3288-regs.h>
+#include <mach/cru_rk3288.h>
+#include <mach/hardware.h>
+
+static void __noreturn rockchip_restart_soc(struct restart_handler *rst)
+{
+ struct rk3288_cru *cru = (struct rk3288_cru *)RK3288_CRU_BASE;
+
+ /* cold reset */
+ writel(RK_CLRBITS(0xffff), &cru->cru_mode_con);
+ writel(0xfdb9, &cru->cru_glb_srst_fst_value);
+
+ hang();
+}
+
+static void rk3288_detect_reset_reason(void)
+{
+ struct rk3288_cru *cru = (struct rk3288_cru *)RK3288_CRU_BASE;
+
+ switch (cru->cru_glb_rst_st) {
+ case (1 << 0):
+ reset_source_set(RESET_POR);
+ break;
+ case (1 << 1):
+ reset_source_set(RESET_RST);
+ break;
+ case (1 << 2):
+ case (1 << 3):
+ reset_source_set(RESET_THERM);
+ break;
+ case (1 << 4):
+ case (1 << 5):
+ reset_source_set(RESET_WDG);
+ break;
+ default:
+ reset_source_set(RESET_UKWN);
+ break;
+ }
+}
+
+static int rk3288_init(void)
+{
+ restart_handler_register_fn(rockchip_restart_soc);
+
+ if (IS_ENABLED(CONFIG_RESET_SOURCE))
+ rk3288_detect_reset_reason();
+
+ return 0;
+}
+postcore_initcall(rk3288_init);
+
+/*
+ * ATM we are not able to determine the boot source.
+ * So let's handle the environment on eMMC, regardless which device
+ * we are booting from.
+ */
+static int rk3288_env_init(void)
+{
+ const char *envpath = "/chosen/environment-emmc";
+ int ret;
+
+ bootsource_set(BOOTSOURCE_MMC);
+ bootsource_set_instance(0);
+
+ ret = of_device_enable_path(envpath);
+ if (ret < 0)
+ pr_warn("Failed to enable environment partition '%s' (%d)\n",
+ envpath, ret);
+
+ return 0;
+}
+device_initcall(rk3288_env_init);
--
1.9.1
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barebox@lists.infradead.org
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^ permalink raw reply related
* [PATCH v2 4/8] clk: Add RK3288 clock driver
From: Wadim Egorov @ 2016-08-24 12:49 UTC (permalink / raw)
To: barebox
In-Reply-To: <1472042970-35151-1-git-send-email-w.egorov@phytec.de>
Add clk driver for RK3288 SoC. This driver comes from the Linux kernel.
Based on kernel v4.4
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
drivers/clk/rockchip/Makefile | 4 +-
drivers/clk/rockchip/clk-rk3288.c | 836 ++++++++++++++++++++++++++++++++++++++
2 files changed, 839 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/rockchip/clk-rk3288.c
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 865542a..e43f573 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -1 +1,3 @@
-obj-y += clk-cpu.o clk-pll.o clk-rk3188.o clk.o
+obj-y += clk-cpu.o clk-pll.o clk.o
+obj-$(CONFIG_ARCH_RK3188) += clk-rk3188.o
+obj-$(CONFIG_ARCH_RK3288) += clk-rk3288.o
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
new file mode 100644
index 0000000..bb111e1
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -0,0 +1,836 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <linux/clk.h>
+#include <of.h>
+#include <of_address.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include "clk.h"
+#include <linux/barebox-wrapper.h>
+#include <init.h>
+
+#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
+#define RK3288_GRF_SOC_STATUS1 0x284
+
+#define CLK_SET_RATE_NO_REPARENT 0
+#define CLK_DIVIDER_READ_ONLY 0
+
+enum rk3288_plls {
+ apll, dpll, cpll, gpll, npll,
+};
+
+static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
+ RK3066_PLL_RATE(2208000000, 1, 92, 1),
+ RK3066_PLL_RATE(2184000000, 1, 91, 1),
+ RK3066_PLL_RATE(2160000000, 1, 90, 1),
+ RK3066_PLL_RATE(2136000000, 1, 89, 1),
+ RK3066_PLL_RATE(2112000000, 1, 88, 1),
+ RK3066_PLL_RATE(2088000000, 1, 87, 1),
+ RK3066_PLL_RATE(2064000000, 1, 86, 1),
+ RK3066_PLL_RATE(2040000000, 1, 85, 1),
+ RK3066_PLL_RATE(2016000000, 1, 84, 1),
+ RK3066_PLL_RATE(1992000000, 1, 83, 1),
+ RK3066_PLL_RATE(1968000000, 1, 82, 1),
+ RK3066_PLL_RATE(1944000000, 1, 81, 1),
+ RK3066_PLL_RATE(1920000000, 1, 80, 1),
+ RK3066_PLL_RATE(1896000000, 1, 79, 1),
+ RK3066_PLL_RATE(1872000000, 1, 78, 1),
+ RK3066_PLL_RATE(1848000000, 1, 77, 1),
+ RK3066_PLL_RATE(1824000000, 1, 76, 1),
+ RK3066_PLL_RATE(1800000000, 1, 75, 1),
+ RK3066_PLL_RATE(1776000000, 1, 74, 1),
+ RK3066_PLL_RATE(1752000000, 1, 73, 1),
+ RK3066_PLL_RATE(1728000000, 1, 72, 1),
+ RK3066_PLL_RATE(1704000000, 1, 71, 1),
+ RK3066_PLL_RATE(1680000000, 1, 70, 1),
+ RK3066_PLL_RATE(1656000000, 1, 69, 1),
+ RK3066_PLL_RATE(1632000000, 1, 68, 1),
+ RK3066_PLL_RATE(1608000000, 1, 67, 1),
+ RK3066_PLL_RATE(1560000000, 1, 65, 1),
+ RK3066_PLL_RATE(1512000000, 1, 63, 1),
+ RK3066_PLL_RATE(1488000000, 1, 62, 1),
+ RK3066_PLL_RATE(1464000000, 1, 61, 1),
+ RK3066_PLL_RATE(1440000000, 1, 60, 1),
+ RK3066_PLL_RATE(1416000000, 1, 59, 1),
+ RK3066_PLL_RATE(1392000000, 1, 58, 1),
+ RK3066_PLL_RATE(1368000000, 1, 57, 1),
+ RK3066_PLL_RATE(1344000000, 1, 56, 1),
+ RK3066_PLL_RATE(1320000000, 1, 55, 1),
+ RK3066_PLL_RATE(1296000000, 1, 54, 1),
+ RK3066_PLL_RATE(1272000000, 1, 53, 1),
+ RK3066_PLL_RATE(1248000000, 1, 52, 1),
+ RK3066_PLL_RATE(1224000000, 1, 51, 1),
+ RK3066_PLL_RATE(1200000000, 1, 50, 1),
+ RK3066_PLL_RATE(1188000000, 2, 99, 1),
+ RK3066_PLL_RATE(1176000000, 1, 49, 1),
+ RK3066_PLL_RATE(1128000000, 1, 47, 1),
+ RK3066_PLL_RATE(1104000000, 1, 46, 1),
+ RK3066_PLL_RATE(1008000000, 1, 84, 2),
+ RK3066_PLL_RATE( 912000000, 1, 76, 2),
+ RK3066_PLL_RATE( 891000000, 8, 594, 2),
+ RK3066_PLL_RATE( 888000000, 1, 74, 2),
+ RK3066_PLL_RATE( 816000000, 1, 68, 2),
+ RK3066_PLL_RATE( 798000000, 2, 133, 2),
+ RK3066_PLL_RATE( 792000000, 1, 66, 2),
+ RK3066_PLL_RATE( 768000000, 1, 64, 2),
+ RK3066_PLL_RATE( 742500000, 8, 495, 2),
+ RK3066_PLL_RATE( 696000000, 1, 58, 2),
+ RK3066_PLL_RATE( 600000000, 1, 50, 2),
+ RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
+ RK3066_PLL_RATE( 552000000, 1, 46, 2),
+ RK3066_PLL_RATE( 504000000, 1, 84, 4),
+ RK3066_PLL_RATE( 500000000, 3, 125, 2),
+ RK3066_PLL_RATE( 456000000, 1, 76, 4),
+ RK3066_PLL_RATE( 408000000, 1, 68, 4),
+ RK3066_PLL_RATE( 400000000, 3, 100, 2),
+ RK3066_PLL_RATE( 384000000, 2, 128, 4),
+ RK3066_PLL_RATE( 360000000, 1, 60, 4),
+ RK3066_PLL_RATE( 312000000, 1, 52, 4),
+ RK3066_PLL_RATE( 300000000, 1, 50, 4),
+ RK3066_PLL_RATE( 297000000, 2, 198, 8),
+ RK3066_PLL_RATE( 252000000, 1, 84, 8),
+ RK3066_PLL_RATE( 216000000, 1, 72, 8),
+ RK3066_PLL_RATE( 148500000, 2, 99, 8),
+ RK3066_PLL_RATE( 126000000, 1, 84, 16),
+ RK3066_PLL_RATE( 48000000, 1, 64, 32),
+ { /* sentinel */ },
+};
+
+#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
+#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
+#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
+#define RK3288_DIV_ACLK_CORE_MP_SHIFT 4
+#define RK3288_DIV_L2RAM_MASK 0x7
+#define RK3288_DIV_L2RAM_SHIFT 0
+#define RK3288_DIV_ATCLK_MASK 0x1f
+#define RK3288_DIV_ATCLK_SHIFT 4
+#define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f
+#define RK3288_DIV_PCLK_DBGPRE_SHIFT 9
+
+#define RK3288_CLKSEL0(_core_m0, _core_mp) \
+ { \
+ .reg = RK3288_CLKSEL_CON(0), \
+ .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
+ RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
+ HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
+ RK3288_DIV_ACLK_CORE_MP_SHIFT), \
+ }
+#define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \
+ { \
+ .reg = RK3288_CLKSEL_CON(37), \
+ .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
+ RK3288_DIV_L2RAM_SHIFT) | \
+ HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
+ RK3288_DIV_ATCLK_SHIFT) | \
+ HIWORD_UPDATE(_pclk_dbg_pre, \
+ RK3288_DIV_PCLK_DBGPRE_MASK, \
+ RK3288_DIV_PCLK_DBGPRE_SHIFT), \
+ }
+
+#define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
+ { \
+ .prate = _prate, \
+ .divs = { \
+ RK3288_CLKSEL0(_core_m0, _core_mp), \
+ RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \
+ }, \
+ }
+
+static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
+ RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
+ RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
+};
+
+static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
+ .core_reg = RK3288_CLKSEL_CON(0),
+ .div_core_shift = 8,
+ .div_core_mask = 0x1f,
+ .mux_core_shift = 15,
+};
+
+PNAME(mux_pll_p) = { "xin24m", "xin32k" };
+PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
+PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
+PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
+
+PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
+PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
+PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
+PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
+PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
+
+PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
+PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
+PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
+PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
+PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
+PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
+PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
+PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
+PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
+PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
+PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
+PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
+PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
+PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
+PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
+
+PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2",
+ "sclk_otgphy0" };
+PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
+PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
+
+static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
+ RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
+ [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
+ RK3288_MODE_CON, 4, 5, 0, NULL),
+ [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
+ RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
+ RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
+ RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+};
+
+static struct clk_div_table div_hclk_cpu_t[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 3, .div = 4 },
+ { /* sentinel */},
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 1
+ */
+
+ GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(0), 1, GFLAGS),
+ GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(0), 2, GFLAGS),
+
+ COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 0, GFLAGS),
+ COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 1, GFLAGS),
+ COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 2, GFLAGS),
+ COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 3, GFLAGS),
+ COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 4, GFLAGS),
+ COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 5, GFLAGS),
+ COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 6, GFLAGS),
+ COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
+ RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 7, GFLAGS),
+ COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3288_CLKGATE_CON(12), 8, GFLAGS),
+ GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
+ RK3288_CLKGATE_CON(12), 9, GFLAGS),
+ GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(12), 10, GFLAGS),
+ GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
+ RK3288_CLKGATE_CON(12), 11, GFLAGS),
+
+ GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(0), 8, GFLAGS),
+ GATE(0, "gpll_ddr", "gpll", 0,
+ RK3288_CLKGATE_CON(0), 9, GFLAGS),
+ COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
+ DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
+
+ GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
+ DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
+ GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(0), 3, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
+ RK3288_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
+ RK3288_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(0, "c2c_host", "aclk_cpu_src", 0,
+ RK3288_CLKGATE_CON(13), 8, GFLAGS),
+ COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
+ RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
+ RK3288_CLKGATE_CON(5), 4, GFLAGS),
+ GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(0), 7, GFLAGS),
+
+ COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(4), 1, GFLAGS),
+ COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(8), 0,
+ RK3288_CLKGATE_CON(4), 2, GFLAGS),
+ MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
+ COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
+ RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
+ RK3288_CLKGATE_CON(4), 0, GFLAGS),
+ GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
+ RK3288_CLKGATE_CON(4), 3, GFLAGS),
+
+ MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
+ COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0,
+ RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(4), 4, GFLAGS),
+ COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
+ RK3288_CLKSEL_CON(9), 0,
+ RK3288_CLKGATE_CON(4), 5, GFLAGS),
+ COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
+ RK3288_CLKSEL_CON(5), 8, 2, MFLAGS,
+ RK3288_CLKGATE_CON(4), 6, GFLAGS),
+ COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
+ RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(4), 7, GFLAGS),
+ COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
+ RK3288_CLKSEL_CON(41), 0,
+ RK3288_CLKGATE_CON(4), 8, GFLAGS),
+ COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
+ RK3288_CLKSEL_CON(40), 8, 2, MFLAGS,
+ RK3288_CLKGATE_CON(4), 9, GFLAGS),
+
+ GATE(0, "sclk_acc_efuse", "xin24m", 0,
+ RK3288_CLKGATE_CON(0), 12, GFLAGS),
+ GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
+ RK3288_CLKGATE_CON(1), 0, GFLAGS),
+ GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
+ RK3288_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
+ RK3288_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
+ RK3288_CLKGATE_CON(1), 3, GFLAGS),
+ GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
+ RK3288_CLKGATE_CON(1), 4, GFLAGS),
+ GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
+ RK3288_CLKGATE_CON(1), 5, GFLAGS),
+ /*
+ * Clock-Architecture Diagram 2
+ */
+
+ COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
+ RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(3), 9, GFLAGS),
+ COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
+ RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(3), 11, GFLAGS),
+ /*
+ * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
+ * so we ignore the mux and make clocks nodes as following,
+ */
+ GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
+ RK3288_CLKGATE_CON(9), 0, GFLAGS),
+ /*
+ * We introduce a virtul node of hclk_vodec_pre_v to split one clock
+ * struct with a gate and a fix divider into two node in software.
+ */
+ GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
+ RK3288_CLKGATE_CON(3), 10, GFLAGS),
+ GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
+ RK3288_CLKGATE_CON(9), 1, GFLAGS),
+
+ COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(3), 0, GFLAGS),
+ DIV(0, "hclk_vio", "aclk_vio0", 0,
+ RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+ COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(3), 2, GFLAGS),
+
+ COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
+ RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(3), 5, GFLAGS),
+ COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
+ RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(3), 4, GFLAGS),
+
+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
+ RK3288_CLKGATE_CON(3), 1, GFLAGS),
+ COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
+ RK3288_CLKGATE_CON(3), 3, GFLAGS),
+
+ COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
+ RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
+ RK3288_CLKGATE_CON(3), 12, GFLAGS),
+ COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3288_CLKGATE_CON(3), 13, GFLAGS),
+
+ COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3288_CLKGATE_CON(3), 14, GFLAGS),
+ COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3288_CLKGATE_CON(3), 15, GFLAGS),
+
+ GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
+ RK3288_CLKGATE_CON(5), 12, GFLAGS),
+ GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
+ RK3288_CLKGATE_CON(5), 11, GFLAGS),
+
+ COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(13), 13, GFLAGS),
+ DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
+ RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
+
+ COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(13), 14, GFLAGS),
+ COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(13), 15, GFLAGS),
+
+ COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
+ RK3288_CLKGATE_CON(3), 7, GFLAGS),
+ COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
+ RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
+
+ DIV(0, "pclk_pd_alive", "gpll", 0,
+ RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
+ COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(5), 8, GFLAGS),
+
+ COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
+ RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(5), 7, GFLAGS),
+
+ COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(2), 0, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
+ RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+ RK3288_CLKGATE_CON(2), 3, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
+ RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+ RK3288_CLKGATE_CON(2), 2, GFLAGS),
+ GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(2), 1, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 3
+ */
+
+ COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(2), 9, GFLAGS),
+ COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RK3288_CLKGATE_CON(2), 10, GFLAGS),
+ COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(2), 11, GFLAGS),
+
+ COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
+ RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3288_CLKGATE_CON(13), 0, GFLAGS),
+ COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
+ RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3288_CLKGATE_CON(13), 1, GFLAGS),
+ COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
+ RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3288_CLKGATE_CON(13), 2, GFLAGS),
+ COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
+ RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3288_CLKGATE_CON(13), 3, GFLAGS),
+
+ MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
+
+ MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
+ MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
+
+ MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
+ MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
+
+ MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
+
+ COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
+ RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(4), 11, GFLAGS),
+ COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
+ RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(4), 10, GFLAGS),
+
+ GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(13), 4, GFLAGS),
+ GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(13), 5, GFLAGS),
+ GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(13), 6, GFLAGS),
+ GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
+ RK3288_CLKGATE_CON(13), 7, GFLAGS),
+
+ COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
+ RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
+ RK3288_CLKGATE_CON(2), 7, GFLAGS),
+
+ COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
+ RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
+ RK3288_CLKGATE_CON(2), 8, GFLAGS),
+
+ GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
+ RK3288_CLKGATE_CON(5), 13, GFLAGS),
+
+ COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3288_CLKGATE_CON(5), 5, GFLAGS),
+ COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(5), 6, GFLAGS),
+
+ COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
+ RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(1), 8, GFLAGS),
+ COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(17), 0,
+ RK3288_CLKGATE_CON(1), 9, GFLAGS),
+ MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(13), 8, 2, MFLAGS),
+ MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
+ COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
+ RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(1), 10, GFLAGS),
+ COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(18), 0,
+ RK3288_CLKGATE_CON(1), 11, GFLAGS),
+ MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(14), 8, 2, MFLAGS),
+ COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
+ RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(1), 12, GFLAGS),
+ COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(19), 0,
+ RK3288_CLKGATE_CON(1), 13, GFLAGS),
+ MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(15), 8, 2, MFLAGS),
+ COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
+ RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(1), 14, GFLAGS),
+ COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(20), 0,
+ RK3288_CLKGATE_CON(1), 15, GFLAGS),
+ MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(16), 8, 2, MFLAGS),
+ COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
+ RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
+ RK3288_CLKGATE_CON(2), 12, GFLAGS),
+ COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(7), 0,
+ RK3288_CLKGATE_CON(2), 13, GFLAGS),
+ MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
+
+ COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(2), 5, GFLAGS),
+ MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
+ GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
+ RK3288_CLKGATE_CON(5), 3, GFLAGS),
+ GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
+ RK3288_CLKGATE_CON(5), 2, GFLAGS),
+ GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
+ RK3288_CLKGATE_CON(5), 0, GFLAGS),
+ GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
+ RK3288_CLKGATE_CON(5), 1, GFLAGS),
+
+ COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
+ RK3288_CLKGATE_CON(2), 6, GFLAGS),
+ MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
+ RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
+
+ GATE(0, "jtag", "ext_jtag", 0,
+ RK3288_CLKGATE_CON(4), 14, GFLAGS),
+
+ COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
+ RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
+ RK3288_CLKGATE_CON(5), 14, GFLAGS),
+ COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
+ RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
+ RK3288_CLKGATE_CON(3), 6, GFLAGS),
+ GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
+ RK3288_CLKGATE_CON(13), 9, GFLAGS),
+ DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
+ RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
+ MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
+ RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 4
+ */
+
+ /* aclk_cpu gates */
+ GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
+ GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
+ GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
+ GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
+ GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
+ GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
+ GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
+ GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
+
+ /* hclk_cpu gates */
+ GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
+ GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
+ GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
+ GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
+
+ /* pclk_cpu gates */
+ GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
+ GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
+ GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
+ GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
+ GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
+ GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
+ GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
+ GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
+ GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
+
+ /* ddrctrl [DDR Controller PHY clock] gates */
+ GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
+ GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
+
+ /* ddrphy gates */
+ GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
+ GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
+
+ /* aclk_peri gates */
+ GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
+ GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
+ GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
+ GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
+ GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
+
+ /* hclk_peri gates */
+ GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
+ GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
+ GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
+ GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
+ GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
+ GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
+ GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
+ GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
+ GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
+ GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
+ GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
+ GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
+ GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
+ GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
+ GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
+ GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
+
+ /* pclk_peri gates */
+ GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
+ GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
+ GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
+ GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
+
+ GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
+ GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
+ GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
+ GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
+ GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
+
+ /* sclk_gpu gates */
+ GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
+
+ /* pclk_pd_alive gates */
+ GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
+ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
+ GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
+ GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
+ GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
+ GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
+
+ /* pclk_pd_pmu gates */
+ GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
+ GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
+ GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
+ GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
+ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
+
+ /* hclk_vio gates */
+ GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
+ GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
+ GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
+ GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
+ GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
+ GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
+ GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
+ GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
+ GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
+ GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
+ GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
+ GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
+ GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
+ GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
+ GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
+ GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
+
+ /* aclk_vio0 gates */
+ GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
+ GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
+ GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
+ GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
+
+ /* aclk_vio1 gates */
+ GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
+ GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
+ GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
+
+ /* aclk_rga_pre gates */
+ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
+ GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
+
+ /*
+ * Other ungrouped clocks.
+ */
+
+ GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
+ GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
+};
+
+static const char *rk3288_critical_clocks[] __initconst = {
+ "aclk_cpu",
+ "aclk_peri",
+ "hclk_peri",
+ "pclk_pd_pmu",
+};
+
+static int __init rk3288_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ struct clk *clk;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return -ENOMEM;
+ }
+
+ rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+
+ /* xin12m is created by an cru-internal divider */
+ clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0);
+ if (IS_ERR(clk))
+ pr_warn("%s: could not register clock xin12m: %ld\n",
+ __func__, PTR_ERR(clk));
+
+ clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0);
+ if (IS_ERR(clk))
+ pr_warn("%s: could not register clock usb480m: %ld\n",
+ __func__, PTR_ERR(clk));
+
+ clk = clk_fixed_factor("hclk_vcodec_pre",
+ "hclk_vcodec_pre_v", 1, 4, 0);
+ if (IS_ERR(clk))
+ pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
+ __func__, PTR_ERR(clk));
+
+ /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
+ clk = clk_fixed_factor("pclk_wdt", "pclk_pd_alive", 1, 1, 0);
+ if (IS_ERR(clk))
+ pr_warn("%s: could not register clock pclk_wdt: %ld\n",
+ __func__, PTR_ERR(clk));
+ else
+ rockchip_clk_add_lookup(clk, PCLK_WDT);
+
+ rockchip_clk_register_plls(rk3288_pll_clks,
+ ARRAY_SIZE(rk3288_pll_clks),
+ RK3288_GRF_SOC_STATUS1);
+ rockchip_clk_register_branches(rk3288_clk_branches,
+ ARRAY_SIZE(rk3288_clk_branches));
+ rockchip_clk_protect_critical(rk3288_critical_clocks,
+ ARRAY_SIZE(rk3288_critical_clocks));
+
+ rockchip_clk_register_armclk(ARMCLK, "armclk",
+ mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ &rk3288_cpuclk_data, rk3288_cpuclk_rates,
+ ARRAY_SIZE(rk3288_cpuclk_rates));
+ return 0;
+}
+CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
--
1.9.1
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^ permalink raw reply related
* [PATCH v2 7/8] configs: Add RK3288 defconfig
From: Wadim Egorov @ 2016-08-24 12:49 UTC (permalink / raw)
To: barebox
In-Reply-To: <1472042970-35151-1-git-send-email-w.egorov@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/configs/rk3288_defconfig | 104 ++++++++++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 arch/arm/configs/rk3288_defconfig
diff --git a/arch/arm/configs/rk3288_defconfig b/arch/arm/configs/rk3288_defconfig
new file mode 100644
index 0000000..f54f4cc
--- /dev/null
+++ b/arch/arm/configs/rk3288_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_RK3288=y
+CONFIG_MACH_PHYTEC_SOM_RK3288=y
+CONFIG_THUMB2_BAREBOX=y
+CONFIG_ARM_BOARD_APPEND_ATAG=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_PROMPT="barebox> "
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BOOTM_OFTREE_UIMAGE=y
+CONFIG_BOOTM_AIMAGE=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_DEFAULT_COMPRESSION_LZO=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_RESET_SOURCE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_ROCKCHIP_UART_PORT=0
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_HOST=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_ARC_EMAC=y
+CONFIG_SMSC_PHY=y
+CONFIG_I2C_GPIO=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_DW=y
+CONFIG_MCI_DW_PIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_GENERIC_PHY=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_FS_BPKFS=y
+CONFIG_FS_UIMAGEFS=y
+CONFIG_LZO_DECOMPRESS=y
--
1.9.1
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [PATCH v2 8/8] doc: Add RK3288 Documentation
From: Wadim Egorov @ 2016-08-24 12:49 UTC (permalink / raw)
To: barebox
In-Reply-To: <1472042970-35151-1-git-send-email-w.egorov@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
Documentation/boards/rk3288.rst | 57 ++++++++++++++++++++++++++++++
Documentation/boards/rk3288/phytec-som.rst | 24 +++++++++++++
2 files changed, 81 insertions(+)
create mode 100644 Documentation/boards/rk3288.rst
create mode 100644 Documentation/boards/rk3288/phytec-som.rst
diff --git a/Documentation/boards/rk3288.rst b/Documentation/boards/rk3288.rst
new file mode 100644
index 0000000..3acca74
--- /dev/null
+++ b/Documentation/boards/rk3288.rst
@@ -0,0 +1,57 @@
+Rockchip RK3288
+===============
+
+The RK3288 SoC has a two stage boot process. The booting is completed in two
+consecutive stages. The binary for the 1st stage is referred to as the
+Secondary Program Loader (SPL). The binary for the 2nd stage is simply referred to
+as barebox.
+SPL is a non-interactive loader and is only used to boot the 2nd stage loader.
+
+At this moment barebox can only be used as a 2nd stage bootloader.
+Starting barebox requires another bootloader which will do the very basic
+SDRAM initialization for us. We can use the u-boot for that.
+
+Building barebox
+----------------
+
+The RK3288 boards in barebox are covered by the ``rk3288_defconfig``.
+The resulting images will be placed under ``images/``:
+
+::
+ barebox-rk3288-phycore-som.img
+
+
+Starting and updating barebox
+-----------------------------
+
+SD/MMC
+^^^^^^
+
+For the first stage bootloader we will need an u-boot image. A detailed
+description on how to build and flash an RK3288 SPL image can be found in the
+u-boot source ``u-boot/doc/README.rockchip``.
+
+U-boot requires an image with a special header.
+
+ mkimage -A arm -T firmware -C none -O u-boot -a 0x02000000 -e 0 -n "barebox image" -d images/barebox-rk3288-phycore-som.img barebox.img
+
+To write an image that boots from an SD card (assumed to be /dev/sdc):
+
+ sudo dd if=u-boot/u-boot-spl-dtb.bin of=/dev/sdc seek=64 bs=512
+ sudo dd if=barebox.img of=/dev/sdc seek=256 bs=512
+
+This puts the Rockchip header and SPL image first and then places the barebox
+image at block 256 (i.e. 128KB from the start of the SD card). This
+corresponds with this setting in U-Boot:
+
+ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256
+
+RK3288 Boards
+-------------
+
+.. toctree::
+ :glob:
+ :numbered:
+ :maxdepth: 1
+
+ rk3288/*
diff --git a/Documentation/boards/rk3288/phytec-som.rst b/Documentation/boards/rk3288/phytec-som.rst
new file mode 100644
index 0000000..1f3c714
--- /dev/null
+++ b/Documentation/boards/rk3288/phytec-som.rst
@@ -0,0 +1,24 @@
+Phytec RK3288 based SOMs
+========================
+
+The phycore-som-rk3288 is actually not a real board. It represents a RK3288
+based Phytec module and its boards in the barebox.
+You can find out more about the Phytec SOM concept on the website:
+
+ http://phytec.com/products/system-on-modules/
+
+
+Supported modules and boards
+----------------------------
+
+Currently, barebox supports the following SOMs and boards:
+
+ - phyCORE
+
+ - PCM-946
+ - PCM-947
+
+Building phycore-som-rk3288
+---------------------------
+
+The phycore-som-rk3288 boards are covered by the ``rk3288_defconfig``.
--
1.9.1
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^ permalink raw reply related
* [PATCH v2 6/8] ARM: Add phyCORE-RK3288 SOM support
From: Wadim Egorov @ 2016-08-24 12:49 UTC (permalink / raw)
To: barebox
In-Reply-To: <1472042970-35151-1-git-send-email-w.egorov@phytec.de>
The phyCORE-RK3288 aka PCM-059 is a SoM (System on Module)
containing a RK3288 SoC. The module can be connected to different
carrier boards.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/phytec-som-rk3288/Makefile | 3 +
arch/arm/boards/phytec-som-rk3288/board.c | 31 +++++
.../defaultenv-physom-rk3288/boot/emmc | 6 +
.../defaultenv-physom-rk3288/boot/mmc | 6 +
.../defaultenv-physom-rk3288/init/automount | 12 ++
.../defaultenv-physom-rk3288/init/bootsource | 3 +
arch/arm/boards/phytec-som-rk3288/lowlevel.c | 44 ++++++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3288-phycore-som.dts | 148 +++++++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 7 +
images/Makefile.rockchip | 4 +
12 files changed, 266 insertions(+)
create mode 100644 arch/arm/boards/phytec-som-rk3288/Makefile
create mode 100644 arch/arm/boards/phytec-som-rk3288/board.c
create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc
create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc
create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount
create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource
create mode 100644 arch/arm/boards/phytec-som-rk3288/lowlevel.c
create mode 100644 arch/arm/dts/rk3288-phycore-som.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 9241b66..24ce130 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_PM9G45) += pm9g45/
obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/
obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/
obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/
+obj-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += phytec-som-rk3288/
obj-$(CONFIG_MACH_REALQ7) += datamodul-edm-qmx6/
obj-$(CONFIG_MACH_RPI_COMMON) += raspberry-pi/
obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/
diff --git a/arch/arm/boards/phytec-som-rk3288/Makefile b/arch/arm/boards/phytec-som-rk3288/Makefile
new file mode 100644
index 0000000..6f34c9a
--- /dev/null
+++ b/arch/arm/boards/phytec-som-rk3288/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o
+lwl-y += lowlevel.o
+bbenv-y += defaultenv-physom-rk3288
diff --git a/arch/arm/boards/phytec-som-rk3288/board.c b/arch/arm/boards/phytec-som-rk3288/board.c
new file mode 100644
index 0000000..8ea6c6c
--- /dev/null
+++ b/arch/arm/boards/phytec-som-rk3288/board.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * Device initialization for the phyCORE-RK3288 SoM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <envfs.h>
+
+static int physom_devices_init(void)
+{
+ if (!of_machine_is_compatible("phytec,rk3288-phycore-som"))
+ return 0;
+
+ barebox_set_hostname("pcm059");
+ defaultenv_append_directory(defaultenv_physom_rk3288);
+
+ return 0;
+}
+device_initcall(physom_devices_init);
diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc
new file mode 100644
index 0000000..731b07f
--- /dev/null
+++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+global.bootm.image=/mnt/emmc/linuximage
+global.bootm.oftree=/mnt/emmc/oftree
+
+global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rw rootwait"
diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc
new file mode 100644
index 0000000..5b19dba
--- /dev/null
+++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+global.bootm.image=/mnt/sdmmc/linuximage
+global.bootm.oftree=/mnt/sdmmc/oftree
+
+global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rw rootwait"
diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount
new file mode 100644
index 0000000..2f9d78a
--- /dev/null
+++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "Automountpoints"
+ exit
+fi
+
+mkdir -p /mnt/emmc
+automount -d /mnt/emmc 'mshc0.probe=1 && [ -e /dev/mshc0.0 ] && mount /dev/mshc0.0 /mnt/emmc'
+
+mkdir -p /mnt/sdmmc
+automount -d /mnt/sdmmc 'mshc1.probe=1 && [ -e /dev/mshc1.0 ] && mount /dev/mshc1.0 /mnt/sdmmc'
diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource
new file mode 100644
index 0000000..36d34e3
--- /dev/null
+++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+global.boot.default="emmc mmc"
diff --git a/arch/arm/boards/phytec-som-rk3288/lowlevel.c b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
new file mode 100644
index 0000000..7804a55
--- /dev/null
+++ b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/rk3288-regs.h>
+#include <mach/grf_rk3288.h>
+#include <mach/hardware.h>
+#include <debug_ll.h>
+
+extern char __dtb_rk3288_phycore_som_start[];
+
+ENTRY_FUNCTION(start_rk3288_phycore_som, r0, r1, r2)
+{
+ void *fdt;
+ arm_cpu_lowlevel_init();
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+ struct rk3288_grf * const grf = (void *)RK3288_GRF_BASE;
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GPIO4C1_MASK << GPIO4C1_SHIFT |
+ GPIO4C0_MASK << GPIO4C0_SHIFT,
+ GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
+ GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
+ INIT_LL();
+ }
+
+ fdt = __dtb_rk3288_phycore_som_start - get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_1G, fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 813e098..77c9ff3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -54,6 +54,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
+pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
pbl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
diff --git a/arch/arm/dts/rk3288-phycore-som.dts b/arch/arm/dts/rk3288-phycore-som.dts
new file mode 100644
index 0000000..05ddd9c
--- /dev/null
+++ b/arch/arm/dts/rk3288-phycore-som.dts
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include <arm/rk3288.dtsi>
+
+/ {
+ model = "phycore-rk3288";
+ compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+
+ vcc33: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc18: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &emmc, "partname:barebox-environment";
+ status = "disabled";
+ };
+
+ environment-sdmmc {
+ compatible = "barebox,environment";
+ device-path = &sdmmc, "partname:barebox-environment";
+ status = "disabled";
+ };
+ };
+};
+
+&pinctrl {
+ sdmmc {
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&emmc {
+ broken-cd;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+ vmmc-supply = <&vcc33>;
+ vqmmc-supply = <&vcc18>;
+ status = "okay";
+
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ partition@8000 {
+ label = "spl";
+ reg = <0x8000 0x8000>;
+ };
+
+ partition@20000 {
+ label = "barebox";
+ reg = <0x20000 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+ vmmc-supply = <&vcc33>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@8000 {
+ label = "spl";
+ reg = <0x8000 0x8000>;
+ };
+
+ partition@20000 {
+ label = "barebox";
+ reg = <0x20000 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
+ reg-shift = <2>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 71fcbe7..f2fa3c6 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -30,4 +30,11 @@ config MACH_RADXA_ROCK
select MFD_ACT8846
bool "Radxa rock board"
+config MACH_PHYTEC_SOM_RK3288
+ depends on ARCH_RK3288
+ select I2C
+ bool "RK3288 phyCORE SOM"
+ help
+ Say Y here if you are using a RK3288 based Phytecs SOM
+
endmenu
diff --git a/images/Makefile.rockchip b/images/Makefile.rockchip
index 9715b92..3f1ee57 100644
--- a/images/Makefile.rockchip
+++ b/images/Makefile.rockchip
@@ -5,3 +5,7 @@
pblx-$(CONFIG_MACH_RADXA_ROCK) += start_radxa_rock
FILE_barebox-radxa-rock.img = start_radxa_rock.pblx
image-$(CONFIG_MACH_RADXA_ROCK) += barebox-radxa-rock.img
+
+pblx-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += start_rk3288_phycore_som
+FILE_barebox-rk3288-phycore-som.img = start_rk3288_phycore_som.pblx
+image-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += barebox-rk3288-phycore-som.img
--
1.9.1
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^ permalink raw reply related
* Re: Fwd: Shouldn't boot_board be called from boot instead of init?
From: Guillermo Rodriguez Garcia @ 2016-08-24 14:42 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20160823081319.GD20657@pengutronix.de>
Hi Sascha,
2016-08-23 10:13 GMT+02:00 Sascha Hauer <s.hauer@pengutronix.de>:
> On Mon, Aug 22, 2016 at 11:12:55AM +0200, Guillermo Rodriguez Garcia wrote:
>> >> > However, I would be glad to get rid of defaultenv-1 rather sooner than
>> >> > later.
>> >>
>> >> Uhm. I actually like defaultenv-1 better than defaultenv-2. Why not
>> >> keep both? Everyone can then make their choice :)
>> >
>> > That's interesting. What do you like better about defaultenv-1? This
>> > information could help me to improve defaultenv-2.
>>
>> I guess it is just a matter of personal preference but I find
>> defaultenv-1 easier to understand and easier to manage. With
>> defaultenv-1 we basically have just one configuration file to edit
>> (/env/config) and optionally init_board and/or boot_board (which are
>> not needed in a majority of the cases). So everything you need to
>> know/edit/tweak is in /env/config.
>>
>> With defaultenv-2 the "board configuration" is scattered through a
>> number of tiny files, some of which contain just a single value (see
>> for example nv/autoboot_timeout or nv/user). I find this more
>> difficult to manage -- you need to edit a lot of tiny files instead of
>> just one. Also I feel that the flow of control is less obvious for the
>> same reason.
>>
>> I'd say defaultenv-1 feels more "imperative" and defaultenv-2 feels
>> more "declarative", and I prefer the former. But I am fully aware that
>> this is just a matter of personal preference :)
>
> I understand your concerns but do not share them all. Maybe we can find
> a way to either make defaultenv-2 more acceptable for you or to make
> defaultenv-1 more appealing to me?
>
> About the number of small files that only contain a single value:
> defaultenv-1 was the opposite and that was a problem. Whenever a board
> wanted to adjust a single value, say the autoboot timeout, it had to
> duplicate a big file and very soon we had many nearly identical copies
> of that file and nobody knew what the actual change was.
Not sure what you mean with duplicating a big file. With defaultenv-1 most
of the time the only single file you need to edit is /env/config, which is quite
small, and most of it should be board specific anyway. I find this (the fact
that all I need to edit/tweak is in that single file) quite convenient.
> With NV
> variables this has become better. I never felt the need though to dig
> through the individual /env/nv files, here the 'nv' and 'global'
> commands or the 'magicvar' command to much better jobs. Normally you
> only have to hand edit /env/nv files when you want to change the default
> of a variable for a given board.
>
> Another thing that made another approach than with defaultenv-1
> necessary was the variables that contain "net", "disk", "nor", "nand".
> This did not scale and was not extensible because you could not pass
> some arbitrary file and use it as kernel.
I can understand that one. But on the other hand not every target needs
that flexibility. That's why I said that I don't see the need to drop
defaultenv-1.
Isn't it better to leave both defaultenv-1 and defaultenv-2 alive and
let everyone
decide which one suits them best?
My impression when I look at defaultenv-2 is as described above: OK,
more flexibility (which I currently don't need), but also more complexity,
configuration scattered over more files, more management overhead.
Plus, I'm happy with defaultenv-1, so why change?
>
> I wonder if defaultenv-1 is not customizable enough and on the other
> hand your board does only boot from very special locations, do you need
> a generic default environment at all or are you better off using your
> own special environment?
In my case, I am currently using barebox on 3 boards. All of them support
multiple boot sources (NAND, NOR, MMC) plus NFS. For all of them I only
needed to edit /env/config; the other files in the default environment
(init, update, boot) all work fine. So (for me) defaultenv-1 was customizable
enough, and I did indeed benefit from having a generic default environment
instead of a custom one written from scratch.
>
> Finally, could this be a documentation issue? Could you have another
> look at defaultenv-2 and see what is not clear or what needs further
> convenience to be better usable?
I think the documentation is fine as a reference. Perhaps a tutorial showing
how to migrate from defaultenv-1 to defaultenv-2 could help "convert" people
to defaultenv-2 by holding their hand and taking them from what they know
(defaultenv-1) to the "new stuff".
But even then I still wonder -- why not let both approaches coexist?
Best,
Guillermo Rodriguez Garcia
guille.rodriguez@gmail.com
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^ permalink raw reply
* Re: [PATCH] ARM: vector_table: Fix creation of second level page table
From: Andrey Smirnov @ 2016-08-24 16:07 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List, Peter Kardos
In-Reply-To: <1472041390-19259-1-git-send-email-s.hauer@pengutronix.de>
On Wed, Aug 24, 2016 at 5:23 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> The second level page tables can only start at a 1MiB section boundary,
> so instead of calling arm_create_pte() with the high vector address
> (which is 0xffff0000, not 1MiB aligned) we have to call it with
> 0xfff00000 to correctly create a second level page table. The vectors
> themselves worked as expected with the old value, but the memory around
> it did not do a 1:1 mapping anymore. This breaks SoCs which have
> peripherals in that area, for example Atmel SoCs like the AT91RM9200.
>
Would you mind re-wording it as something to the effect of: "...
mapping anymore, breaking SoCs which also have peripherals in that
area..."? The original sentence structure, to me, reads as if this
patch/commit introduces a change that breaks Atmel SoCs.
> Fixes: f6b77fe9: ARM: Rework vector table setup
>
> Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/cpu/mmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index a31bce4..2b70866 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
> vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
> pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
> vectors, adr);
> - exc = arm_create_pte(adr);
> + exc = arm_create_pte(adr & ~(SZ_1M - 1));
ALIGN_DOWN(adr, SZ_1M) ?
Thanks,
Andrey Smirnov
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^ permalink raw reply
* [MPR] August 24th 2016 "Pls Privada"
From: MPR From MAR @ 2016-08-24 20:51 UTC (permalink / raw)
To: barebox
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^ permalink raw reply
* Re: [PATCH 1/3] video: switch to media bus formats
From: Sascha Hauer @ 2016-08-25 6:28 UTC (permalink / raw)
To: Philipp Zabel; +Cc: barebox
In-Reply-To: <1472035219-23917-1-git-send-email-p.zabel@pengutronix.de>
On Wed, Aug 24, 2016 at 12:40:17PM +0200, Philipp Zabel wrote:
> V4L2 pixel formats are supposed to describe video frames in memory. To
> describe the pixel format on the hardware bus between display interface
> and encoders, use media bus formats, which are more expressive.
>
> This allows to get rid of the custom GBR24 and LVDS666 fourccs.
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Applied, thanks
Sascha
> ---
> drivers/video/imx-ipu-v3/imx-hdmi.c | 3 +-
> drivers/video/imx-ipu-v3/imx-ipu-v3.h | 4 +-
> drivers/video/imx-ipu-v3/imx-ldb.c | 7 +-
> drivers/video/imx-ipu-v3/ipu-dc.c | 19 +++--
> drivers/video/imx-ipu-v3/ipu-prv.h | 2 -
> drivers/video/imx-ipu-v3/ipufb.c | 21 +++--
> include/video/fourcc.h | 151 ----------------------------------
> include/video/media-bus-format.h | 137 ++++++++++++++++++++++++++++++
> 8 files changed, 165 insertions(+), 179 deletions(-)
> create mode 100644 include/video/media-bus-format.h
>
> diff --git a/drivers/video/imx-ipu-v3/imx-hdmi.c b/drivers/video/imx-ipu-v3/imx-hdmi.c
> index 8b251a5..17b6e4c 100644
> --- a/drivers/video/imx-ipu-v3/imx-hdmi.c
> +++ b/drivers/video/imx-ipu-v3/imx-hdmi.c
> @@ -22,6 +22,7 @@
> #include <asm-generic/div64.h>
> #include <linux/clk.h>
> #include <i2c/i2c.h>
> +#include <video/media-bus-format.h>
> #include <video/vpl.h>
> #include <mach/imx6-regs.h>
> #include <mach/imx53-regs.h>
> @@ -1261,7 +1262,7 @@ static int dw_hdmi_ioctl(struct vpl *vpl, unsigned int port,
> mode = data;
>
> mode->di_clkflags = IPU_DI_CLKMODE_EXT | IPU_DI_CLKMODE_SYNC;
> - mode->interface_pix_fmt = V4L2_PIX_FMT_RGB24;
> + mode->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
>
> return 0;
> }
> diff --git a/drivers/video/imx-ipu-v3/imx-ipu-v3.h b/drivers/video/imx-ipu-v3/imx-ipu-v3.h
> index fbfec22..cdfff69 100644
> --- a/drivers/video/imx-ipu-v3/imx-ipu-v3.h
> +++ b/drivers/video/imx-ipu-v3/imx-ipu-v3.h
> @@ -116,7 +116,7 @@ struct ipu_di;
> struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
> void ipu_dc_put(struct ipu_dc *dc);
> int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
> - u32 pixel_fmt, u32 width);
> + u32 bus_format, u32 width);
> void ipu_dc_enable_channel(struct ipu_dc *dc);
> void ipu_dc_disable_channel(struct ipu_dc *dc);
>
> @@ -323,7 +323,7 @@ struct ipu_client_platformdata {
>
> struct ipu_di_mode {
> u32 di_clkflags;
> - u32 interface_pix_fmt;
> + u32 bus_format;
> };
>
> #define IMX_IPU_VPL_DI_MODE 0x12660001
> diff --git a/drivers/video/imx-ipu-v3/imx-ldb.c b/drivers/video/imx-ipu-v3/imx-ldb.c
> index 17ae894..14a86a4 100644
> --- a/drivers/video/imx-ipu-v3/imx-ldb.c
> +++ b/drivers/video/imx-ipu-v3/imx-ldb.c
> @@ -26,6 +26,7 @@
> #include <malloc.h>
> #include <errno.h>
> #include <init.h>
> +#include <video/media-bus-format.h>
> #include <video/vpl.h>
> #include <mfd/imx6q-iomuxc-gpr.h>
> #include <linux/clk.h>
> @@ -75,7 +76,7 @@ struct imx_ldb_data {
>
> struct imx_ldb {
> struct device_d *dev;
> - u32 interface_pix_fmt;
> + u32 bus_format;
> int mode_valid;
> struct imx_ldb_channel channel[2];
> u32 ldb_ctrl;
> @@ -273,8 +274,8 @@ static int imx_ldb_ioctl(struct vpl *vpl, unsigned int port,
> mode = data;
>
> mode->di_clkflags = IPU_DI_CLKMODE_EXT | IPU_DI_CLKMODE_SYNC;
> - mode->interface_pix_fmt = (imx_ldb_ch->datawidth == 24) ?
> - V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
> + mode->bus_format = (imx_ldb_ch->datawidth == 24) ?
> + MEDIA_BUS_FMT_RGB888_1X24 : MEDIA_BUS_FMT_RGB666_1X18;
>
> return 0;
> case VPL_GET_VIDEOMODES:
> diff --git a/drivers/video/imx-ipu-v3/ipu-dc.c b/drivers/video/imx-ipu-v3/ipu-dc.c
> index 2deb2ae..7b343e8 100644
> --- a/drivers/video/imx-ipu-v3/ipu-dc.c
> +++ b/drivers/video/imx-ipu-v3/ipu-dc.c
> @@ -17,6 +17,7 @@
> #include <linux/err.h>
> #include <linux/clk.h>
> #include <malloc.h>
> +#include <video/media-bus-format.h>
>
> #include "imx-ipu-v3.h"
> #include "ipu-prv.h"
> @@ -138,18 +139,18 @@ static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
> ipuwritel("dc", reg2, priv->dc_tmpl_reg + word * 8 + 4);
> }
>
> -static int ipu_pixfmt_to_map(u32 fmt)
> +static int ipu_bus_format_to_map(u32 bus_format)
> {
> - switch (fmt) {
> - case V4L2_PIX_FMT_RGB24:
> + switch (bus_format) {
> + case MEDIA_BUS_FMT_RGB888_1X24:
> return IPU_DC_MAP_RGB24;
> - case V4L2_PIX_FMT_RGB565:
> + case MEDIA_BUS_FMT_RGB565_1X16:
> return IPU_DC_MAP_RGB565;
> - case IPU_PIX_FMT_GBR24:
> + case MEDIA_BUS_FMT_GBR888_1X24:
> return IPU_DC_MAP_GBR24;
> - case V4L2_PIX_FMT_BGR666:
> + case MEDIA_BUS_FMT_RGB666_1X18:
> return IPU_DC_MAP_BGR666;
> - case V4L2_PIX_FMT_BGR24:
> + case MEDIA_BUS_FMT_BGR888_1X24:
> return IPU_DC_MAP_BGR24;
> default:
> return -EINVAL;
> @@ -157,7 +158,7 @@ static int ipu_pixfmt_to_map(u32 fmt)
> }
>
> int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
> - u32 pixel_fmt, u32 width)
> + u32 bus_format, u32 width)
> {
> struct ipu_dc_priv *priv = dc->priv;
> u32 reg = 0;
> @@ -165,7 +166,7 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
>
> dc->di = ipu_di_get_num(di);
>
> - map = ipu_pixfmt_to_map(pixel_fmt);
> + map = ipu_bus_format_to_map(bus_format);
> if (map < 0) {
> dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
> return map;
> diff --git a/drivers/video/imx-ipu-v3/ipu-prv.h b/drivers/video/imx-ipu-v3/ipu-prv.h
> index 44d7802..4d1c069 100644
> --- a/drivers/video/imx-ipu-v3/ipu-prv.h
> +++ b/drivers/video/imx-ipu-v3/ipu-prv.h
> @@ -19,8 +19,6 @@ struct ipu_soc;
>
> #include "imx-ipu-v3.h"
>
> -#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
> -
> #define IPUV3_CHANNEL_CSI0 0
> #define IPUV3_CHANNEL_CSI1 1
> #define IPUV3_CHANNEL_CSI2 2
> diff --git a/drivers/video/imx-ipu-v3/ipufb.c b/drivers/video/imx-ipu-v3/ipufb.c
> index 67fec11..cfafa22 100644
> --- a/drivers/video/imx-ipu-v3/ipufb.c
> +++ b/drivers/video/imx-ipu-v3/ipufb.c
> @@ -23,6 +23,7 @@
> #include <linux/clk.h>
> #include <linux/err.h>
> #include <asm-generic/div64.h>
> +#include <video/media-bus-format.h>
>
> #include "imx-ipu-v3.h"
> #include "ipuv3-plane.h"
> @@ -56,7 +57,7 @@ struct ipufb_info {
> void (*enable)(int enable);
>
> unsigned int di_clkflags;
> - u32 interface_pix_fmt;
> + u32 bus_format;
> struct ipu_dc *dc;
> struct ipu_di *di;
>
> @@ -108,7 +109,7 @@ int ipu_crtc_mode_set(struct ipufb_info *fbi,
> int ret;
> struct ipu_di_signal_cfg sig_cfg = {};
> struct ipu_di_mode di_mode = {};
> - u32 interface_pix_fmt;
> + u32 bus_format;
>
> dev_info(fbi->dev, "%s: mode->xres: %d\n", __func__,
> mode->xres);
> @@ -116,8 +117,7 @@ int ipu_crtc_mode_set(struct ipufb_info *fbi,
> mode->yres);
>
> vpl_ioctl(&fbi->vpl, 2 + fbi->dino, IMX_IPU_VPL_DI_MODE, &di_mode);
> - interface_pix_fmt = di_mode.interface_pix_fmt ?
> - di_mode.interface_pix_fmt : fbi->interface_pix_fmt;
> + bus_format = di_mode.bus_format ?: fbi->bus_format;
>
> if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
> sig_cfg.Hsync_pol = 1;
> @@ -148,8 +148,8 @@ int ipu_crtc_mode_set(struct ipufb_info *fbi,
> sig_cfg.hsync_pin = 2;
> sig_cfg.vsync_pin = 3;
>
> - ret = ipu_dc_init_sync(fbi->dc, fbi->di, sig_cfg.interlaced,
> - interface_pix_fmt, mode->xres);
> + ret = ipu_dc_init_sync(fbi->dc, fbi->di, sig_cfg.interlaced, bus_format,
> + mode->xres);
> if (ret) {
> dev_err(fbi->dev,
> "initializing display controller failed with %d\n",
> @@ -318,14 +318,13 @@ static int ipufb_probe(struct device_d *dev)
> ret = of_property_read_string(node, "interface-pix-fmt", &fmt);
> if (!ret) {
> if (!strcmp(fmt, "rgb24"))
> - fbi->interface_pix_fmt = V4L2_PIX_FMT_RGB24;
> + fbi->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
> else if (!strcmp(fmt, "rgb565"))
> - fbi->interface_pix_fmt = V4L2_PIX_FMT_RGB565;
> + fbi->bus_format = MEDIA_BUS_FMT_RGB565_1X16;
> else if (!strcmp(fmt, "bgr666"))
> - fbi->interface_pix_fmt = V4L2_PIX_FMT_BGR666;
> + fbi->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
> else if (!strcmp(fmt, "lvds666"))
> - fbi->interface_pix_fmt =
> - v4l2_fourcc('L', 'V', 'D', '6');
> + fbi->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
> }
>
> ret = vpl_ioctl(&fbi->vpl, 2 + fbi->dino, VPL_GET_VIDEOMODES, &info->modes);
> diff --git a/include/video/fourcc.h b/include/video/fourcc.h
> index 322142c..211aabb 100644
> --- a/include/video/fourcc.h
> +++ b/include/video/fourcc.h
> @@ -1,157 +1,6 @@
> #ifndef __VIDEO_FOURCC_H
> #define __VIDEO_FOURCC_H
>
> -/* Four-character-code (FOURCC) */
> -#define v4l2_fourcc(a, b, c, d)\
> - ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
> -
> -/* Pixel format FOURCC depth Description */
> -
> -/* RGB formats */
> -#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */
> -#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */
> -#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */
> -#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */
> -#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */
> -#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */
> -#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */
> -#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */
> -#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */
> -#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */
> -#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */
> -
> -/* Grey formats */
> -#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */
> -#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */
> -#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */
> -#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */
> -#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */
> -#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */
> -
> -/* Grey bit-packed formats */
> -#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */
> -
> -/* Palette formats */
> -#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */
> -
> -/* Chrominance formats */
> -#define V4L2_PIX_FMT_UV8 v4l2_fourcc('U', 'V', '8', ' ') /* 8 UV 4:4 */
> -
> -/* Luminance+Chrominance formats */
> -#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */
> -#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */
> -#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */
> -#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */
> -#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */
> -#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */
> -#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */
> -#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */
> -#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16 YVU411 planar */
> -#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */
> -#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */
> -#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */
> -#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */
> -#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */
> -#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */
> -#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */
> -#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */
> -#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
> -#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */
> -
> -/* two planes -- one Y, one Cr + Cb interleaved */
> -#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
> -#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
> -#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
> -#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
> -#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
> -#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
> -
> -/* two non contiguous planes - one Y, one Cr + Cb interleaved */
> -#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
> -#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */
> -#define V4L2_PIX_FMT_NV16M v4l2_fourcc('N', 'M', '1', '6') /* 16 Y/CbCr 4:2:2 */
> -#define V4L2_PIX_FMT_NV61M v4l2_fourcc('N', 'M', '6', '1') /* 16 Y/CrCb 4:2:2 */
> -#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 macroblocks */
> -#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 macroblocks */
> -
> -/* three non contiguous planes - Y, Cb, Cr */
> -#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12 YUV420 planar */
> -#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') /* 12 YVU420 planar */
> -
> -/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */
> -#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */
> -#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */
> -#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */
> -#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') /* 8 RGRG.. GBGB.. */
> -#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') /* 10 BGBG.. GRGR.. */
> -#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') /* 10 GBGB.. RGRG.. */
> -#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') /* 10 GRGR.. BGBG.. */
> -#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') /* 10 RGRG.. GBGB.. */
> -#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') /* 12 BGBG.. GRGR.. */
> -#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') /* 12 GBGB.. RGRG.. */
> -#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */
> -#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */
> - /* 10bit raw bayer a-law compressed to 8 bits */
> -#define V4L2_PIX_FMT_SBGGR10ALAW8 v4l2_fourcc('a', 'B', 'A', '8')
> -#define V4L2_PIX_FMT_SGBRG10ALAW8 v4l2_fourcc('a', 'G', 'A', '8')
> -#define V4L2_PIX_FMT_SGRBG10ALAW8 v4l2_fourcc('a', 'g', 'A', '8')
> -#define V4L2_PIX_FMT_SRGGB10ALAW8 v4l2_fourcc('a', 'R', 'A', '8')
> - /* 10bit raw bayer DPCM compressed to 8 bits */
> -#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8')
> -#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8')
> -#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0')
> -#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8')
> - /*
> - * 10bit raw bayer, expanded to 16 bits
> - * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb...
> - */
> -#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */
> -
> -/* compressed formats */
> -#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */
> -#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */
> -#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */
> -#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */
> -#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */
> -#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */
> -#define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */
> -#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */
> -#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */
> -#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */
> -#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') /* MPEG-4 part 2 ES */
> -#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') /* Xvid */
> -#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */
> -#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */
> -#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */
> -
> -/* Vendor-specific formats */
> -#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */
> -#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */
> -#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */
> -#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') /* SN9C20x YUV 4:2:0 */
> -#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */
> -#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */
> -#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */
> -#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */
> -#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */
> -#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */
> -#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */
> -#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */
> -#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') /* compressed BGGR bayer */
> -#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') /* compressed RGGB bayer */
> -#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') /* compressed GBRG bayer */
> -#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') /* compressed RGGB bayer */
> -#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */
> -#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') /* ov511 JPEG */
> -#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') /* ov518 JPEG */
> -#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') /* stv0680 bayer */
> -#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') /* tm5600/tm60x0 */
> -#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') /* one line of Y then 1 line of VYUY */
> -#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') /* YUV420 planar in blocks of 256 pixels */
> -#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') /* JPEG-Lite */
> -#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') /* se401 janggu compressed rgb */
> -#define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') /* S5C73M3 interleaved UYVY/JPEG */
> -
> #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
> ((__u32)(c) << 16) | ((__u32)(d) << 24))
>
> diff --git a/include/video/media-bus-format.h b/include/video/media-bus-format.h
> new file mode 100644
> index 0000000..190d491
> --- /dev/null
> +++ b/include/video/media-bus-format.h
> @@ -0,0 +1,137 @@
> +/*
> + * Media Bus API header
> + *
> + * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __LINUX_MEDIA_BUS_FORMAT_H
> +#define __LINUX_MEDIA_BUS_FORMAT_H
> +
> +/*
> + * These bus formats uniquely identify data formats on the data bus. Format 0
> + * is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where
> + * the data format is fixed. Additionally, "2X8" means that one pixel is
> + * transferred in two 8-bit samples, "BE" or "LE" specify in which order those
> + * samples are transferred over the bus: "LE" means that the least significant
> + * bits are transferred first, "BE" means that the most significant bits are
> + * transferred first, and "PADHI" and "PADLO" define which bits - low or high,
> + * in the incomplete high byte, are filled with padding bits.
> + *
> + * The bus formats are grouped by type, bus_width, bits per component, samples
> + * per pixel and order of subsamples. Numerical values are sorted using generic
> + * numerical sort order (8 thus comes before 10).
> + *
> + * As their value can't change when a new bus format is inserted in the
> + * enumeration, the bus formats are explicitly given a numerical value. The next
> + * free values for each category are listed below, update them when inserting
> + * new pixel codes.
> + */
> +
> +#define MEDIA_BUS_FMT_FIXED 0x0001
> +
> +/* RGB - next is 0x1018 */
> +#define MEDIA_BUS_FMT_RGB444_1X12 0x1016
> +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
> +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
> +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
> +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
> +#define MEDIA_BUS_FMT_RGB565_1X16 0x1017
> +#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
> +#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006
> +#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007
> +#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008
> +#define MEDIA_BUS_FMT_RGB666_1X18 0x1009
> +#define MEDIA_BUS_FMT_RBG888_1X24 0x100e
> +#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015
> +#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010
> +#define MEDIA_BUS_FMT_BGR888_1X24 0x1013
> +#define MEDIA_BUS_FMT_GBR888_1X24 0x1014
> +#define MEDIA_BUS_FMT_RGB888_1X24 0x100a
> +#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b
> +#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c
> +#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
> +#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
> +#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
> +#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
> +
> +/* YUV (including grey) - next is 0x2026 */
> +#define MEDIA_BUS_FMT_Y8_1X8 0x2001
> +#define MEDIA_BUS_FMT_UV8_1X8 0x2015
> +#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002
> +#define MEDIA_BUS_FMT_VYUY8_1_5X8 0x2003
> +#define MEDIA_BUS_FMT_YUYV8_1_5X8 0x2004
> +#define MEDIA_BUS_FMT_YVYU8_1_5X8 0x2005
> +#define MEDIA_BUS_FMT_UYVY8_2X8 0x2006
> +#define MEDIA_BUS_FMT_VYUY8_2X8 0x2007
> +#define MEDIA_BUS_FMT_YUYV8_2X8 0x2008
> +#define MEDIA_BUS_FMT_YVYU8_2X8 0x2009
> +#define MEDIA_BUS_FMT_Y10_1X10 0x200a
> +#define MEDIA_BUS_FMT_UYVY10_2X10 0x2018
> +#define MEDIA_BUS_FMT_VYUY10_2X10 0x2019
> +#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b
> +#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c
> +#define MEDIA_BUS_FMT_Y12_1X12 0x2013
> +#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c
> +#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d
> +#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e
> +#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f
> +#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f
> +#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010
> +#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011
> +#define MEDIA_BUS_FMT_YVYU8_1X16 0x2012
> +#define MEDIA_BUS_FMT_YDYUYDYV8_1X16 0x2014
> +#define MEDIA_BUS_FMT_UYVY10_1X20 0x201a
> +#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b
> +#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d
> +#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e
> +#define MEDIA_BUS_FMT_VUY8_1X24 0x2024
> +#define MEDIA_BUS_FMT_YUV8_1X24 0x2025
> +#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020
> +#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021
> +#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022
> +#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023
> +#define MEDIA_BUS_FMT_YUV10_1X30 0x2016
> +#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017
> +
> +/* Bayer - next is 0x3019 */
> +#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001
> +#define MEDIA_BUS_FMT_SGBRG8_1X8 0x3013
> +#define MEDIA_BUS_FMT_SGRBG8_1X8 0x3002
> +#define MEDIA_BUS_FMT_SRGGB8_1X8 0x3014
> +#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8 0x3015
> +#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8 0x3016
> +#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8 0x3017
> +#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8 0x3018
> +#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 0x300b
> +#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 0x300c
> +#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 0x3009
> +#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 0x300d
> +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE 0x3003
> +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE 0x3004
> +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE 0x3005
> +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE 0x3006
> +#define MEDIA_BUS_FMT_SBGGR10_1X10 0x3007
> +#define MEDIA_BUS_FMT_SGBRG10_1X10 0x300e
> +#define MEDIA_BUS_FMT_SGRBG10_1X10 0x300a
> +#define MEDIA_BUS_FMT_SRGGB10_1X10 0x300f
> +#define MEDIA_BUS_FMT_SBGGR12_1X12 0x3008
> +#define MEDIA_BUS_FMT_SGBRG12_1X12 0x3010
> +#define MEDIA_BUS_FMT_SGRBG12_1X12 0x3011
> +#define MEDIA_BUS_FMT_SRGGB12_1X12 0x3012
> +
> +/* JPEG compressed formats - next is 0x4002 */
> +#define MEDIA_BUS_FMT_JPEG_1X8 0x4001
> +
> +/* Vendor specific formats - next is 0x5002 */
> +
> +/* S5C73M3 sensor specific interleaved UYVY and JPEG */
> +#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8 0x5001
> +
> +/* HSV - next is 0x6002 */
> +#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001
> +
> +#endif /* __LINUX_MEDIA_BUS_FORMAT_H */
> --
> 2.8.1
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* [PATCH v2] ARM: vector_table: Fix creation of second level page table
From: Sascha Hauer @ 2016-08-25 6:36 UTC (permalink / raw)
To: Barebox List
The second level page tables can only start at a 1MiB section boundary,
so instead of calling arm_create_pte() with the high vector address
(which is 0xffff0000, not 1MiB aligned) we have to call it with
0xfff00000 to correctly create a second level page table.
The old values broke SoCs which have peripherals in the upper 1MiB
area, like for example the Atmel AT91RM9200. On these Socs we correctly
created the vector page, but the pages around it did not have a 1:1
mapping anymore which led to unreachable peripherals.
Fixes: f6b77fe9: ARM: Rework vector table setup
Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Changes since v1:
- Use ALIGN_DOWN instead of open coded alignment
- more clear commit message
arch/arm/cpu/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index a31bce4..459abe5 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
vectors, adr);
- exc = arm_create_pte(adr);
+ exc = arm_create_pte(ALIGN_DOWN(adr, SZ_1M));
idx = (adr & (SZ_1M - 1)) >> PAGE_SHIFT;
exc[idx] = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached;
}
--
2.8.1
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^ permalink raw reply related
* Re: [PATCH] ARM: vector_table: Fix creation of second level page table
From: Sascha Hauer @ 2016-08-25 6:37 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Barebox List, Peter Kardos
In-Reply-To: <CAHQ1cqFGc8r+kGrKinM3_y+3GPAz=-=nfpRyUiwSSvQSvVXuZA@mail.gmail.com>
On Wed, Aug 24, 2016 at 09:07:22AM -0700, Andrey Smirnov wrote:
> On Wed, Aug 24, 2016 at 5:23 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > The second level page tables can only start at a 1MiB section boundary,
> > so instead of calling arm_create_pte() with the high vector address
> > (which is 0xffff0000, not 1MiB aligned) we have to call it with
> > 0xfff00000 to correctly create a second level page table. The vectors
> > themselves worked as expected with the old value, but the memory around
> > it did not do a 1:1 mapping anymore. This breaks SoCs which have
> > peripherals in that area, for example Atmel SoCs like the AT91RM9200.
> >
>
> Would you mind re-wording it as something to the effect of: "...
> mapping anymore, breaking SoCs which also have peripherals in that
> area..."? The original sentence structure, to me, reads as if this
> patch/commit introduces a change that breaks Atmel SoCs.
Sure.
>
> > Fixes: f6b77fe9: ARM: Rework vector table setup
> >
> > Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/cpu/mmu.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> > index a31bce4..2b70866 100644
> > --- a/arch/arm/cpu/mmu.c
> > +++ b/arch/arm/cpu/mmu.c
> > @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
> > vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
> > pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
> > vectors, adr);
> > - exc = arm_create_pte(adr);
> > + exc = arm_create_pte(adr & ~(SZ_1M - 1));
>
> ALIGN_DOWN(adr, SZ_1M) ?
Yes, that's better. I just sent an updated version.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply
* Re: [PATCH] ARM: vector_table: Fix creation of second level page table
From: Peter Kardos @ 2016-08-25 20:50 UTC (permalink / raw)
To: Sascha Hauer, Barebox List
In-Reply-To: <1472041390-19259-1-git-send-email-s.hauer@pengutronix.de>
Tested with my AT91RM9200 system, v2016.08 + patch; The system
starts/boots as expected.
If no one objects, we can consider this issue closed/fixed.
Peter
On 8/24/2016 2:23 PM, Sascha Hauer wrote:
> The second level page tables can only start at a 1MiB section boundary,
> so instead of calling arm_create_pte() with the high vector address
> (which is 0xffff0000, not 1MiB aligned) we have to call it with
> 0xfff00000 to correctly create a second level page table. The vectors
> themselves worked as expected with the old value, but the memory around
> it did not do a 1:1 mapping anymore. This breaks SoCs which have
> peripherals in that area, for example Atmel SoCs like the AT91RM9200.
>
> Fixes: f6b77fe9: ARM: Rework vector table setup
>
> Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/cpu/mmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index a31bce4..2b70866 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
> vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
> pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
> vectors, adr);
> - exc = arm_create_pte(adr);
> + exc = arm_create_pte(adr & ~(SZ_1M - 1));
> idx = (adr & (SZ_1M - 1)) >> PAGE_SHIFT;
> exc[idx] = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached;
> }
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^ permalink raw reply
* Re: AT91RM9200 hang in atmel_serial_putc
From: Peter Kardos @ 2016-08-25 20:53 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20160824122441.GH20657@pengutronix.de>
Hi Sascha,
Can confirm, with v2016.08 + patch the system boots and seems to work as
expected.
Thanks for your help with this issue.
Cheers, Peter
On 8/24/2016 2:24 PM, Sascha Hauer wrote:
> Hi Peter,
>
> On Mon, Aug 22, 2016 at 10:39:24PM +0200, Peter Kardos wrote:
>> Hi Sascha,
>>
>> I've tested your workaround and it seems to work; the board starts and
>> attempts
>> to boot.
> I just sent a proper solution for that problem, you're on Cc. I'm
> confident that this solves your problem. Could you give this a test
> please?
>
> Sascha
>
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^ permalink raw reply
* Re: [PATCH v2] ARM: vector_table: Fix creation of second level page table
From: Peter Kardos @ 2016-08-25 21:32 UTC (permalink / raw)
To: barebox
In-Reply-To: <1472106992-30755-1-git-send-email-s.hauer@pengutronix.de>
Tested this one as well with my AT91RM9200 system, v2016.08 + patch;
The system starts/boots as expected.
If no one objects, we can consider this issue closed/fixed.
Peter
On 8/25/2016 8:36 AM, Sascha Hauer wrote:
> The second level page tables can only start at a 1MiB section boundary,
> so instead of calling arm_create_pte() with the high vector address
> (which is 0xffff0000, not 1MiB aligned) we have to call it with
> 0xfff00000 to correctly create a second level page table.
> The old values broke SoCs which have peripherals in the upper 1MiB
> area, like for example the Atmel AT91RM9200. On these Socs we correctly
> created the vector page, but the pages around it did not have a 1:1
> mapping anymore which led to unreachable peripherals.
>
> Fixes: f6b77fe9: ARM: Rework vector table setup
>
> Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>
> Changes since v1:
> - Use ALIGN_DOWN instead of open coded alignment
> - more clear commit message
>
> arch/arm/cpu/mmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index a31bce4..459abe5 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
> vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
> pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
> vectors, adr);
> - exc = arm_create_pte(adr);
> + exc = arm_create_pte(ALIGN_DOWN(adr, SZ_1M));
> idx = (adr & (SZ_1M - 1)) >> PAGE_SHIFT;
> exc[idx] = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached;
> }
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^ permalink raw reply
* [PATCH 1/2] defaultenv-2: remove ps1 duplicates
From: Sascha Hauer @ 2016-08-26 5:36 UTC (permalink / raw)
To: Barebox List
Some boards duplicate the PS1 initialization to add a '#' at the end
of the prompt. It's not worth duplicating this for this purpose. Remove
them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/at91sam9m10ihd/env/init/ps1 | 9 ---------
arch/arm/boards/highbank/env/init/ps1 | 9 ---------
arch/arm/boards/raspberry-pi/env/init/ps1 | 7 -------
arch/arm/boards/versatile/env/init/ps1 | 7 -------
4 files changed, 32 deletions(-)
delete mode 100644 arch/arm/boards/at91sam9m10ihd/env/init/ps1
delete mode 100644 arch/arm/boards/highbank/env/init/ps1
delete mode 100644 arch/arm/boards/raspberry-pi/env/init/ps1
delete mode 100644 arch/arm/boards/versatile/env/init/ps1
diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/ps1 b/arch/arm/boards/at91sam9m10ihd/env/init/ps1
deleted file mode 100644
index a94acc1..0000000
--- a/arch/arm/boards/at91sam9m10ihd/env/init/ps1
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/sh
-
-/env/config
-
-if [ ${global.allow_color} = "true" ]; then
- export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# "
-else
- export PS1="barebox@\h:\w\n# "
-fi
diff --git a/arch/arm/boards/highbank/env/init/ps1 b/arch/arm/boards/highbank/env/init/ps1
deleted file mode 100644
index a94acc1..0000000
--- a/arch/arm/boards/highbank/env/init/ps1
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/sh
-
-/env/config
-
-if [ ${global.allow_color} = "true" ]; then
- export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# "
-else
- export PS1="barebox@\h:\w\n# "
-fi
diff --git a/arch/arm/boards/raspberry-pi/env/init/ps1 b/arch/arm/boards/raspberry-pi/env/init/ps1
deleted file mode 100644
index f894846..0000000
--- a/arch/arm/boards/raspberry-pi/env/init/ps1
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-
-if [ ${global.allow_color} = "true" ]; then
- export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# "
-else
- export PS1="barebox@\h:\w\n# "
-fi
diff --git a/arch/arm/boards/versatile/env/init/ps1 b/arch/arm/boards/versatile/env/init/ps1
deleted file mode 100644
index a1d0754..0000000
--- a/arch/arm/boards/versatile/env/init/ps1
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-
-if [ ${global.allow_color} = "true" ]; then
- export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# "
-else
- export PS1="barebox@\h:\w\n# "
-fi
--
2.8.1
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^ permalink raw reply related
* [PATCH 2/2] defaultenv-2: remove unused *-menu-add-entry calls
From: Sascha Hauer @ 2016-08-26 5:36 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1472189802-13765-1-git-send-email-s.hauer@pengutronix.de>
The *-menu-add-entry functions no longer exist in defaultenv-2, so
remove the calls to these functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/afi-gf/defaultenv-gf/boot/sd | 5 -----
arch/arm/boards/afi-gf/defaultenv-gf/init/automount | 5 -----
arch/arm/boards/at91sam9m10ihd/env/init/automount | 5 -----
arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand | 5 -----
arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 | 5 -----
arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand | 5 -----
arch/arm/boards/ccxmx51/env/init/mtdparts-nand | 5 -----
arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor | 5 -----
arch/arm/boards/crystalfontz-cfa10036/env/init/automount | 5 -----
arch/arm/boards/datamodul-edm-qmx6/env/init/automount | 5 -----
arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount | 5 -----
arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand | 5 -----
arch/arm/boards/highbank/env/init/automount | 5 -----
arch/arm/boards/karo-tx25/env/init/mtdparts-nand | 5 -----
arch/arm/boards/lubbock/env/init/mtdparts-nor | 5 -----
arch/arm/boards/mainstone/env/init/mtdparts-nor | 5 -----
arch/arm/boards/mx31moboard/env/init/mtdparts-nor | 5 -----
arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor | 5 -----
arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand | 5 -----
arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor | 5 -----
arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand | 5 -----
arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor | 5 -----
arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor | 5 -----
.../phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount | 5 -----
.../arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount | 5 -----
arch/arm/boards/raspberry-pi/env/init/bootargs-base | 5 -----
arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand | 5 -----
arch/arm/boards/versatile/env/boot/nor | 5 -----
arch/arm/boards/versatile/env/boot/nor-update | 5 -----
arch/arm/boards/versatile/env/init/automount | 5 -----
arch/arm/boards/versatile/env/init/mtdparts-nor | 5 -----
arch/arm/boards/zylonite/env/init/mtdparts-nand | 5 -----
arch/ppc/boards/pcm030/env/init/mtdparts-nor | 5 -----
defaultenv/defaultenv-2-base/init/automount | 5 -----
34 files changed, 170 deletions(-)
diff --git a/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd b/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd
index dce0605..aa94b2f 100644
--- a/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd
+++ b/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- boot-menu-add-entry "$0" "kernel & rootfs on SD card"
- exit
-fi
-
global.bootm.image=/boot/uImage
global.bootm.oftree=/boot/oftree
#global.bootm.initrd=<path to initrd>
diff --git a/arch/arm/boards/afi-gf/defaultenv-gf/init/automount b/arch/arm/boards/afi-gf/defaultenv-gf/init/automount
index c67bd1b..560bdb7 100644
--- a/arch/arm/boards/afi-gf/defaultenv-gf/init/automount
+++ b/arch/arm/boards/afi-gf/defaultenv-gf/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth1.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/automount b/arch/arm/boards/at91sam9m10ihd/env/init/automount
index 5bb63cc..96ffa70 100644
--- a/arch/arm/boards/at91sam9m10ihd/env/init/automount
+++ b/arch/arm/boards/at91sam9m10ihd/env/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand
index ac516d8..433bc88 100644
--- a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand
+++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="128k(nand0.at91bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),128k(nand0.bareboxenv2),128k(nand0.oftree),1280k(nand0.free),3M(nand0.kernel),195M(nand0.rootfs),300M(nand0.userdata),-(nand0.cache)"
kernelname="atmel_nand"
diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80
index 44198c8..5457e4e 100644
--- a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80
+++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "SPI NOR partitions"
- exit
-fi
-
mtdparts="32k(m25p0.at91bootstrap)ro,256k(m25p0.barebox),128k(m25p0.bareboxenv),128k(m25p0.bareboxenv2),128k(m25p0.oftree),-(m25p0.kernel)"
kernelname="m25p0"
diff --git a/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand b/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand
index 9335bb1..48c1c5d 100644
--- a/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand
+++ b/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="128k(nand0.xload),256k(nand0.barebox)ro,128k(nand0.bareboxenv),128k(nand0.oftree),4M(nand0.kernel),120M(nand0.rootfs),-(nand0.data)"
kernelname="omap2-nand"
diff --git a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand b/arch/arm/boards/ccxmx51/env/init/mtdparts-nand
index 5ea35d2..27ed38a 100644
--- a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand
+++ b/arch/arm/boards/ccxmx51/env/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="512k(barebox)ro,256k(bareboxenv),3328k(kernel),-(root)"
kernelname="mxc_nand"
diff --git a/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor b/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor
index 8702b40..39777f9 100644
--- a/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor
+++ b/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="256k(boot),256k(env),3584k(kernel),-(root)"
kernelname="physmap-flash.0"
diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/init/automount b/arch/arm/boards/crystalfontz-cfa10036/env/init/automount
index 8fdca7c..6f85c27 100644
--- a/arch/arm/boards/crystalfontz-cfa10036/env/init/automount
+++ b/arch/arm/boards/crystalfontz-cfa10036/env/init/automount
@@ -1,9 +1,4 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
mkdir -p /mnt/disk0.2
automount -d /mnt/disk0.2 '[ -e /dev/disk0.2 ] && mount /dev/disk0.2 /mnt/disk0.2'
diff --git a/arch/arm/boards/datamodul-edm-qmx6/env/init/automount b/arch/arm/boards/datamodul-edm-qmx6/env/init/automount
index 2ce37c7..e786b82 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/env/init/automount
+++ b/arch/arm/boards/datamodul-edm-qmx6/env/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount b/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount
index 8cb5eaf..71dfd95 100644
--- a/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount
+++ b/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
index 7271341..b51104a 100644
--- a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
+++ b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="256k(nand0.barebox),128k(nand0.bareboxenv),1536k(nand0.kernel),-(nand0.root)"
kernelname="nand"
diff --git a/arch/arm/boards/highbank/env/init/automount b/arch/arm/boards/highbank/env/init/automount
index 2c283c6..eb5c07a 100644
--- a/arch/arm/boards/highbank/env/init/automount
+++ b/arch/arm/boards/highbank/env/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand
index e2dcfab..0288163 100644
--- a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand
+++ b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
kernelname="mxc_nand"
diff --git a/arch/arm/boards/lubbock/env/init/mtdparts-nor b/arch/arm/boards/lubbock/env/init/mtdparts-nor
index 3307596..b5c4e32 100644
--- a/arch/arm/boards/lubbock/env/init/mtdparts-nor
+++ b/arch/arm/boards/lubbock/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)"
kernelname="application-flash"
diff --git a/arch/arm/boards/mainstone/env/init/mtdparts-nor b/arch/arm/boards/mainstone/env/init/mtdparts-nor
index 3307596..b5c4e32 100644
--- a/arch/arm/boards/mainstone/env/init/mtdparts-nor
+++ b/arch/arm/boards/mainstone/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)"
kernelname="application-flash"
diff --git a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor
index f09a9cc..ab5b175 100644
--- a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor
+++ b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="512k(nor0.barebox)ro,256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
kernelname="physmap-flash.0"
diff --git a/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor b/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor
index 0d10584..f584307 100644
--- a/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor
+++ b/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor
@@ -1,9 +1,4 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- boot-menu-add-entry "$0" "nor"
- exit
-fi
-
global.bootm.image="/dev/nor0.kernel"
global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro"
diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand
index 84220b7..540277c 100644
--- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand
+++ b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
kernelname="mxc_nand"
diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor
index 2ef6ead..940eb86 100644
--- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor
+++ b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
kernelname="physmap-flash.0"
diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand
index 8a41f62..c7185db 100644
--- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand
+++ b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="512k(nand0.barebox),256k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
kernelname="mxc_nand"
diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor
index f787f28..09c3ba9 100644
--- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor
+++ b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="512k(nor0.barebox),128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
kernelname="physmap-flash.0"
diff --git a/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor
index e617cba..4423943 100644
--- a/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor
+++ b/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="512k(nor0.barebox),256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
kernelname="physmap-flash.0"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount
index a059e19..91ded44 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
index 49d99bd..4b223d8 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/raspberry-pi/env/init/bootargs-base b/arch/arm/boards/raspberry-pi/env/init/bootargs-base
index 4dda550..416dc8a 100644
--- a/arch/arm/boards/raspberry-pi/env/init/bootargs-base
+++ b/arch/arm/boards/raspberry-pi/env/init/bootargs-base
@@ -1,8 +1,3 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Base bootargs"
- exit
-fi
-
global.linux.bootargs.base="console=ttyAMA0,115200"
diff --git a/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand
index 58e859b..42907ae 100644
--- a/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand
+++ b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="0xC0000(nand0.bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),3M(nand0.kernel),-(nand0.rootfs)"
kernelname="atmel_nand"
diff --git a/arch/arm/boards/versatile/env/boot/nor b/arch/arm/boards/versatile/env/boot/nor
index 3f31605..f90bcc3 100644
--- a/arch/arm/boards/versatile/env/boot/nor
+++ b/arch/arm/boards/versatile/env/boot/nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- boot-menu-add-entry "$0" "nor"
- exit
-fi
-
global.bootm.image="/dev/nor0.kernel"
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=5 rootfstype=ubifs"
diff --git a/arch/arm/boards/versatile/env/boot/nor-update b/arch/arm/boards/versatile/env/boot/nor-update
index 728889d..5799ed6 100644
--- a/arch/arm/boards/versatile/env/boot/nor-update
+++ b/arch/arm/boards/versatile/env/boot/nor-update
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- boot-menu-add-entry "$0" "nor update"
- exit
-fi
-
global.bootm.image="/dev/nor0.update"
dtb=/dev/nor0.dtb
diff --git a/arch/arm/boards/versatile/env/init/automount b/arch/arm/boards/versatile/env/init/automount
index 53f9196..d08990b 100644
--- a/arch/arm/boards/versatile/env/init/automount
+++ b/arch/arm/boards/versatile/env/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
diff --git a/arch/arm/boards/versatile/env/init/mtdparts-nor b/arch/arm/boards/versatile/env/init/mtdparts-nor
index 9079d48..20c2b99 100644
--- a/arch/arm/boards/versatile/env/init/mtdparts-nor
+++ b/arch/arm/boards/versatile/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="512k(nor0.barebox)ro,512k(nor0.bareboxenv),4864k(nor0.kernel),256k(nor0.dtb),3M(nor0.update),-(nor0.root)"
kernelname="physmap-flash.0"
diff --git a/arch/arm/boards/zylonite/env/init/mtdparts-nand b/arch/arm/boards/zylonite/env/init/mtdparts-nand
index 9db4652..749318b 100644
--- a/arch/arm/boards/zylonite/env/init/mtdparts-nand
+++ b/arch/arm/boards/zylonite/env/init/mtdparts-nand
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)"
kernelname="pxa3xx_nand-0"
diff --git a/arch/ppc/boards/pcm030/env/init/mtdparts-nor b/arch/ppc/boards/pcm030/env/init/mtdparts-nor
index e900a3b..44c07ea 100644
--- a/arch/ppc/boards/pcm030/env/init/mtdparts-nor
+++ b/arch/ppc/boards/pcm030/env/init/mtdparts-nor
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NOR partitions"
- exit
-fi
-
mtdparts="512k(nor0.bareboxlow),4M(nor0.kernel),512k(nor0.oftree),26M(nor0.root),512k(nor0.barebox),512k(nor0.bareboxenv)"
kernelname="physmap-flash.0"
diff --git a/defaultenv/defaultenv-2-base/init/automount b/defaultenv/defaultenv-2-base/init/automount
index fd1f5a6..959b2c1 100644
--- a/defaultenv/defaultenv-2-base/init/automount
+++ b/defaultenv/defaultenv-2-base/init/automount
@@ -1,10 +1,5 @@
#!/bin/sh
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Automountpoints"
- exit
-fi
-
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
--
2.8.1
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^ permalink raw reply related
* Re: [PATCH v2 6/8] ARM: Add phyCORE-RK3288 SOM support
From: Sascha Hauer @ 2016-08-26 5:43 UTC (permalink / raw)
To: Wadim Egorov; +Cc: barebox
In-Reply-To: <1472042970-35151-6-git-send-email-w.egorov@phytec.de>
On Wed, Aug 24, 2016 at 02:49:28PM +0200, Wadim Egorov wrote:
> The phyCORE-RK3288 aka PCM-059 is a SoM (System on Module)
> containing a RK3288 SoC. The module can be connected to different
> carrier boards.
>
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> ---
> arch/arm/boards/Makefile | 1 +
> arch/arm/boards/phytec-som-rk3288/Makefile | 3 +
> arch/arm/boards/phytec-som-rk3288/board.c | 31 +++++
> .../defaultenv-physom-rk3288/boot/emmc | 6 +
> .../defaultenv-physom-rk3288/boot/mmc | 6 +
> .../defaultenv-physom-rk3288/init/automount | 12 ++
> .../defaultenv-physom-rk3288/init/bootsource | 3 +
> arch/arm/boards/phytec-som-rk3288/lowlevel.c | 44 ++++++
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3288-phycore-som.dts | 148 +++++++++++++++++++++
> arch/arm/mach-rockchip/Kconfig | 7 +
> images/Makefile.rockchip | 4 +
> 12 files changed, 266 insertions(+)
> create mode 100644 arch/arm/boards/phytec-som-rk3288/Makefile
> create mode 100644 arch/arm/boards/phytec-som-rk3288/board.c
> create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc
> create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc
> create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount
> create mode 100644 arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource
> create mode 100644 arch/arm/boards/phytec-som-rk3288/lowlevel.c
> create mode 100644 arch/arm/dts/rk3288-phycore-som.dts
>
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index 9241b66..24ce130 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_PM9G45) += pm9g45/
> obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/
> obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/
> obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/
> +obj-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += phytec-som-rk3288/
> obj-$(CONFIG_MACH_REALQ7) += datamodul-edm-qmx6/
> obj-$(CONFIG_MACH_RPI_COMMON) += raspberry-pi/
> obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/
> diff --git a/arch/arm/boards/phytec-som-rk3288/Makefile b/arch/arm/boards/phytec-som-rk3288/Makefile
> new file mode 100644
> index 0000000..6f34c9a
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-rk3288/Makefile
> @@ -0,0 +1,3 @@
> +obj-y += board.o
> +lwl-y += lowlevel.o
> +bbenv-y += defaultenv-physom-rk3288
> diff --git a/arch/arm/boards/phytec-som-rk3288/board.c b/arch/arm/boards/phytec-som-rk3288/board.c
> new file mode 100644
> index 0000000..8ea6c6c
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-rk3288/board.c
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
> + * Author: Wadim Egorov <w.egorov@phytec.de>
> + *
> + * Device initialization for the phyCORE-RK3288 SoM
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <envfs.h>
> +
> +static int physom_devices_init(void)
> +{
> + if (!of_machine_is_compatible("phytec,rk3288-phycore-som"))
> + return 0;
> +
> + barebox_set_hostname("pcm059");
> + defaultenv_append_directory(defaultenv_physom_rk3288);
> +
> + return 0;
> +}
> +device_initcall(physom_devices_init);
> diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc
> new file mode 100644
> index 0000000..731b07f
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/emmc
> @@ -0,0 +1,6 @@
> +#!/bin/sh
> +
> +global.bootm.image=/mnt/emmc/linuximage
> +global.bootm.oftree=/mnt/emmc/oftree
> +
> +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rw rootwait"
> diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc
> new file mode 100644
> index 0000000..5b19dba
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/boot/mmc
> @@ -0,0 +1,6 @@
> +#!/bin/sh
> +
> +global.bootm.image=/mnt/sdmmc/linuximage
> +global.bootm.oftree=/mnt/sdmmc/oftree
> +
> +global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rw rootwait"
> diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount
> new file mode 100644
> index 0000000..2f9d78a
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/automount
> @@ -0,0 +1,12 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> + init-menu-add-entry "$0" "Automountpoints"
> + exit
> +fi
This is no longer needed.
> +
> +mkdir -p /mnt/emmc
> +automount -d /mnt/emmc 'mshc0.probe=1 && [ -e /dev/mshc0.0 ] && mount /dev/mshc0.0 /mnt/emmc'
> +
> +mkdir -p /mnt/sdmmc
> +automount -d /mnt/sdmmc 'mshc1.probe=1 && [ -e /dev/mshc1.0 ] && mount /dev/mshc1.0 /mnt/sdmmc'
Maybe rename this to automount-mmc or similar to not overwrite the
generic automount file? You'll probably want to have the generic
automountpoints once you get network support.
> diff --git a/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource
> new file mode 100644
> index 0000000..36d34e3
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-rk3288/defaultenv-physom-rk3288/init/bootsource
> @@ -0,0 +1,3 @@
> +#!/bin/sh
> +
> +global.boot.default="emmc mmc"
This should go to defaultenv-physom-rk3288/nv/boot.default
> +&emmc {
> + broken-cd;
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + disable-wp;
> + non-removable;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
> + vmmc-supply = <&vcc33>;
> + vqmmc-supply = <&vcc18>;
> + status = "okay";
> +
> + #size-cells = <1>;
> + #address-cells = <1>;
> +
> + partition@8000 {
> + label = "spl";
> + reg = <0x8000 0x8000>;
> + };
> +
> + partition@20000 {
> + label = "barebox";
> + reg = <0x20000 0xe0000>;
> + };
> +
> + partition@e0000 {
> + label = "barebox-environment";
> + reg = <0xe0000 0x20000>;
> + };
> +};
The reg property is <start size>, so it seems the barebox partition and
the barebox-environment partition overlap.
> +
> +&sdmmc {
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + card-detect-delay = <200>;
> + disable-wp;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
> + vmmc-supply = <&vcc33>;
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@8000 {
> + label = "spl";
> + reg = <0x8000 0x8000>;
> + };
> +
> + partition@20000 {
> + label = "barebox";
> + reg = <0x20000 0xe0000>;
> + };
> +
> + partition@e0000 {
> + label = "barebox-environment";
> + reg = <0xe0000 0x20000>;
> + };
> +};
Same here.
The rest of the series looks fine to me, enough to resend this patch.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* Re: [PATCH v2] ARM: vector_table: Fix creation of second level page table
From: Sascha Hauer @ 2016-08-26 5:45 UTC (permalink / raw)
To: Peter Kardos; +Cc: barebox
In-Reply-To: <d3c2af19-1d8f-a078-ef33-3cc43a14d990@gmail.com>
On Thu, Aug 25, 2016 at 11:32:43PM +0200, Peter Kardos wrote:
> Tested this one as well with my AT91RM9200 system, v2016.08 + patch; The
> system starts/boots as expected.
> If no one objects, we can consider this issue closed/fixed.
I took this as a
Tested-by: Peter Kardos <kardos.peter.sk@gmail.com>
Thanks for testing.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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* Re: [PATCH v2] ARM: vector_table: Fix creation of second level page table
From: Peter Kardos @ 2016-08-27 19:09 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20160826054533.GP20657@pengutronix.de>
Thanks for the fix.
Peter
On 8/26/2016 7:45 AM, Sascha Hauer wrote:
> On Thu, Aug 25, 2016 at 11:32:43PM +0200, Peter Kardos wrote:
>> Tested this one as well with my AT91RM9200 system, v2016.08 + patch; The
>> system starts/boots as expected.
>> If no one objects, we can consider this issue closed/fixed.
> I took this as a
> Tested-by: Peter Kardos <kardos.peter.sk@gmail.com>
>
> Thanks for testing.
>
> Sascha
>
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* Re: Fwd: Shouldn't boot_board be called from boot instead of init?
From: Sascha Hauer @ 2016-08-29 7:06 UTC (permalink / raw)
To: Guillermo Rodriguez Garcia; +Cc: barebox
In-Reply-To: <CABDcavaN3ZV6bYVkBs_i4emasduzxVWX3b4k=MwMafeCYU8KaA@mail.gmail.com>
On Wed, Aug 24, 2016 at 04:42:42PM +0200, Guillermo Rodriguez Garcia wrote:
> Hi Sascha,
>
> 2016-08-23 10:13 GMT+02:00 Sascha Hauer <s.hauer@pengutronix.de>:
> > On Mon, Aug 22, 2016 at 11:12:55AM +0200, Guillermo Rodriguez Garcia wrote:
> >> >> > However, I would be glad to get rid of defaultenv-1 rather sooner than
> >> >> > later.
> >> >>
> >> >> Uhm. I actually like defaultenv-1 better than defaultenv-2. Why not
> >> >> keep both? Everyone can then make their choice :)
> >> >
> >> > That's interesting. What do you like better about defaultenv-1? This
> >> > information could help me to improve defaultenv-2.
> >>
> >> I guess it is just a matter of personal preference but I find
> >> defaultenv-1 easier to understand and easier to manage. With
> >> defaultenv-1 we basically have just one configuration file to edit
> >> (/env/config) and optionally init_board and/or boot_board (which are
> >> not needed in a majority of the cases). So everything you need to
> >> know/edit/tweak is in /env/config.
> >>
> >> With defaultenv-2 the "board configuration" is scattered through a
> >> number of tiny files, some of which contain just a single value (see
> >> for example nv/autoboot_timeout or nv/user). I find this more
> >> difficult to manage -- you need to edit a lot of tiny files instead of
> >> just one. Also I feel that the flow of control is less obvious for the
> >> same reason.
> >>
> >> I'd say defaultenv-1 feels more "imperative" and defaultenv-2 feels
> >> more "declarative", and I prefer the former. But I am fully aware that
> >> this is just a matter of personal preference :)
> >
> > I understand your concerns but do not share them all. Maybe we can find
> > a way to either make defaultenv-2 more acceptable for you or to make
> > defaultenv-1 more appealing to me?
> >
> > About the number of small files that only contain a single value:
> > defaultenv-1 was the opposite and that was a problem. Whenever a board
> > wanted to adjust a single value, say the autoboot timeout, it had to
> > duplicate a big file and very soon we had many nearly identical copies
> > of that file and nobody knew what the actual change was.
>
> Not sure what you mean with duplicating a big file. With defaultenv-1 most
> of the time the only single file you need to edit is /env/config, which is quite
> small, and most of it should be board specific anyway. I find this (the fact
> that all I need to edit/tweak is in that single file) quite convenient.
>
> > With NV
> > variables this has become better. I never felt the need though to dig
> > through the individual /env/nv files, here the 'nv' and 'global'
> > commands or the 'magicvar' command to much better jobs. Normally you
> > only have to hand edit /env/nv files when you want to change the default
> > of a variable for a given board.
> >
> > Another thing that made another approach than with defaultenv-1
> > necessary was the variables that contain "net", "disk", "nor", "nand".
> > This did not scale and was not extensible because you could not pass
> > some arbitrary file and use it as kernel.
>
> I can understand that one. But on the other hand not every target needs
> that flexibility. That's why I said that I don't see the need to drop
> defaultenv-1.
> Isn't it better to leave both defaultenv-1 and defaultenv-2 alive and
> let everyone
> decide which one suits them best?
>
> My impression when I look at defaultenv-2 is as described above: OK,
> more flexibility (which I currently don't need), but also more complexity,
> configuration scattered over more files, more management overhead.
> Plus, I'm happy with defaultenv-1, so why change?
>
> >
> > I wonder if defaultenv-1 is not customizable enough and on the other
> > hand your board does only boot from very special locations, do you need
> > a generic default environment at all or are you better off using your
> > own special environment?
>
> In my case, I am currently using barebox on 3 boards. All of them support
> multiple boot sources (NAND, NOR, MMC) plus NFS. For all of them I only
> needed to edit /env/config; the other files in the default environment
> (init, update, boot) all work fine. So (for me) defaultenv-1 was customizable
> enough, and I did indeed benefit from having a generic default environment
> instead of a custom one written from scratch.
>
> >
> > Finally, could this be a documentation issue? Could you have another
> > look at defaultenv-2 and see what is not clear or what needs further
> > convenience to be better usable?
>
> I think the documentation is fine as a reference. Perhaps a tutorial showing
> how to migrate from defaultenv-1 to defaultenv-2 could help "convert" people
> to defaultenv-2 by holding their hand and taking them from what they know
> (defaultenv-1) to the "new stuff".
>
> But even then I still wonder -- why not let both approaches coexist?
It's my interest to keep the diversion between boards small. Normally
as a barebox user you shouldn't care about the particular type of the
board you have, instead it should always feel the same (Or, if you
decide to customize barebox via Kconfig or patches, it should be
applyable for all boards without having to repeat this step for every
board you use in the future). defaultenv-1 make this goal hard to
archieve. Most boards only copy and modify /env/config, but some also
duplicate /env/boot and other files. /env/boot is problematic because
it contains behaviour, not configuration. With each duplication we
introduce a new behaviour which means that this board beahves different
from the rest of the boards and also won't get updates from the generic
/env/boot file anymore.
This all is not problematic when you only care about one board or a few
boards that you use, but is a nightmare when you have > 100 boards
from which you only have access to a few of them. defaultenv-2 is better
in this regard since we can do adjustments without changing other things
and it generally needs less adjustments.
I think it's not really defaultenv-1 that disturbs me, but more the
in-tree users of it. Also it's not really nice that by choosing a board
you also choose between defaultenv-1 and defaultenv-2. It would be much
nicer if these choices were independent.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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* [PATCH] video: backlight: fix the value of 'brightness_max'
From: Sascha Hauer @ 2016-08-29 15:36 UTC (permalink / raw)
To: Barebox List
Fixes: 87c6a88 video/backlight-pwm: fix the value of 'brightness_max'.
brightness_max should really contain the number of brightness steps, so
the number of elements in the brightness array.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/video/backlight-pwm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/video/backlight-pwm.c b/drivers/video/backlight-pwm.c
index 7f1715d..2915dba 100644
--- a/drivers/video/backlight-pwm.c
+++ b/drivers/video/backlight-pwm.c
@@ -156,6 +156,8 @@ static int pwm_backlight_parse_dt(struct device_d *dev,
if (ret < 0)
return ret;
+ pwm_backlight->backlight.brightness_max = length - 1;
+
for (i = 0; i < length; i++)
if (pwm_backlight->levels[i] > pwm_backlight->scale)
pwm_backlight->scale = pwm_backlight->levels[i];
@@ -165,8 +167,8 @@ static int pwm_backlight_parse_dt(struct device_d *dev,
} else {
/* We implicitly assume here a linear levels array { 0, 1, 2, ... 100 } */
pwm_backlight->scale = 100;
+ pwm_backlight->backlight.brightness_max = pwm_backlight->scale;
}
- pwm_backlight->backlight.brightness_max = pwm_backlight->scale;
pwm_backlight->enable_gpio = of_get_named_gpio_flags(node, "enable-gpios", 0, &flags);
--
2.8.1
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* [PATCH] commands: usbgadget: Fix -d option help text
From: Sascha Hauer @ 2016-08-29 15:37 UTC (permalink / raw)
To: Barebox List
The -d option disables any currently active gadget, it does not
necessarily have to be a serial gadget.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
commands/usbgadget.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/commands/usbgadget.c b/commands/usbgadget.c
index fc2252a..a7e8d6c 100644
--- a/commands/usbgadget.c
+++ b/commands/usbgadget.c
@@ -96,7 +96,7 @@ BAREBOX_CMD_HELP_OPT ("-a", "Create CDC ACM function")
BAREBOX_CMD_HELP_OPT ("-s", "Create Generic Serial function")
BAREBOX_CMD_HELP_OPT ("-A <desc>", "Create Android Fastboot function")
BAREBOX_CMD_HELP_OPT ("-D <desc>", "Create DFU function")
-BAREBOX_CMD_HELP_OPT ("-d", "Disable the serial gadget")
+BAREBOX_CMD_HELP_OPT ("-d", "Disable the currently running gadget")
BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(usbgadget)
--
2.8.1
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* [PATCH] blspec: Handle nfs:// pathes from boot
From: Sascha Hauer @ 2016-08-29 15:37 UTC (permalink / raw)
To: Barebox List
Fixes: cb47dde boot: Call blspec_scan_directory() only on strings containing an absolute path
This commit introduced a check if the path contains a '/' at the
beginning. For booting a bootloader spec entry from NFS we have to
test the path for starting with "nfs://" aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/boot.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/boot.c b/common/boot.c
index e66bacb..df9cba5 100644
--- a/common/boot.c
+++ b/common/boot.c
@@ -250,6 +250,7 @@ static int bootscript_scan_path(struct bootentries *bootentries, const char *pat
* - a cdev name
* - a full path of a directory containing bootloader spec entries
* - a full path of a directory containing bootscripts
+ * - a nfs:// path
*
* Returns the number of entries found or a negative error code.
*/
@@ -263,7 +264,7 @@ int bootentry_create_from_name(struct bootentries *bootentries,
if (ret > 0)
found += ret;
- if (*name == '/') {
+ if (*name == '/' || !strncmp(name, "nfs://", 6)) {
ret = blspec_scan_directory(bootentries, name);
if (ret > 0)
found += ret;
--
2.8.1
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* [PATCH] usb: chipidea i.MX: Do not return unnecessary error
From: Sascha Hauer @ 2016-08-29 15:37 UTC (permalink / raw)
To: Barebox List
We only allow to setup the host/peripheral role once, when it's already
set then we return -EBUSY.
Return 0 instead when we set the same role again and only return -EBUSY
when we actually try to change the role.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/usb/imx/chipidea-imx.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/imx/chipidea-imx.c b/drivers/usb/imx/chipidea-imx.c
index a799abe..fb451f3 100644
--- a/drivers/usb/imx/chipidea-imx.c
+++ b/drivers/usb/imx/chipidea-imx.c
@@ -150,7 +150,7 @@ static int imx_chipidea_probe_dt(struct imx_chipidea *ci)
static int ci_register_role(struct imx_chipidea *ci)
{
- if (ci->role_registered)
+ if (ci->role_registered != IMX_USB_MODE_OTG)
return -EBUSY;
if (ci->mode == IMX_USB_MODE_HOST) {
@@ -180,8 +180,12 @@ static int ci_set_mode(struct param_d *param, void *priv)
{
struct imx_chipidea *ci = priv;
- if (ci->role_registered)
- return -EBUSY;
+ if (ci->role_registered != IMX_USB_MODE_OTG) {
+ if (ci->role_registered == ci->mode)
+ return 0;
+ else
+ return -EBUSY;
+ }
return ci_register_role(ci);
}
@@ -225,6 +229,7 @@ static int imx_chipidea_probe(struct device_d *dev)
ci = xzalloc(sizeof(*ci));
ci->dev = dev;
+ ci->role_registered = IMX_USB_MODE_OTG;
if (IS_ENABLED(CONFIG_OFDEVICE) && dev->device_node) {
ret = imx_chipidea_probe_dt(ci);
--
2.8.1
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