* [PATCH] ARM: imx6: reset PLL2's PFD2 on i.MX6D
From: Uwe Kleine-König @ 2016-09-14 7:56 UTC (permalink / raw)
To: barebox
The check for is_imx6q was introduced initially in
f1f6d76370b3 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources")
to differentiate between i.MX6DL+i.MX6SL and i.MX6Q. The i.MX6D must be
handled like the latter, so drop the check. i.MX6DL+i.MX6SL can be
ignored here since since
a66596282413 ("imx6: lowlevel_init: Fix workaround for new i.MX6s chips")
the PFD handling is only done for i.MX6DQ.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-imx/imx6.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb8964ac8..4391839a0b7e 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -77,7 +77,7 @@ void imx6_init_lowlevel(void)
BM_ANADIG_PFD_480_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+ BM_ANADIG_PFD_528_PFD2_CLKGATE |
BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
@@ -88,7 +88,7 @@ void imx6_init_lowlevel(void)
BM_ANADIG_PFD_480_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+ BM_ANADIG_PFD_528_PFD2_CLKGATE |
BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
--
2.8.1
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* [PATCH 1/2] pbl: console: Make it work with multiple setup_c()
From: Sascha Hauer @ 2016-09-14 8:21 UTC (permalink / raw)
To: Barebox List
setup_c() may be called multiple times. When we store the pointer
to the console in bss, then it's zeroed during setup_c() and the
pointer to the console is lost. Initialize the pointer explicitly
to a non zero value to force storing it in the data section.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
pbl/console.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/pbl/console.c b/pbl/console.c
index 4cefe748..0607a31 100644
--- a/pbl/console.c
+++ b/pbl/console.c
@@ -1,8 +1,10 @@
#include <common.h>
#include <debug_ll.h>
-static void (*__putc)(void *ctx, int c);
-static void *putc_ctx;
+#define INVALID_PTR ((void *)-1)
+
+static void (*__putc)(void *ctx, int c) = INVALID_PTR;
+static void *putc_ctx = INVALID_PTR;
/**
* pbl_set_putc() - setup UART used for PBL console
@@ -20,10 +22,10 @@ void pbl_set_putc(void (*putcf)(void *ctx, int c), void *ctx)
void console_putc(unsigned int ch, char c)
{
- if (!__putc)
- putc_ll(c);
- else
+ if (__putc != INVALID_PTR)
__putc(putc_ctx, c);
+ else
+ putc_ll(c);
}
int console_puts(unsigned int ch, const char *str)
--
2.8.1
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* [PATCH 2/2] ARM: i.MX6: Sabrelite: Add PBL console support
From: Sascha Hauer @ 2016-09-14 8:21 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473841290-3935-1-git-send-email-s.hauer@pengutronix.de>
Add PBL console support to allow for better debugging.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c | 57 +++++++++++++++++++---
1 file changed, 49 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
index abfb77a..3b51e01 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
@@ -3,29 +3,70 @@
#include <mach/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
+#include <mach/imx6-regs.h>
+#include <io.h>
+#include <mach/debug_ll.h>
+#include <mach/esdctl.h>
+#include <asm/cache.h>
extern char __dtb_imx6q_sabrelite_start[];
-ENTRY_FUNCTION(start_imx6q_sabrelite, r0, r1, r2)
+static noinline void imx6q_sabrelite_start(void)
{
- void *fdt;
+ void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+ void __iomem *uart = IOMEM(MX6_UART2_BASE_ADDR);
+
+ writel(0x4, iomuxbase + 0x0bc);
+
+ imx6_ungate_all_peripherals();
+ imx6_uart_setup(uart);
+ pbl_set_putc(imx_uart_putc, uart);
+ pr_debug("Freescale i.MX6q SabreLite\n");
+
+ imx6q_barebox_entry(__dtb_imx6q_sabrelite_start);
+}
+
+ENTRY_FUNCTION(start_imx6q_sabrelite, r0, r1, r2)
+{
imx6_cpu_lowlevel_init();
- fdt = __dtb_imx6q_sabrelite_start - get_runtime_offset();
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+ barrier();
- barebox_arm_entry(0x10000000, SZ_1G, fdt);
+ imx6q_sabrelite_start();
}
extern char __dtb_imx6dl_sabrelite_start[];
-ENTRY_FUNCTION(start_imx6dl_sabrelite, r0, r1, r2)
+static noinline void imx6dl_sabrelite_start(void)
{
- void *fdt;
+ void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+ void __iomem *uart = IOMEM(MX6_UART2_BASE_ADDR);
+
+ writel(0x4, iomuxbase + 0x16c);
+
+ imx6_ungate_all_peripherals();
+ imx6_uart_setup(uart);
+ pbl_set_putc(imx_uart_putc, uart);
+ pr_debug("Freescale i.MX6q SabreLite\n");
+
+ imx6q_barebox_entry(__dtb_imx6q_sabrelite_start);
+}
+
+ENTRY_FUNCTION(start_imx6dl_sabrelite, r0, r1, r2)
+{
imx6_cpu_lowlevel_init();
- fdt = __dtb_imx6dl_sabrelite_start - get_runtime_offset();
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+ barrier();
- barebox_arm_entry(0x10000000, SZ_1G, fdt);
+ imx6dl_sabrelite_start();
}
--
2.8.1
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* [PATCH 2/2] ARM: Fix calling of arm_mem_barebox_image()
From: Sascha Hauer @ 2016-09-14 8:21 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473841313-4204-1-git-send-email-s.hauer@pengutronix.de>
arm_mem_barebox_image() is used to pick a suitable place where to
put the final image to. This is called from both the PBL uncompression
code and also from the final image. To make it work properly it is
crucial that it's called with the same arguments both times. Currently
it is called with the wrong image size from the PBL uncompression code.
The size passed to arm_mem_barebox_image() has to be the size of the
whole uncompressed image including the BSS segment size. The PBL code
calls it with the compressed image size instead and without the BSS
segment. This patch fixes this by reading the uncompressed image size
from the compressed binary (the uncompressed size is appended to the
end of the compressed binary by our compression wrappers). The size
of the BSS segment is unknown though by the PBL uncompression code,
so we introduce a maximum BSS size which is used instead.
The code before this patch worked by accident because the base address
of the final image was aligned down to a 1MiB boundary. The alignment
was sufficient already to make enough space. This breaks though when
the uncompressed image including BSS becomes bigger than 1MiB while
the compressed image is smaller.
Fixes: 65071bd0: arm: Clarify memory layout calculation
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/start-pbl.c | 6 ++++--
arch/arm/cpu/start.c | 3 +--
arch/arm/cpu/uncompress.c | 10 ++++++----
arch/arm/include/asm/barebox-arm.h | 9 ++++++++-
4 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index f723edc..5f1469b 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -28,6 +28,7 @@
#include <asm/sections.h>
#include <asm/pgtable.h>
#include <asm/cache.h>
+#include <asm/unaligned.h>
#include "mmu-early.h"
@@ -49,7 +50,7 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
unsigned long memsize, void *boarddata)
{
uint32_t offset;
- uint32_t pg_start, pg_end, pg_len;
+ uint32_t pg_start, pg_end, pg_len, uncompressed_len;
void __noreturn (*barebox)(unsigned long, unsigned long, void *);
uint32_t endmem = membase + memsize;
unsigned long barebox_base;
@@ -63,9 +64,10 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
pg_start = (uint32_t)&input_data - offset;
pg_end = (uint32_t)&input_data_end - offset;
pg_len = pg_end - pg_start;
+ uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
if (IS_ENABLED(CONFIG_RELOCATABLE))
- barebox_base = arm_mem_barebox_image(membase, endmem, pg_len);
+ barebox_base = arm_mem_barebox_image(membase, endmem, uncompressed_len + MAX_BSS_SIZE);
else
barebox_base = TEXT_BASE;
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index f25e592..0120117 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -143,8 +143,7 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
{
unsigned long endmem = membase + memsize;
unsigned long malloc_start, malloc_end;
- unsigned long barebox_size = barebox_image_size +
- ((unsigned long)&__bss_stop - (unsigned long)&__bss_start);
+ unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
if (IS_ENABLED(CONFIG_RELOCATABLE)) {
unsigned long barebox_base = arm_mem_barebox_image(membase,
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index b8e2e9f..eeb5a65 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -29,6 +29,7 @@
#include <asm/sections.h>
#include <asm/pgtable.h>
#include <asm/cache.h>
+#include <asm/unaligned.h>
#include <debug_ll.h>
@@ -44,7 +45,7 @@ static int __attribute__((__used__))
void __noreturn barebox_multi_pbl_start(unsigned long membase,
unsigned long memsize, void *boarddata)
{
- uint32_t pg_len;
+ uint32_t pg_len, uncompressed_len;
void __noreturn (*barebox)(unsigned long, unsigned long, void *);
uint32_t endmem = membase + memsize;
unsigned long barebox_base;
@@ -72,10 +73,11 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
*/
pg_start = image_end + 1;
pg_len = *(image_end);
+ uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
if (IS_ENABLED(CONFIG_RELOCATABLE))
barebox_base = arm_mem_barebox_image(membase, endmem,
- pg_len);
+ uncompressed_len + MAX_BSS_SIZE);
else
barebox_base = TEXT_BASE;
@@ -92,8 +94,8 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
free_mem_ptr = arm_mem_early_malloc(membase, endmem);
free_mem_end_ptr = arm_mem_early_malloc_end(membase, endmem);
- pr_debug("uncompressing barebox binary at 0x%p (size 0x%08x) to 0x%08lx\n",
- pg_start, pg_len, barebox_base);
+ pr_debug("uncompressing barebox binary at 0x%p (size 0x%08x) to 0x%08lx (uncompressed size: 0x%08x)\n",
+ pg_start, pg_len, barebox_base, uncompressed_len);
pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len);
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 0acdfa3..061296a 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -164,6 +164,13 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
static void __naked noinline __##name \
(uint32_t arg0, uint32_t arg1, uint32_t arg2)
-
+/*
+ * When using compressed images in conjunction with relocatable images
+ * the PBL code must pick a suitable place where to uncompress the barebox
+ * image. For doing this the PBL code must know the size of the final
+ * image including the BSS segment. The BSS size is unknown to the PBL
+ * code, so define a maximum BSS size here.
+ */
+#define MAX_BSS_SIZE SZ_1M
#endif /* _BAREBOX_ARM_H_ */
--
2.8.1
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* [PATCH 1/2] Add comp_copy function for use with CONFIG_IMAGE_COMPRESSION_NONE
From: Sascha Hauer @ 2016-09-14 8:21 UTC (permalink / raw)
To: Barebox List
The Makefile compression commands all append the size of the
uncompressed image. With CONFIG_IMAGE_COMPRESSION_NONE simply
'shipped' is used which does not append the size. Add and use
a special comp_copy function which adds the size. This helps
us to get the uncompressed image size in the startup code later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/pbl/Makefile | 2 +-
images/Makefile | 2 +-
scripts/Makefile.lib | 8 ++++++++
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/pbl/Makefile b/arch/arm/pbl/Makefile
index 1ff39db..c455112 100644
--- a/arch/arm/pbl/Makefile
+++ b/arch/arm/pbl/Makefile
@@ -3,7 +3,7 @@ suffix_$(CONFIG_IMAGE_COMPRESSION_GZIP) = gzip
suffix_$(CONFIG_IMAGE_COMPRESSION_LZO) = lzo
suffix_$(CONFIG_IMAGE_COMPRESSION_LZ4) = lz4
suffix_$(CONFIG_IMAGE_COMPRESSION_XZKERN) = xzkern
-suffix_$(CONFIG_IMAGE_COMPRESSION_NONE) = shipped
+suffix_$(CONFIG_IMAGE_COMPRESSION_NONE) = comp_copy
OBJCOPYFLAGS_zbarebox.bin = -O binary
piggy_o := piggy.$(suffix_y).o
diff --git a/images/Makefile b/images/Makefile
index da9cc8d..0537af1 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -85,7 +85,7 @@ suffix_$(CONFIG_IMAGE_COMPRESSION_GZIP) = gzip
suffix_$(CONFIG_IMAGE_COMPRESSION_LZO) = lzo
suffix_$(CONFIG_IMAGE_COMPRESSION_LZ4) = lz4
suffix_$(CONFIG_IMAGE_COMPRESSION_XZKERN) = xzkern
-suffix_$(CONFIG_IMAGE_COMPRESSION_NONE) = shipped
+suffix_$(CONFIG_IMAGE_COMPRESSION_NONE) = comp_copy
# barebox.z - compressed barebox binary
# ----------------------------------------------------------------
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index e55bc27..e79998c 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -380,6 +380,14 @@ cmd_lz4 = (cat $(filter-out FORCE,$^) | \
%.lz4: %
$(call if_changed,lz4)
+# comp_copy
+# ---------------------------------------------------------------------------
+# Wrapper which only copies a file, but compatible to the compression
+# functions above. Appends the size to the result file
+quiet_cmd_comp_copy ?= SHIPPED_S $@
+cmd_comp_copy ?= cat $(filter-out FORCE,$^) > $@; \
+ $(call size_append, $(filter-out FORCE,$^)) >> $@
+
quiet_cmd_disasm = DISASM $@
cmd_disasm = $(OBJDUMP) -d $< > $@
--
2.8.1
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* [PATCH] defenv-1: remove unused variable kernelimage_type
From: Sascha Hauer @ 2016-09-14 8:27 UTC (permalink / raw)
To: Barebox List
kernelimage_type is used nowwhere, remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/friendlyarm-mini6410/env/config | 4 ----
arch/arm/boards/friendlyarm-tiny6410/env/config | 4 ----
2 files changed, 8 deletions(-)
diff --git a/arch/arm/boards/friendlyarm-mini6410/env/config b/arch/arm/boards/friendlyarm-mini6410/env/config
index 74beeff..924d7b8 100644
--- a/arch/arm/boards/friendlyarm-mini6410/env/config
+++ b/arch/arm/boards/friendlyarm-mini6410/env/config
@@ -24,13 +24,9 @@ rootfs_type=ubifs
rootfsimage=root-${machine}.${rootfs_type}
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
-kernelimage_type=zimage
kernelimage=zImage-${machine}
-#kernelimage_type=uimage
#kernelimage=uImage-$machine
-#kernelimage_type=raw
#kernelimage=Image-$machine
-#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
diff --git a/arch/arm/boards/friendlyarm-tiny6410/env/config b/arch/arm/boards/friendlyarm-tiny6410/env/config
index 6422e9f..f38535b 100644
--- a/arch/arm/boards/friendlyarm-tiny6410/env/config
+++ b/arch/arm/boards/friendlyarm-tiny6410/env/config
@@ -24,13 +24,9 @@ rootfs_type=ubifs
rootfsimage=root-${machine}.${rootfs_type}
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
-kernelimage_type=zimage
kernelimage=zImage-${machine}
-#kernelimage_type=uimage
#kernelimage=uImage-$machine
-#kernelimage_type=raw
#kernelimage=Image-$machine
-#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
--
2.8.1
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* [PATCH] ARM: karo-tx6: Include correct device tree
From: Sascha Hauer @ 2016-09-14 8:31 UTC (permalink / raw)
To: Barebox List
As a i.MX6dl board dts imx6dl-tx6u.dts should include imx6dl.dtsi, not
the i.MX6q variant. This fixes various pinctrl problems.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx6dl-tx6u.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx6dl-tx6u.dts b/arch/arm/dts/imx6dl-tx6u.dts
index 77fda62..6c26feb 100644
--- a/arch/arm/dts/imx6dl-tx6u.dts
+++ b/arch/arm/dts/imx6dl-tx6u.dts
@@ -1,6 +1,6 @@
/dts-v1/;
-#include <arm/imx6q.dtsi>
+#include <arm/imx6dl.dtsi>
#include <arm/imx6qdl-tx6.dtsi>
#include "imx6qdl.dtsi"
#include "imx6qdl-tx6x.dtsi"
--
2.8.1
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* [PATCH 12/12] ARM: vincell_defconfig: make smaller
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
The image built with vincell_defconfig has become too big to fit
into the SoC internal SRAM. Make it smaller by disabling UBIFS
support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/vincell_defconfig | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/configs/vincell_defconfig b/arch/arm/configs/vincell_defconfig
index 83862de..81bfbed 100644
--- a/arch/arm/configs/vincell_defconfig
+++ b/arch/arm/configs/vincell_defconfig
@@ -104,7 +104,6 @@ CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_MCI=y
-CONFIG_MCI_MMC_BOOT_PARTITIONS=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_STATE_DRV=y
CONFIG_EEPROM_AT25=y
@@ -112,5 +111,4 @@ CONFIG_EEPROM_AT24=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_FS_TFTP=y
-CONFIG_FS_UBIFS=y
-CONFIG_FS_UBIFS_COMPRESSION_LZO=y
+CONFIG_LZO_DECOMPRESS=y
--
2.8.1
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* [PATCH 01/12] ARM: i.MX53: Add uart5 clock support
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx5.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index d3cde7e..c4c47a6 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -467,6 +467,7 @@ int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs)
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C3_BASE_ADDR, NULL);
--
2.8.1
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* [PATCH 11/12] ARM: imx_v7_defconfig: Enable Vincell support
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
Now that we can start images bigger than internal SRAM size we can
enable the Vincell support in the imx_v7_defconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/imx_v7_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index e3a8f47..51cbf60 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -3,8 +3,10 @@ CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
CONFIG_MACH_EMBEDSKY_E9=y
CONFIG_MACH_FREESCALE_MX51_PDK=y
-CONFIG_MACH_FREESCALE_MX53_LOCO=y
CONFIG_MACH_CCMX53=y
+CONFIG_MACH_FREESCALE_MX53_LOCO=y
+CONFIG_MACH_GUF_VINCELL=y
+CONFIG_MACH_GUF_VINCELL_XLOAD=y
CONFIG_MACH_TQMA53=y
CONFIG_MACH_FREESCALE_MX53_VMX53=y
CONFIG_MACH_PHYTEC_SOM_IMX6=y
--
2.8.1
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* [PATCH 05/12] ARM: i.MX53: do not pass base address to imx*_boot_save_loc
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
The functions can determine the necessary base addresses
themselves since they are SoC specific anyway.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/boot.c | 20 ++++++++++++++------
arch/arm/mach-imx/imx25.c | 2 +-
arch/arm/mach-imx/imx27.c | 2 +-
arch/arm/mach-imx/imx35.c | 2 +-
arch/arm/mach-imx/imx51.c | 2 +-
arch/arm/mach-imx/imx53.c | 2 +-
arch/arm/mach-imx/imx6.c | 2 +-
arch/arm/mach-imx/include/mach/generic.h | 13 ++++++-------
8 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 376e370..f6c546d 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -20,7 +20,10 @@
#include <io.h>
#include <mach/generic.h>
#include <mach/imx25-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx35-regs.h>
+#include <mach/imx51-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/imx6-regs.h>
/* [CTRL][TYPE] */
@@ -75,8 +78,9 @@ static void imx25_35_boot_save_loc(unsigned int ctrl, unsigned int type)
bootsource_set(src);
}
-void imx25_boot_save_loc(void __iomem *ccm_base)
+void imx25_boot_save_loc(void)
{
+ void __iomem *ccm_base = IOMEM(MX25_CCM_BASE_ADDR);
uint32_t val;
val = readl(ccm_base + MX25_CCM_RCSR);
@@ -84,8 +88,9 @@ void imx25_boot_save_loc(void __iomem *ccm_base)
(val >> MX25_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
}
-void imx35_boot_save_loc(void __iomem *ccm_base)
+void imx35_boot_save_loc(void)
{
+ void __iomem *ccm_base = IOMEM(MX35_CCM_BASE_ADDR);
uint32_t val;
val = readl(ccm_base + MX35_CCM_RCSR);
@@ -104,8 +109,9 @@ void imx35_boot_save_loc(void __iomem *ccm_base)
#define IMX27_GPCR_BOOT_32BIT_CS0 6
#define IMX27_GPCR_BOOT_8BIT_NAND_512 7
-void imx27_boot_save_loc(void __iomem *sysctrl_base)
+void imx27_boot_save_loc(void)
{
+ void __iomem *sysctrl_base = IOMEM(MX27_SYSCTRL_BASE_ADDR);
enum bootsource src;
uint32_t val;
@@ -136,8 +142,9 @@ void imx27_boot_save_loc(void __iomem *sysctrl_base)
#define IMX51_SBMR_BT_MEM_CTL_SHIFT 0
#define IMX51_SBMR_BMOD_SHIFT 14
-void imx51_boot_save_loc(void __iomem *src_base)
+void imx51_boot_save_loc(void)
{
+ void __iomem *src_base = IOMEM(MX51_SRC_BASE_ADDR);
enum bootsource src = BOOTSOURCE_UNKNOWN;
uint32_t reg;
unsigned int ctrl, type;
@@ -167,8 +174,9 @@ void imx51_boot_save_loc(void __iomem *src_base)
}
#define IMX53_SRC_SBMR 0x4
-void imx53_boot_save_loc(void __iomem *src_base)
+void imx53_boot_save_loc(void)
{
+ void __iomem *src_base = IOMEM(MX53_SRC_BASE_ADDR);
enum bootsource src = BOOTSOURCE_UNKNOWN;
int instance;
uint32_t cfg1 = readl(src_base + IMX53_SRC_SBMR);
@@ -278,7 +286,7 @@ internal_boot:
return;
}
-void imx6_boot_save_loc(void __iomem *src_base)
+void imx6_boot_save_loc(void)
{
enum bootsource src = BOOTSOURCE_UNKNOWN;
int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 2534d75..a4e27dd 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -52,7 +52,7 @@ int imx25_init(void)
{
int val;
- imx25_boot_save_loc((void *)MX25_CCM_BASE_ADDR);
+ imx25_boot_save_loc();
add_generic_device("imx25-esdctl", 0, NULL, MX25_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
/*
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index b99a4ea..81b9f53 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -100,7 +100,7 @@ static void imx27_init_max(void)
int imx27_init(void)
{
imx27_silicon_revision();
- imx27_boot_save_loc((void *)MX27_SYSCTRL_BASE_ADDR);
+ imx27_boot_save_loc();
add_generic_device("imx27-esdctl", DEVICE_ID_SINGLE, NULL,
MX27_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 3e1aa97..d37bdfd 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -55,7 +55,7 @@ int imx35_init(void)
imx35_silicon_revision();
- imx35_boot_save_loc((void *)MX35_CCM_BASE_ADDR);
+ imx35_boot_save_loc();
add_generic_device("imx35-esdctl", 0, NULL, MX35_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index a6784d0..ffe6a7c 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -58,7 +58,7 @@ static void imx51_ipu_mipi_setup(void)
int imx51_init(void)
{
imx_set_silicon_revision("i.MX51", imx51_silicon_revision());
- imx51_boot_save_loc((void *)MX51_SRC_BASE_ADDR);
+ imx51_boot_save_loc();
add_generic_device("imx51-esdctl", 0, NULL, MX51_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
imx51_ipu_mipi_setup();
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 872d293..2758f1b 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -53,7 +53,7 @@ static int imx53_silicon_revision(void)
int imx53_init(void)
{
imx53_silicon_revision();
- imx53_boot_save_loc((void *)MX53_SRC_BASE_ADDR);
+ imx53_boot_save_loc();
add_generic_device("imx53-esdctl", 0, NULL, MX53_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb89..c23cc54 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -120,7 +120,7 @@ int imx6_init(void)
imx6_init_lowlevel();
- imx6_boot_save_loc((void *)MX6_SRC_BASE_ADDR);
+ imx6_boot_save_loc();
rev = readl(MX6_ANATOP_BASE_ADDR + SI_REV);
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index cadc501..9279bef 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -8,13 +8,12 @@
u64 imx_uid(void);
-void imx25_boot_save_loc(void __iomem *ccm_base);
-void imx35_boot_save_loc(void __iomem *ccm_base);
-void imx27_boot_save_loc(void __iomem *sysctrl_base);
-void imx50_boot_save_loc(void __iomem *src_base);
-void imx51_boot_save_loc(void __iomem *src_base);
-void imx53_boot_save_loc(void __iomem *src_base);
-void imx6_boot_save_loc(void __iomem *src_base);
+void imx25_boot_save_loc(void);
+void imx35_boot_save_loc(void);
+void imx27_boot_save_loc(void);
+void imx51_boot_save_loc(void);
+void imx53_boot_save_loc(void);
+void imx6_boot_save_loc(void);
void imx6_get_boot_source(enum bootsource *src, int *instance);
int imx1_init(void);
--
2.8.1
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* [PATCH 10/12] ARM: i.MX53 Vincell: Add NAND xload support
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
The Vincell boards do the SDRAM setup from board init code, so the
image size is limited to the internal SRAM size. To overcome this
limitation use the NAND xload support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/guf-vincell/lowlevel.c | 9 +++++++++
arch/arm/mach-imx/Kconfig | 9 +++++++++
images/Makefile.imx | 14 ++++++++++----
3 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c
index 3985dd7..a346a4d 100644
--- a/arch/arm/boards/guf-vincell/lowlevel.c
+++ b/arch/arm/boards/guf-vincell/lowlevel.c
@@ -12,6 +12,7 @@
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
#include <asm/cache.h>
+#include <mach/xload.h>
#define IOMUX_PADCTL_DDRI_DDR (1 << 9)
@@ -133,6 +134,8 @@ static noinline void imx53_guf_vincell_init(int is_lt)
void __iomem *uart = IOMEM(MX53_UART4_BASE_ADDR);
void *fdt;
u32 r;
+ enum bootsource src;
+ int instance;
arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
@@ -154,6 +157,12 @@ static noinline void imx53_guf_vincell_init(int is_lt)
disable_watchdog();
configure_dram_iomux();
imx_esdctlv4_init();
+
+ imx53_get_boot_source(&src, &instance);
+
+ if (src == BOOTSOURCE_NAND &&
+ IS_ENABLED(CONFIG_MACH_GUF_VINCELL_XLOAD))
+ imx53_nand_start_image();
}
if (is_lt)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a80bc6b..81f78e0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -224,6 +224,15 @@ config MACH_GUF_VINCELL
bool "Garz-Fricke Vincell"
select ARCH_IMX53
+config MACH_GUF_VINCELL_XLOAD
+ depends on MACH_GUF_VINCELL
+ bool "Garz-Fricke Vincell NAND xload support"
+ help
+ The Vincell initializes SDRAM from board code. This normally limits
+ the image size to the size of the SoC internal SRAM. Enable this
+ option to be able to use bigger images when booting from NAND. Images
+ built with this option are no longer bootable from USB though.
+
config MACH_TQMA53
bool "TQ i.MX53 TQMa53"
select ARCH_IMX53
diff --git a/images/Makefile.imx b/images/Makefile.imx
index b02fdff..1904e8b 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -97,14 +97,20 @@ CFG_start_imx53_vmx53.pblx.imximg = $(board)/freescale-mx53-vmx53/flash-header-i
FILE_barebox-freescale-imx53-vmx53.img = start_imx53_vmx53.pblx.imximg
image-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += barebox-freescale-imx53-vmx53.img
+ifdef CONFIG_MACH_GUF_VINCELL_XLOAD
+VINCELL_IMAGE := imx-sram-img
+else
+VINCELL_IMAGE := pblx.imximg
+endif
+
pblx-$(CONFIG_MACH_GUF_VINCELL) += start_imx53_guf_vincell
-CFG_start_imx53_guf_vincell.pblx.imximg = $(board)/guf-vincell/flash-header.imxcfg
-FILE_barebox-guf-vincell.img = start_imx53_guf_vincell.pblx.imximg
+CFG_start_imx53_guf_vincell.$(VINCELL_IMAGE) = $(board)/guf-vincell/flash-header.imxcfg
+FILE_barebox-guf-vincell.img = start_imx53_guf_vincell.$(VINCELL_IMAGE)
image-$(CONFIG_MACH_GUF_VINCELL) += barebox-guf-vincell.img
pblx-$(CONFIG_MACH_GUF_VINCELL) += start_imx53_guf_vincell_lt
-CFG_start_imx53_guf_vincell_lt.pblx.imximg = $(board)/guf-vincell/flash-header.imxcfg
-FILE_barebox-guf-vincell-lt.img = start_imx53_guf_vincell_lt.pblx.imximg
+CFG_start_imx53_guf_vincell_lt.$(VINCELL_IMAGE) = $(board)/guf-vincell/flash-header.imxcfg
+FILE_barebox-guf-vincell-lt.img = start_imx53_guf_vincell_lt.$(VINCELL_IMAGE)
image-$(CONFIG_MACH_GUF_VINCELL) += barebox-guf-vincell-lt.img
pblx-$(CONFIG_MACH_TQMA53) += start_imx53_mba53_512mib
--
2.8.1
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* [PATCH 03/12] ARM: i.MX53 Vincell: Adjust bbu handler partition size to real partition size
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
The bootloader partition size was increased to 0xe0000, so adjust
the barebox update handler partition size accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/guf-vincell/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c
index ee5be10..007b6dd 100644
--- a/arch/arm/boards/guf-vincell/board.c
+++ b/arch/arm/boards/guf-vincell/board.c
@@ -41,7 +41,7 @@ static int vincell_devices_init(void)
clk_set_rate(clk_lookup("nfc_podf"), 33333334);
imx53_bbu_internal_nand_register_handler("nand",
- BBU_HANDLER_FLAG_DEFAULT, SZ_512K);
+ BBU_HANDLER_FLAG_DEFAULT, 0xe0000);
return 0;
}
--
2.8.1
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* [PATCH 04/12] ARM: i.MX53 Vincell: Add PBL console support
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
PBL console support is more useful than debug_ll. Add support
for it to the Vincell Board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/guf-vincell/lowlevel.c | 50 ++++++++++++++++++++--------------
1 file changed, 29 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c
index af7c65d..3985dd7 100644
--- a/arch/arm/boards/guf-vincell/lowlevel.c
+++ b/arch/arm/boards/guf-vincell/lowlevel.c
@@ -11,6 +11,7 @@
#include <mach/generic.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
+#include <asm/cache.h>
#define IOMUX_PADCTL_DDRI_DDR (1 << 9)
@@ -123,12 +124,16 @@ void disable_watchdog(void)
writew(0x0, MX53_WDOG2_BASE_ADDR + 8);
}
-static noinline void imx53_guf_vincell_init(void *fdt)
+extern char __dtb_imx53_guf_vincell_lt_start[];
+extern char __dtb_imx53_guf_vincell_start[];
+
+static noinline void imx53_guf_vincell_init(int is_lt)
{
void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR;
+ void __iomem *uart = IOMEM(MX53_UART4_BASE_ADDR);
+ void *fdt;
u32 r;
- imx5_cpu_lowlevel_init();
arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
writel(0x0088494c, ccm + MX5_CCM_CBCDR);
@@ -137,12 +142,11 @@ static noinline void imx53_guf_vincell_init(void *fdt)
imx53_init_lowlevel_early(800);
- if (IS_ENABLED(CONFIG_DEBUG_LL)) {
- writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
- writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
- imx53_uart_setup_ll();
- putc_ll('>');
- }
+ writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
+ writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
+ imx53_uart_setup(uart);
+ pbl_set_putc(imx_uart_putc, uart);
+ pr_debug("GuF Vincell\n");
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -152,27 +156,31 @@ static noinline void imx53_guf_vincell_init(void *fdt)
imx_esdctlv4_init();
}
+ if (is_lt)
+ fdt = __dtb_imx53_guf_vincell_lt_start;
+ else
+ fdt = __dtb_imx53_guf_vincell_start;
+
imx53_barebox_entry(fdt);
}
-extern char __dtb_imx53_guf_vincell_lt_start[];
-
-ENTRY_FUNCTION(start_imx53_guf_vincell_lt, r0, r1, r2)
+static void __imx53_guf_vincell_init(int is_lt)
{
- void *fdt;
-
- fdt = __dtb_imx53_guf_vincell_lt_start - get_runtime_offset();
+ arm_early_mmu_cache_invalidate();
+ imx5_cpu_lowlevel_init();
+ relocate_to_current_adr();
+ setup_c();
+ barrier();
- imx53_guf_vincell_init(fdt);
+ imx53_guf_vincell_init(is_lt);
}
-extern char __dtb_imx53_guf_vincell_start[];
+ENTRY_FUNCTION(start_imx53_guf_vincell_lt, r0, r1, r2)
+{
+ __imx53_guf_vincell_init(1);
+}
ENTRY_FUNCTION(start_imx53_guf_vincell, r0, r1, r2)
{
- void *fdt;
-
- fdt = __dtb_imx53_guf_vincell_start - get_runtime_offset();
-
- imx53_guf_vincell_init(fdt);
+ __imx53_guf_vincell_init(0);
}
--
2.8.1
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* [PATCH 07/12] ARM: i.MX53: Detect booting from USB
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
The USB download mode can be detected by reading the BMOD[0|1]
bits. Add support for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/boot.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index c72ec61..b66c29d 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -217,6 +217,12 @@ void imx53_get_boot_source(enum bootsource *src, int *instance)
void __iomem *src_base = IOMEM(MX53_SRC_BASE_ADDR);
uint32_t cfg1 = readl(src_base + IMX53_SRC_SBMR);
+ if (((cfg1 >> 24) & 0x3) == 0x3) {
+ *src = BOOTSOURCE_USB;
+ *instance = 0;
+ return;
+ }
+
switch ((cfg1 & 0xff) >> 4) {
case 2:
*src = BOOTSOURCE_HD;
--
2.8.1
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* [PATCH 06/12] ARM: i.MX: Provide bootsource functions for early boot code
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
The regular bootsource functions only work in a running barebox,
provide functions for early code. This has already been done for
i.MX6, this patch adds the same functions for the other SoCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/boot.c | 90 ++++++++++++++++++++++++--------
arch/arm/mach-imx/include/mach/generic.h | 5 ++
2 files changed, 72 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index f6c546d..c72ec61 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -78,7 +78,7 @@ static void imx25_35_boot_save_loc(unsigned int ctrl, unsigned int type)
bootsource_set(src);
}
-void imx25_boot_save_loc(void)
+void imx25_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *ccm_base = IOMEM(MX25_CCM_BASE_ADDR);
uint32_t val;
@@ -88,7 +88,18 @@ void imx25_boot_save_loc(void)
(val >> MX25_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
}
-void imx35_boot_save_loc(void)
+void imx25_boot_save_loc(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+
+ imx25_get_boot_source(&src, &instance);
+
+ bootsource_set(src);
+ bootsource_set_instance(instance);
+}
+
+void imx35_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *ccm_base = IOMEM(MX35_CCM_BASE_ADDR);
uint32_t val;
@@ -98,6 +109,17 @@ void imx35_boot_save_loc(void)
(val >> MX35_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
}
+void imx35_boot_save_loc(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+
+ imx35_get_boot_source(&src, &instance);
+
+ bootsource_set(src);
+ bootsource_set_instance(instance);
+}
+
#define IMX27_SYSCTRL_GPCR 0x18
#define IMX27_GPCR_BOOT_SHIFT 16
#define IMX27_GPCR_BOOT_MASK (0xf << IMX27_GPCR_BOOT_SHIFT)
@@ -109,10 +131,9 @@ void imx35_boot_save_loc(void)
#define IMX27_GPCR_BOOT_32BIT_CS0 6
#define IMX27_GPCR_BOOT_8BIT_NAND_512 7
-void imx27_boot_save_loc(void)
+void imx27_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *sysctrl_base = IOMEM(MX27_SYSCTRL_BASE_ADDR);
- enum bootsource src;
uint32_t val;
val = readl(sysctrl_base + IMX27_SYSCTRL_GPCR);
@@ -121,20 +142,29 @@ void imx27_boot_save_loc(void)
switch (val) {
case IMX27_GPCR_BOOT_UART_USB:
- src = BOOTSOURCE_SERIAL;
+ *src = BOOTSOURCE_SERIAL;
break;
case IMX27_GPCR_BOOT_8BIT_NAND_2k:
case IMX27_GPCR_BOOT_16BIT_NAND_2k:
case IMX27_GPCR_BOOT_16BIT_NAND_512:
case IMX27_GPCR_BOOT_8BIT_NAND_512:
- src = BOOTSOURCE_NAND;
+ *src = BOOTSOURCE_NAND;
break;
default:
- src = BOOTSOURCE_NOR;
+ *src = BOOTSOURCE_NOR;
break;
}
+}
+
+void imx27_boot_save_loc(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+
+ imx27_get_boot_source(&src, &instance);
bootsource_set(src);
+ bootsource_set_instance(instance);
}
#define IMX51_SRC_SBMR 0x4
@@ -142,10 +172,9 @@ void imx27_boot_save_loc(void)
#define IMX51_SBMR_BT_MEM_CTL_SHIFT 0
#define IMX51_SBMR_BMOD_SHIFT 14
-void imx51_boot_save_loc(void)
+void imx51_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *src_base = IOMEM(MX51_SRC_BASE_ADDR);
- enum bootsource src = BOOTSOURCE_UNKNOWN;
uint32_t reg;
unsigned int ctrl, type;
@@ -158,63 +187,78 @@ void imx51_boot_save_loc(void)
ctrl = (reg >> IMX51_SBMR_BT_MEM_CTL_SHIFT) & 0x3;
type = (reg >> IMX51_SBMR_BT_MEM_TYPE_SHIFT) & 0x3;
- src = locations[ctrl][type];
+ *src = locations[ctrl][type];
break;
case 1:
/* reserved */
- src = BOOTSOURCE_UNKNOWN;
+ *src = BOOTSOURCE_UNKNOWN;
break;
case 3:
- src = BOOTSOURCE_SERIAL;
+ *src = BOOTSOURCE_SERIAL;
break;
}
+}
+
+void imx51_boot_save_loc(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+
+ imx51_get_boot_source(&src, &instance);
bootsource_set(src);
+ bootsource_set_instance(instance);
}
#define IMX53_SRC_SBMR 0x4
-void imx53_boot_save_loc(void)
+void imx53_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *src_base = IOMEM(MX53_SRC_BASE_ADDR);
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance;
uint32_t cfg1 = readl(src_base + IMX53_SRC_SBMR);
switch ((cfg1 & 0xff) >> 4) {
case 2:
- src = BOOTSOURCE_HD;
+ *src = BOOTSOURCE_HD;
break;
case 3:
if (cfg1 & (1 << 3))
- src = BOOTSOURCE_SPI;
+ *src = BOOTSOURCE_SPI;
else
- src = BOOTSOURCE_I2C;
+ *src = BOOTSOURCE_I2C;
break;
case 4:
case 5:
case 6:
case 7:
- src = BOOTSOURCE_MMC;
+ *src = BOOTSOURCE_MMC;
break;
default:
break;
}
if (cfg1 & (1 << 7))
- src = BOOTSOURCE_NAND;
+ *src = BOOTSOURCE_NAND;
- switch (src) {
+ switch (*src) {
case BOOTSOURCE_MMC:
case BOOTSOURCE_SPI:
case BOOTSOURCE_I2C:
- instance = (cfg1 >> 20) & 0x3;
+ *instance = (cfg1 >> 20) & 0x3;
break;
default:
- instance = 0;
+ *instance = 0;
break;
}
+}
+
+void imx53_boot_save_loc(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+
+ imx53_get_boot_source(&src, &instance);
bootsource_set(src);
bootsource_set_instance(instance);
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 9279bef..7c275df 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -14,6 +14,11 @@ void imx27_boot_save_loc(void);
void imx51_boot_save_loc(void);
void imx53_boot_save_loc(void);
void imx6_boot_save_loc(void);
+
+void imx25_get_boot_source(enum bootsource *src, int *instance);
+void imx35_get_boot_source(enum bootsource *src, int *instance);
+void imx51_get_boot_source(enum bootsource *src, int *instance);
+void imx53_get_boot_source(enum bootsource *src, int *instance);
void imx6_get_boot_source(enum bootsource *src, int *instance);
int imx1_init(void);
--
2.8.1
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* [PATCH 08/12] mtd: imx-nand: Move v3 register definitions to include file
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
Move v3 register definitions to include file so that they can
be reused for the early nand boot code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/include/mach/imx-nand.h | 49 +++++++++++++++++++++++++++++++
drivers/mtd/nand/nand_imx.c | 49 -------------------------------
2 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h
index b9305e2..0adba09 100644
--- a/arch/arm/mach-imx/include/mach/imx-nand.h
+++ b/arch/arm/mach-imx/include/mach/imx-nand.h
@@ -59,6 +59,55 @@ struct imx_nand_platform_data {
#define NFC_V2_SPAS_SPARESIZE(spas) ((spas) >> 1)
+#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
+#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
+
+#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
+#define NFC_V3_CONFIG1_SP_EN (1 << 0)
+#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
+
+#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
+
+#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
+
+#define NFC_V3_WRPROT (host->regs_ip + 0x0)
+#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
+#define NFC_V3_WRPROT_LOCK (1 << 1)
+#define NFC_V3_WRPROT_UNLOCK (1 << 2)
+#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
+
+#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
+
+#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
+#define NFC_V3_CONFIG2_PS_512 (0 << 0)
+#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
+#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
+#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
+#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
+#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
+#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
+#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
+#define NFC_V3_MX51_CONFIG2_PPB(x) (((x) & 0x3) << 7)
+#define NFC_V3_MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8)
+#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
+#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
+#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
+#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
+
+#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
+#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
+#define NFC_V3_CONFIG3_FW8 (1 << 3)
+#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
+#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
+#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
+#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
+
+#define NFC_V3_IPC (host->regs_ip + 0x2C)
+#define NFC_V3_IPC_CREQ (1 << 0)
+#define NFC_V3_IPC_INT (1 << 31)
+
+#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
+
/*
* Operation modes for the NFC. Valid for v1, v2 and v3
* type controllers.
diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c
index 6f31c28..e0d840b 100644
--- a/drivers/mtd/nand/nand_imx.c
+++ b/drivers/mtd/nand/nand_imx.c
@@ -31,55 +31,6 @@
#include <of_mtd.h>
#include <errno.h>
-#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
-#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
-
-#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
-#define NFC_V3_CONFIG1_SP_EN (1 << 0)
-#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
-
-#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
-
-#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
-
-#define NFC_V3_WRPROT (host->regs_ip + 0x0)
-#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
-#define NFC_V3_WRPROT_LOCK (1 << 1)
-#define NFC_V3_WRPROT_UNLOCK (1 << 2)
-#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
-
-#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
-
-#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
-#define NFC_V3_CONFIG2_PS_512 (0 << 0)
-#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
-#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
-#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
-#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
-#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
-#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
-#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
-#define NFC_V3_MX51_CONFIG2_PPB(x) (((x) & 0x3) << 7)
-#define NFC_V3_MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8)
-#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
-#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
-#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
-#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
-
-#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
-#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
-#define NFC_V3_CONFIG3_FW8 (1 << 3)
-#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
-#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
-#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
-#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
-
-#define NFC_V3_IPC (host->regs_ip + 0x2C)
-#define NFC_V3_IPC_CREQ (1 << 0)
-#define NFC_V3_IPC_INT (1 << 31)
-
-#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
-
struct imx_nand_host {
struct mtd_info mtd;
struct nand_chip nand;
--
2.8.1
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* [PATCH 02/12] ARM: i.MX53 Vincell: Reset phy consistently from device tree
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
The phy reset for the Vincell board is done from device tree whereas
the Vincell-LT resets the phy from board init code. Since both boards
share the same code base the regular Vincell board ends up with a
duplicated phy reset, with the second reset being done after the
FEC has been initialized.
Fix this by removing the phy reset from the board code and adding the
phy reset to the Vincell-LT dts file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/guf-vincell/board.c | 11 -----------
arch/arm/dts/imx53-guf-vincell-lt.dts | 1 +
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c
index 43c1952..ee5be10 100644
--- a/arch/arm/boards/guf-vincell/board.c
+++ b/arch/arm/boards/guf-vincell/board.c
@@ -29,15 +29,6 @@
#include <mach/bbu.h>
#include <mach/imx5.h>
-#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
-
-static void vincell_fec_reset(void)
-{
- gpio_direction_output(LOCO_FEC_PHY_RST, 0);
- mdelay(1);
- gpio_set_value(LOCO_FEC_PHY_RST, 1);
-}
-
static int vincell_devices_init(void)
{
if (!of_machine_is_compatible("guf,imx53-vincell") &&
@@ -49,8 +40,6 @@ static int vincell_devices_init(void)
clk_set_rate(clk_lookup("emi_slow_podf"), 133333334);
clk_set_rate(clk_lookup("nfc_podf"), 33333334);
- vincell_fec_reset();
-
imx53_bbu_internal_nand_register_handler("nand",
BBU_HANDLER_FLAG_DEFAULT, SZ_512K);
diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts
index bcc378d..67a4133 100644
--- a/arch/arm/dts/imx53-guf-vincell-lt.dts
+++ b/arch/arm/dts/imx53-guf-vincell-lt.dts
@@ -136,6 +136,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
--
2.8.1
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* [PATCH 09/12] ARM: i.MX53: Implement NAND xload
From: Sascha Hauer @ 2016-09-14 9:12 UTC (permalink / raw)
To: Barebox List
In-Reply-To: <1473844368-13030-1-git-send-email-s.hauer@pengutronix.de>
Some i.MX53 want to setup the SDRAM from C code rather than
from DCD tables. The image size for these boards is limited
to the internal SRAM size. To overcome this limitation for
i.MX53 boards booting from NAND implement an xload mechanism
to load only the PBL to SRAM and let barebox load the rest
of the image itself after SDRAM has been initialized.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/include/mach/xload.h | 1 +
arch/arm/mach-imx/xload-imx-nand.c | 308 +++++++++++++++++++++++++++++++++
3 files changed, 310 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/xload-imx-nand.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0763944..a216c9b 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -25,4 +25,4 @@ obj-pbl-y += esdctl.o boot.o
obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
lwl-y += cpu_init.o
-pbl-y += xload-spi.o xload-esdhc.o xload-common.o
+pbl-y += xload-spi.o xload-esdhc.o xload-common.o xload-imx-nand.o
diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h
index 997522e..3898d66 100644
--- a/arch/arm/mach-imx/include/mach/xload.h
+++ b/arch/arm/mach-imx/include/mach/xload.h
@@ -1,6 +1,7 @@
#ifndef __MACH_XLOAD_H
#define __MACH_XLOAD_H
+int imx53_nand_start_image(void);
int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len);
int imx6_spi_start_image(int instance);
int imx6_esdhc_load_image(int instance, void *buf, int len);
diff --git a/arch/arm/mach-imx/xload-imx-nand.c b/arch/arm/mach-imx/xload-imx-nand.c
new file mode 100644
index 0000000..22e41fa
--- /dev/null
+++ b/arch/arm/mach-imx/xload-imx-nand.c
@@ -0,0 +1,308 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#define pr_fmt(fmt) "imx-nand-boot: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <linux/mtd/nand.h>
+#include <mach/imx-nand.h>
+#include <mach/generic.h>
+#include <mach/imx53-regs.h>
+#include <mach/xload.h>
+
+struct imx_nand {
+ void __iomem *base;
+ void __iomem *main_area0;
+ void __iomem *regs_ip;
+ void __iomem *regs_axi;
+ void *spare0;
+ int pagesize;
+ int v1;
+ int pages_per_block;
+};
+
+static void wait_op_done(struct imx_nand *host)
+{
+ u32 r;
+
+ while (1) {
+ r = readl(NFC_V3_IPC);
+ if (r & NFC_V3_IPC_INT)
+ break;
+ };
+
+ r &= ~NFC_V3_IPC_INT;
+
+ writel(r, NFC_V3_IPC);
+}
+
+/*
+ * This function issues the specified command to the NAND device and
+ * waits for completion.
+ *
+ * @param cmd command for NAND Flash
+ */
+static void imx_nandboot_send_cmd(struct imx_nand *host, u16 cmd)
+{
+ /* fill command */
+ writel(cmd, NFC_V3_FLASH_CMD);
+
+ /* send out command */
+ writel(NFC_CMD, NFC_V3_LAUNCH);
+
+ /* Wait for operation to complete */
+ wait_op_done(host);
+}
+
+/*
+ * This function sends an address (or partial address) to the
+ * NAND device. The address is used to select the source/destination for
+ * a NAND command.
+ *
+ * @param addr address to be written to NFC.
+ * @param islast True if this is the last address cycle for command
+ */
+static void imx_nandboot_send_addr(struct imx_nand *host, u16 addr)
+{
+ /* fill address */
+ writel(addr, NFC_V3_FLASH_ADDR0);
+
+ /* send out address */
+ writel(NFC_ADDR, NFC_V3_LAUNCH);
+
+ wait_op_done(host);
+}
+
+static void imx_nandboot_nfc_addr(struct imx_nand *host, int page)
+{
+ imx_nandboot_send_addr(host, 0);
+
+ if (host->pagesize == 2048)
+ imx_nandboot_send_addr(host, 0);
+
+ imx_nandboot_send_addr(host, page & 0xff);
+ imx_nandboot_send_addr(host, (page >> 8) & 0xff);
+ imx_nandboot_send_addr(host, (page >> 16) & 0xff);
+
+ if (host->pagesize == 2048)
+ imx_nandboot_send_cmd(host, NAND_CMD_READSTART);
+}
+
+static void imx_nandboot_send_page(struct imx_nand *host, unsigned int ops)
+{
+ uint32_t tmp;
+
+ tmp = readl(NFC_V3_CONFIG1);
+ tmp &= ~(7 << 4);
+ writel(tmp, NFC_V3_CONFIG1);
+
+ /* transfer data from NFC ram to nand */
+ writel(ops, NFC_V3_LAUNCH);
+
+ wait_op_done(host);
+}
+
+static void __memcpy32(void *trg, const void *src, int size)
+{
+ int i;
+ unsigned int *t = trg;
+ unsigned const int *s = src;
+
+ for (i = 0; i < (size >> 2); i++)
+ *t++ = *s++;
+}
+
+static void imx_nandboot_get_page(struct imx_nand *host, unsigned int page)
+{
+ imx_nandboot_send_cmd(host, NAND_CMD_READ0);
+ imx_nandboot_nfc_addr(host, page);
+ imx_nandboot_send_page(host, NFC_OUTPUT);
+}
+
+static int imx_nandboot_read_page(struct imx_nand *host, unsigned int page,
+ void *buf)
+{
+ int nsubpages;
+ u32 eccstat, err;
+
+ imx_nandboot_get_page(host, page);
+
+ __memcpy32(buf, host->main_area0, host->pagesize);
+
+ eccstat = readl(NFC_V3_ECC_STATUS_RESULT);
+ nsubpages = host->pagesize / 512;
+
+ do {
+ err = eccstat & 0xf;
+ if (err == 0xf)
+ return -EBADMSG;
+ eccstat >>= 4;
+ } while (--nsubpages);
+
+ return 0;
+}
+
+static int dbbt_block_is_bad(void *_dbbt, int block)
+{
+ int i;
+ u32 *dbbt = _dbbt;
+ int num_bad_blocks;
+
+ if (!_dbbt)
+ return false;
+
+ dbbt++; /* reserved */
+
+ num_bad_blocks = *dbbt++;
+
+ for (i = 0; i < num_bad_blocks; i++) {
+ if (*dbbt == block)
+ return true;
+ dbbt++;
+ }
+
+ return false;
+}
+
+static int read_firmware(struct imx_nand *host, void *dbbt, int page, void *buf,
+ int npages)
+{
+ int ret;
+
+ if (dbbt_block_is_bad(dbbt, page / host->pages_per_block))
+ page = ALIGN(page, host->pages_per_block);
+
+ while (npages) {
+ if (!(page % host->pages_per_block)) {
+ if (dbbt_block_is_bad(NULL, page / host->pages_per_block)) {
+ page += host->pages_per_block;
+ continue;
+ }
+ }
+
+ ret = imx_nandboot_read_page(host, page, buf);
+ if (ret)
+ return ret;
+
+ buf += host->pagesize;
+ page++;
+ npages--;
+ }
+
+ return 0;
+}
+
+int imx53_nand_start_image(void)
+{
+ struct imx_nand host;
+ void *buf = IOMEM(MX53_CSD0_BASE_ADDR);
+ void *dbbt = NULL;
+ int page_firmware1, page_firmware2, page_dbbt, image_size, npages;
+ void (*firmware)(void);
+ int ret;
+ u32 cfg1 = readl(IOMEM(MX53_SRC_BASE_ADDR) + 0x4);
+
+ host.base = IOMEM(MX53_NFC_AXI_BASE_ADDR);
+ host.main_area0 = host.base;
+ host.regs_ip = IOMEM(MX53_NFC_BASE_ADDR);
+ host.regs_axi = host.base + 0x1e00;
+ host.spare0 = host.base + 0x1000;
+
+ switch ((cfg1 >> 14) & 0x3) {
+ case 0:
+ host.pagesize = 512;
+ break;
+ case 1:
+ host.pagesize = 2048;
+ break;
+ case 2:
+ case 3:
+ host.pagesize = 4096;
+ break;
+ }
+
+ switch ((cfg1 >> 17) & 0x3) {
+ case 0:
+ host.pages_per_block = 32;
+ break;
+ case 1:
+ host.pages_per_block = 64;
+ break;
+ case 2:
+ host.pages_per_block = 128;
+ break;
+ case 3:
+ host.pages_per_block = 256;
+ break;
+ }
+
+ pr_debug("Using pagesize %d, %d pages per block\n",
+ host.pagesize, host.pages_per_block);
+
+ ret = imx_nandboot_read_page(&host, 0, buf);
+ if (ret)
+ return ret;
+
+ if (*(u32 *)(buf + 0x4) != 0x20424346) {
+ pr_err("No FCB Found on flash\n");
+ return -EINVAL;
+ }
+
+ page_firmware1 = *(u32 *)(buf + 0x68);
+ page_firmware2 = *(u32 *)(buf + 0x6c);
+ page_dbbt = *(u32 *)(buf + 0x78);
+
+ image_size = ALIGN(imx_image_size(), host.pagesize);
+ npages = image_size / host.pagesize;
+
+ if (page_dbbt) {
+ ret = imx_nandboot_read_page(&host, page_dbbt, buf);
+ if (!ret && *(u32 *)(buf + 0x4) == 0x44424254) {
+ ret = imx_nandboot_read_page(&host, page_dbbt + 4, buf);
+ if (!ret) {
+ pr_debug("Using DBBT from page %d\n", page_dbbt + 4);
+ dbbt = buf;
+ buf += host.pagesize;
+ }
+ }
+ }
+
+ pr_debug("Reading firmware from page %d, size %d\n",
+ page_firmware1, image_size);
+
+ ret = read_firmware(&host, dbbt, page_firmware1, buf, npages);
+ if (ret) {
+ pr_debug("Reading primary firmware failed\n");
+ if (page_firmware2) {
+ pr_debug("Reading firmware from page %d, size %d\n",
+ page_firmware2, image_size);
+ ret = read_firmware(&host, dbbt, page_firmware2, buf, npages);
+ if (ret) {
+ pr_err("Could not read firmware\n");
+ return -EINVAL;
+ }
+ } else {
+ pr_err("Reading primary firmware failed, no secondary firmware found\n");
+ return -EINVAL;
+ }
+ }
+
+ pr_debug("Firmware read, starting it\n");
+
+ firmware = buf;
+
+ firmware();
+
+ return 0;
+}
--
2.8.1
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^ permalink raw reply related
* Re: [PATCH 04/12] ARM: i.MX53 Vincell: Add PBL console support
From: Michael Grzeschik @ 2016-09-14 9:24 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
In-Reply-To: <1473844368-13030-4-git-send-email-s.hauer@pengutronix.de>
On Wed, Sep 14, 2016 at 11:12:40AM +0200, Sascha Hauer wrote:
> PBL console support is more useful than debug_ll. Add support
> for it to the Vincell Board.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/boards/guf-vincell/lowlevel.c | 50 ++++++++++++++++++++--------------
> 1 file changed, 29 insertions(+), 21 deletions(-)
>
> diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c
> index af7c65d..3985dd7 100644
> --- a/arch/arm/boards/guf-vincell/lowlevel.c
> +++ b/arch/arm/boards/guf-vincell/lowlevel.c
> @@ -11,6 +11,7 @@
> #include <mach/generic.h>
> #include <asm/barebox-arm.h>
> #include <asm/barebox-arm-head.h>
> +#include <asm/cache.h>
>
> #define IOMUX_PADCTL_DDRI_DDR (1 << 9)
>
> @@ -123,12 +124,16 @@ void disable_watchdog(void)
> writew(0x0, MX53_WDOG2_BASE_ADDR + 8);
> }
>
> -static noinline void imx53_guf_vincell_init(void *fdt)
> +extern char __dtb_imx53_guf_vincell_lt_start[];
> +extern char __dtb_imx53_guf_vincell_start[];
> +
> +static noinline void imx53_guf_vincell_init(int is_lt)
> {
> void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR;
> + void __iomem *uart = IOMEM(MX53_UART4_BASE_ADDR);
This should be MX53_UART2_BASE_ADDR to be consistent with
linux,stdout-path in imx53-guf-vincell.dts and imx53-guf-vincell-lt.dts.
> + void *fdt;
> u32 r;
>
> - imx5_cpu_lowlevel_init();
> arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
>
> writel(0x0088494c, ccm + MX5_CCM_CBCDR);
> @@ -137,12 +142,11 @@ static noinline void imx53_guf_vincell_init(void *fdt)
>
> imx53_init_lowlevel_early(800);
>
> - if (IS_ENABLED(CONFIG_DEBUG_LL)) {
> - writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
> - writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
> - imx53_uart_setup_ll();
> - putc_ll('>');
> - }
> + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
> + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
> + imx53_uart_setup(uart);
> + pbl_set_putc(imx_uart_putc, uart);
> + pr_debug("GuF Vincell\n");
>
> /* Skip SDRAM initialization if we run from RAM */
> r = get_pc();
> @@ -152,27 +156,31 @@ static noinline void imx53_guf_vincell_init(void *fdt)
> imx_esdctlv4_init();
> }
>
> + if (is_lt)
> + fdt = __dtb_imx53_guf_vincell_lt_start;
> + else
> + fdt = __dtb_imx53_guf_vincell_start;
> +
> imx53_barebox_entry(fdt);
> }
>
> -extern char __dtb_imx53_guf_vincell_lt_start[];
> -
> -ENTRY_FUNCTION(start_imx53_guf_vincell_lt, r0, r1, r2)
> +static void __imx53_guf_vincell_init(int is_lt)
> {
> - void *fdt;
> -
> - fdt = __dtb_imx53_guf_vincell_lt_start - get_runtime_offset();
> + arm_early_mmu_cache_invalidate();
> + imx5_cpu_lowlevel_init();
> + relocate_to_current_adr();
> + setup_c();
> + barrier();
>
> - imx53_guf_vincell_init(fdt);
> + imx53_guf_vincell_init(is_lt);
> }
>
> -extern char __dtb_imx53_guf_vincell_start[];
> +ENTRY_FUNCTION(start_imx53_guf_vincell_lt, r0, r1, r2)
> +{
> + __imx53_guf_vincell_init(1);
> +}
>
> ENTRY_FUNCTION(start_imx53_guf_vincell, r0, r1, r2)
> {
> - void *fdt;
> -
> - fdt = __dtb_imx53_guf_vincell_start - get_runtime_offset();
> -
> - imx53_guf_vincell_init(fdt);
> + __imx53_guf_vincell_init(0);
> }
> --
> 2.8.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* Re: [PATCH] ARM: imx6: reset PLL2's PFD2 on i.MX6D
From: Lucas Stach @ 2016-09-14 9:51 UTC (permalink / raw)
To: Uwe Kleine-König; +Cc: barebox
In-Reply-To: <1473839813-11206-1-git-send-email-u.kleine-koenig@pengutronix.de>
Am Mittwoch, den 14.09.2016, 09:56 +0200 schrieb Uwe Kleine-König:
> The check for is_imx6q was introduced initially in
>
> f1f6d76370b3 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources")
>
> to differentiate between i.MX6DL+i.MX6SL and i.MX6Q. The i.MX6D must be
> handled like the latter, so drop the check. i.MX6DL+i.MX6SL can be
> ignored here since since
>
> a66596282413 ("imx6: lowlevel_init: Fix workaround for new i.MX6s chips")
>
> the PFD handling is only done for i.MX6DQ.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> arch/arm/mach-imx/imx6.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
> index ba8fb8964ac8..4391839a0b7e 100644
> --- a/arch/arm/mach-imx/imx6.c
> +++ b/arch/arm/mach-imx/imx6.c
> @@ -77,7 +77,7 @@ void imx6_init_lowlevel(void)
The comment right above this code block isn't reflecting reality anymore
after this change. Please fix it up.
Regards,
Lucas
> BM_ANADIG_PFD_480_PFD0_CLKGATE,
> MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
> writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
> - (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
> + BM_ANADIG_PFD_528_PFD2_CLKGATE |
> BM_ANADIG_PFD_528_PFD1_CLKGATE |
> BM_ANADIG_PFD_528_PFD0_CLKGATE,
> MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
> @@ -88,7 +88,7 @@ void imx6_init_lowlevel(void)
> BM_ANADIG_PFD_480_PFD0_CLKGATE,
> MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
> writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
> - (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
> + BM_ANADIG_PFD_528_PFD2_CLKGATE |
> BM_ANADIG_PFD_528_PFD1_CLKGATE |
> BM_ANADIG_PFD_528_PFD0_CLKGATE,
> MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
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^ permalink raw reply
* [PATCH v2] ARM: imx6: reset PLL2's PFD2 on i.MX6D
From: Uwe Kleine-König @ 2016-09-14 10:17 UTC (permalink / raw)
To: barebox
In-Reply-To: <1473846672.2243.39.camel@pengutronix.de>
The check for is_imx6q was introduced initially in
f1f6d76370b3 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources")
to differentiate between i.MX6DL+i.MX6SL and i.MX6Q. The i.MX6D must be
handled like the latter, so drop the check. i.MX6DL+i.MX6SL can be
ignored here since since
a66596282413 ("imx6: lowlevel_init: Fix workaround for new i.MX6s chips")
the PFD handling is only done for i.MX6DQ.
Update the comment to be not only logically correct but also helpful.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-imx/imx6.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb8964ac8..18509a7b51db 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -65,10 +65,10 @@ void imx6_init_lowlevel(void)
writel(0xffffffff, 0x020c407c);
writel(0xffffffff, 0x020c4080);
- /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
- * to make sure PFD is working right, otherwise, PFDs may
- * not output clock after reset, MX6DL and MX6SL have added 396M pfd
- * workaround in ROM code, as bus clock need it
+ /*
+ * Due to a hardware bug (related to errata ERR006282) on i.MX6DQ we
+ * need to gate/ungate all PFDs to make sure PFD is working right,
+ * otherwise PFDs may not output clock after reset.
*/
if (is_imx6q || is_imx6d) {
writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
@@ -77,7 +77,7 @@ void imx6_init_lowlevel(void)
BM_ANADIG_PFD_480_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+ BM_ANADIG_PFD_528_PFD2_CLKGATE |
BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
@@ -88,7 +88,7 @@ void imx6_init_lowlevel(void)
BM_ANADIG_PFD_480_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+ BM_ANADIG_PFD_528_PFD2_CLKGATE |
BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
--
2.8.1
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^ permalink raw reply related
* Re: [PATCH] ARM: imx6: reset PLL2's PFD2 on i.MX6D
From: Lucas Stach @ 2016-09-14 11:05 UTC (permalink / raw)
To: Uwe Kleine-König; +Cc: barebox
In-Reply-To: <1473846672.2243.39.camel@pengutronix.de>
Am Mittwoch, den 14.09.2016, 11:51 +0200 schrieb Lucas Stach:
> Am Mittwoch, den 14.09.2016, 09:56 +0200 schrieb Uwe Kleine-König:
> > The check for is_imx6q was introduced initially in
> >
> > f1f6d76370b3 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources")
> >
> > to differentiate between i.MX6DL+i.MX6SL and i.MX6Q. The i.MX6D must be
> > handled like the latter, so drop the check. i.MX6DL+i.MX6SL can be
> > ignored here since since
> >
> > a66596282413 ("imx6: lowlevel_init: Fix workaround for new i.MX6s chips")
> >
> > the PFD handling is only done for i.MX6DQ.
> >
> > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > ---
> > arch/arm/mach-imx/imx6.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
> > index ba8fb8964ac8..4391839a0b7e 100644
> > --- a/arch/arm/mach-imx/imx6.c
> > +++ b/arch/arm/mach-imx/imx6.c
> > @@ -77,7 +77,7 @@ void imx6_init_lowlevel(void)
>
> The comment right above this code block isn't reflecting reality anymore
> after this change. Please fix it up.
FTR: Please, disregard my comment. It's wrong and this patch is just
fine.
>
> > BM_ANADIG_PFD_480_PFD0_CLKGATE,
> > MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
> > writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
> > - (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
> > + BM_ANADIG_PFD_528_PFD2_CLKGATE |
> > BM_ANADIG_PFD_528_PFD1_CLKGATE |
> > BM_ANADIG_PFD_528_PFD0_CLKGATE,
> > MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
> > @@ -88,7 +88,7 @@ void imx6_init_lowlevel(void)
> > BM_ANADIG_PFD_480_PFD0_CLKGATE,
> > MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
> > writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
> > - (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
> > + BM_ANADIG_PFD_528_PFD2_CLKGATE |
> > BM_ANADIG_PFD_528_PFD1_CLKGATE |
> > BM_ANADIG_PFD_528_PFD0_CLKGATE,
> > MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
>
>
>
> _______________________________________________
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> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply
* Re: [PATCH] ARM: i.MX6: Enable parent propagation for clk_gate2
From: Sam Ravnborg @ 2016-09-14 11:11 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
In-Reply-To: <1473775689-8969-1-git-send-email-s.hauer@pengutronix.de>
Hi Sascha.
On Tue, Sep 13, 2016 at 04:08:09PM +0200, Sascha Hauer wrote:
> Enable parent rate propagation for clk_gate2 to allow the
> clock consumers to adjust their rates.
> One effect of this is that the i.MX6 NAND controller now can adjust
> its rate. It already called a clk_set_rate(rate, 96000000), but this
> had no effect, so the clock stayed at reset default 24MHz resulting
> in a rather slow timing. This became a problem when commit
> "1daa3bc mtd: nand_mxs: Setup timing" introduced EDO timing mode for
> faster NAND chips. EDO mode can only work properly for cycle times
> < 30ns (at least that's specified in the ONFI spec). 1daa3bc resulted
> in sporadic NAND read errors on some boards.
Nice work!
We have tested this patch on ~10 boards that failed
with DMA errors before.
None of these boards failed after applying this patch.
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Sam Ravnborg <sam@ravnborg.org>
Sam
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* Re: [PATCH] ARM: i.MX6: Enable parent propagation for clk_gate2
From: Sascha Hauer @ 2016-09-14 12:46 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: Barebox List
In-Reply-To: <20160914111114.GA15884@ravnborg.org>
On Wed, Sep 14, 2016 at 01:11:14PM +0200, Sam Ravnborg wrote:
> Hi Sascha.
>
> On Tue, Sep 13, 2016 at 04:08:09PM +0200, Sascha Hauer wrote:
> > Enable parent rate propagation for clk_gate2 to allow the
> > clock consumers to adjust their rates.
> > One effect of this is that the i.MX6 NAND controller now can adjust
> > its rate. It already called a clk_set_rate(rate, 96000000), but this
> > had no effect, so the clock stayed at reset default 24MHz resulting
> > in a rather slow timing. This became a problem when commit
> > "1daa3bc mtd: nand_mxs: Setup timing" introduced EDO timing mode for
> > faster NAND chips. EDO mode can only work properly for cycle times
> > < 30ns (at least that's specified in the ONFI spec). 1daa3bc resulted
> > in sporadic NAND read errors on some boards.
>
> Nice work!
>
> We have tested this patch on ~10 boards that failed
> with DMA errors before.
> None of these boards failed after applying this patch.
Great :)
Have you noticed the NAND is much faster now?
Sascha
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