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* [PATCH 1/2] fixup! watchdog: add designware driver
From: Steffen Trumtrar @ 2016-11-01  9:52 UTC (permalink / raw)
  To: barebox; +Cc: Steffen Trumtrar

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/watchdog/dw_wdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
index fa2752896c2f..8fd8c81e6c38 100644
--- a/drivers/watchdog/dw_wdt.c
+++ b/drivers/watchdog/dw_wdt.c
@@ -151,7 +151,7 @@ static int dw_wdt_drv_probe(struct device_d *dev)
 	if (ret)
 		return ret;
 
-	dw_wdt->rst = reset_control_get(dev, "dw-wdt");
+	dw_wdt->rst = reset_control_get(dev, NULL);
 	if (IS_ERR(dw_wdt->rst))
 		dev_warn(dev, "No reset lines. Will not be able to stop once started.\n");
 
-- 
2.10.1


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* [PATCH 2/2] fixup! ARM: socfpga: dtsi: add dw-wdt reset lines
From: Steffen Trumtrar @ 2016-11-01  9:52 UTC (permalink / raw)
  To: barebox; +Cc: Steffen Trumtrar
In-Reply-To: <20161101095227.2087-1-s.trumtrar@pengutronix.de>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 arch/arm/dts/socfpga.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 66d7f21dc6a3..5b141c23914c 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -52,10 +52,8 @@
 
 &watchdog0 {
 	resets = <&rst L4WD0_RESET>;
-	reset-names = "dw-wdt";
 };
 
 &watchdog1 {
 	resets = <&rst L4WD1_RESET>;
-	reset-names = "dw-wdt";
 };
-- 
2.10.1


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* [PATCH 1/5] PCI: add some useful debug output
From: Lucas Stach @ 2016-11-01  8:58 UTC (permalink / raw)
  To: barebox

This makes diagnosing problems in address space allocation
much easier.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/pci.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 191561da0368..46f5d5f7de36 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -179,6 +179,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 				pr_debug("BAR does not fit within bus IO res\n");
 				return;
 			}
+			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_io);
 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
 			dev->resource[bar].flags = IORESOURCE_IO;
 			last_addr = last_io;
@@ -197,6 +198,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 				pr_debug("BAR does not fit within bus p-mem res\n");
 				return;
 			}
+			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem_pref);
 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem_pref);
 			dev->resource[bar].flags = IORESOURCE_MEM |
 			                           IORESOURCE_PREFETCH;
@@ -215,6 +217,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 				pr_debug("BAR does not fit within bus np-mem res\n");
 				return;
 			}
+			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem);
 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
 			dev->resource[bar].flags = IORESOURCE_MEM;
 			last_addr = last_mem;
@@ -286,18 +289,21 @@ static void postscan_setup_bridge(struct pci_dev *dev)
 
 	if (last_mem) {
 		last_mem = ALIGN(last_mem, SZ_1M);
+		pr_debug("bridge NP limit at 0x%08x\n", last_mem);
 		pci_write_config_word(dev, PCI_MEMORY_LIMIT,
 				      ((last_mem - 1) & 0xfff00000) >> 16);
 	}
 
 	if (last_mem_pref) {
 		last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
+		pr_debug("bridge P limit at 0x%08x\n", last_mem_pref);
 		pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
 				      ((last_mem_pref - 1) & 0xfff00000) >> 16);
 	}
 
 	if (last_io) {
 		last_io = ALIGN(last_io, SZ_4K);
+		pr_debug("bridge IO limit at 0x%08x\n", last_io);
 		pci_write_config_byte(dev, PCI_IO_LIMIT,
 				((last_io - 1) & 0x0000f000) >> 8);
 		pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
-- 
2.10.1


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* [PATCH 5/5] PCI: split PCI hierarchy enumeration and config from device registration
From: Lucas Stach @ 2016-11-01  8:58 UTC (permalink / raw)
  To: barebox
In-Reply-To: <20161101085855.953-1-l.stach@pengutronix.de>

This gets rid of some of the special cases in the bus scanning function
by splitting hierarchy enumeration and configuration and the actual
device registration into 2 passes.

This ensures that the PCI hierarchy below a root port is completely
set up before any device driver is probed.

This simplifies the code and makes it less error prone, while moving
the PCI address space layout closer to the one used by Linux.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/pci.c | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 12aafccde578..b2570eb15181 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -28,6 +28,20 @@ static struct pci_bus *pci_alloc_bus(void)
 	return b;
 }
 
+static void pci_bus_register_devices(struct pci_bus *bus)
+{
+	struct pci_dev *dev;
+	struct pci_bus *child_bus;
+
+	/* activate all devices on this bus */
+	list_for_each_entry(dev, &bus->devices, bus_list)
+		pci_register_device(dev);
+
+	/* walk down the hierarchy */
+	list_for_each_entry(child_bus, &bus->children, node)
+		pci_bus_register_devices(child_bus);
+}
+
 void register_pci_controller(struct pci_controller *hose)
 {
 	struct pci_bus *bus;
@@ -64,6 +78,7 @@ void register_pci_controller(struct pci_controller *hose)
 		last_io = 0;
 
 	pci_scan_bus(bus);
+	pci_bus_register_devices(bus);
 
 	list_add_tail(&bus->node, &pci_root_buses);
 
@@ -384,16 +399,8 @@ unsigned int pci_scan_bus(struct pci_bus *bus)
 			dev->rom_address = (l == 0xffffffff) ? 0 : l;
 
 			setup_device(dev, 6);
-			/*
-			 * If this device is on the root bus, there is no bridge
-			 * to configure, so we can activate it right away.
-			 */
-			if (!bus->parent_bus)
-				pci_register_device(dev);
 			break;
 		case PCI_HEADER_TYPE_BRIDGE:
-			setup_device(dev, 2);
-
 			child_bus = pci_alloc_bus();
 			/* inherit parent properties */
 			child_bus->host = bus->host;
@@ -412,18 +419,12 @@ unsigned int pci_scan_bus(struct pci_bus *bus)
 			list_add_tail(&child_bus->node, &bus->children);
 			dev->subordinate = child_bus;
 
-			/* activate bridge device */
-			pci_register_device(dev);
-
 			/* scan pci hierarchy behind bridge */
 			prescan_setup_bridge(dev);
 			pci_scan_bus(child_bus);
 			postscan_setup_bridge(dev);
 
-			/* finally active all devices behind the bridge */
-			list_for_each_entry(dev, &child_bus->devices, bus_list)
-				if (!dev->subordinate)
-					pci_register_device(dev);
+			setup_device(dev, 2);
 			break;
 		default:
 		bad:
-- 
2.10.1


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* [PATCH 3/5] PCI: align address range before scanning bridge
From: Lucas Stach @ 2016-11-01  8:58 UTC (permalink / raw)
  To: barebox
In-Reply-To: <20161101085855.953-1-l.stach@pengutronix.de>

Otherwise we may end up with a too low base address and push
requests for the upstream bus onto the downstream side.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/pci.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index eb3ce0f3211a..19cda1f145bc 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -252,6 +252,7 @@ static void prescan_setup_bridge(struct pci_dev *dev)
 
 	if (last_mem) {
 		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
+		last_mem = ALIGN(last_mem, SZ_1M);
 		pci_write_config_word(dev, PCI_MEMORY_BASE,
 				      (last_mem & 0xfff00000) >> 16);
 		cmdstat |= PCI_COMMAND_MEMORY;
@@ -259,6 +260,7 @@ static void prescan_setup_bridge(struct pci_dev *dev)
 
 	if (last_mem_pref) {
 		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
+		last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
 		pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,
 				      (last_mem_pref & 0xfff00000) >> 16);
 		cmdstat |= PCI_COMMAND_MEMORY;
@@ -270,6 +272,7 @@ static void prescan_setup_bridge(struct pci_dev *dev)
 	}
 
 	if (last_io) {
+		last_io = ALIGN(last_io, SZ_4K);
 		pci_write_config_byte(dev, PCI_IO_BASE,
 				      (last_io & 0x0000f000) >> 8);
 		pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
-- 
2.10.1


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* [PATCH 4/5] PCI: align BAR address to BAR size
From: Lucas Stach @ 2016-11-01  8:58 UTC (permalink / raw)
  To: barebox
In-Reply-To: <20161101085855.953-1-l.stach@pengutronix.de>

PCI BARs require their address to be at least aligned to their
size, otherwise address decoding will fail as the base address
gets rounded down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/pci.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 19cda1f145bc..12aafccde578 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -174,11 +174,12 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 				continue;
 			}
 			pr_debug("pbar%d: mask=%08x io %d bytes\n", bar, mask, size);
-			if (last_io + size >
+			if (ALIGN(last_io, size) + size >
 			    dev->bus->resource[PCI_BUS_RESOURCE_IO]->end) {
 				pr_debug("BAR does not fit within bus IO res\n");
 				return;
 			}
+			last_io = ALIGN(last_io, size);
 			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_io);
 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
 			dev->resource[bar].flags = IORESOURCE_IO;
@@ -193,11 +194,12 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 			}
 			pr_debug("pbar%d: mask=%08x P memory %d bytes\n",
 			    bar, mask, size);
-			if (last_mem_pref + size >
+			if (ALIGN(last_mem_pref, size) + size >
 			    dev->bus->resource[PCI_BUS_RESOURCE_MEM_PREF]->end) {
 				pr_debug("BAR does not fit within bus p-mem res\n");
 				return;
 			}
+			last_mem_pref = ALIGN(last_mem_pref, size);
 			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem_pref);
 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem_pref);
 			dev->resource[bar].flags = IORESOURCE_MEM |
@@ -212,11 +214,12 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 			}
 			pr_debug("pbar%d: mask=%08x NP memory %d bytes\n",
 			    bar, mask, size);
-			if (last_mem + size >
+			if (ALIGN(last_mem, size) + size >
 			    dev->bus->resource[PCI_BUS_RESOURCE_MEM]->end) {
 				pr_debug("BAR does not fit within bus np-mem res\n");
 				return;
 			}
+			last_mem = ALIGN(last_mem, size);
 			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem);
 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
 			dev->resource[bar].flags = IORESOURCE_MEM;
-- 
2.10.1


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* [PATCH 2/5] PCI: only check specific flag for 64bit BAR
From: Lucas Stach @ 2016-11-01  8:58 UTC (permalink / raw)
  To: barebox
In-Reply-To: <20161101085855.953-1-l.stach@pengutronix.de>

The memory type may include other flags, so just check for
the 64bit allocation flag to see if the BAR is a 64bit one.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/pci.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 46f5d5f7de36..eb3ce0f3211a 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -227,8 +227,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 		dev->resource[bar].start = last_addr;
 		dev->resource[bar].end = last_addr + size - 1;
 
-		if ((mask & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
-		    PCI_BASE_ADDRESS_MEM_TYPE_64) {
+		if ((mask & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 			dev->resource[bar].flags |= IORESOURCE_MEM_64;
 			pci_write_config_dword(dev,
 			       PCI_BASE_ADDRESS_1 + bar * 4, 0);
-- 
2.10.1


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* [PATCH] net: e1000: set edev parent pointer
From: Lucas Stach @ 2016-11-01  8:57 UTC (permalink / raw)
  To: barebox

This way the ethernet device will show up at the correct point
in the device hierarchy.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/net/e1000/main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/e1000/main.c b/drivers/net/e1000/main.c
index 77bcd179a824..6f9dddaf232a 100644
--- a/drivers/net/e1000/main.c
+++ b/drivers/net/e1000/main.c
@@ -3600,6 +3600,7 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	e1000_get_ethaddr(edev, edev->ethaddr);
 
 	/* Set up the function pointers and register the device */
+	edev->parent = &pdev->dev;
 	edev->init = e1000_init;
 	edev->recv = e1000_poll;
 	edev->send = e1000_transmit;
-- 
2.10.1


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* [PATCH] ARM: riotboard: fix barebox partition size
From: Lucas Stach @ 2016-10-31 21:20 UTC (permalink / raw)
  To: barebox

This was missed when updating all the partition sizes. The
environment partition has been moved to the correct location,
but the barebox partition size remained unchanged.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/dts/imx6s-riotboard.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx6s-riotboard.dts b/arch/arm/dts/imx6s-riotboard.dts
index 7193f28..5758872 100644
--- a/arch/arm/dts/imx6s-riotboard.dts
+++ b/arch/arm/dts/imx6s-riotboard.dts
@@ -29,7 +29,7 @@
 
 	partition@0 {
 		label = "barebox";
-		reg = <0x0 0x80000>;
+		reg = <0x0 0xe0000>;
 	};
 
 	environment_usdhc4: partition@e0000 {
-- 
2.7.4


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* [PATCH v2] net: e1000: fix i210 register remapping
From: Lucas Stach @ 2016-10-31 16:58 UTC (permalink / raw)
  To: barebox

Don't mask out the remapping flag before checking the register offset,
otherwise none of the switch statements will ever match.

Fixes: ff6a64d42ffc (e1000: Consolidate register offset fixups)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2: don't break it the other way around
---
 drivers/net/e1000/regio.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/net/e1000/regio.c b/drivers/net/e1000/regio.c
index b2e9d7b6a7df..1610d5851f05 100644
--- a/drivers/net/e1000/regio.c
+++ b/drivers/net/e1000/regio.c
@@ -5,8 +5,6 @@
 static uint32_t e1000_true_offset(struct e1000_hw *hw, uint32_t reg)
 {
 	if (reg & E1000_MIGHT_BE_REMAPPED) {
-		reg &= ~E1000_MIGHT_BE_REMAPPED;
-
 		if (hw->mac_type == e1000_igb) {
 			switch (reg) {
 			case E1000_EEWR:
@@ -19,7 +17,8 @@ static uint32_t e1000_true_offset(struct e1000_hw *hw, uint32_t reg)
 				reg = E1000_I210_EEMNGCTL;
 				break;
 			}
-		};
+		}
+		reg &= ~E1000_MIGHT_BE_REMAPPED;
 	}
 
 	return reg;
-- 
2.10.1


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* [PATCH] net: e1000: fix i210 register remapping
From: Lucas Stach @ 2016-10-31 16:55 UTC (permalink / raw)
  To: barebox

Don't mask out the remapping flag before checking the register offset,
otherwise none of the switch statements will ever match.

Fixes: ff6a64d42ffc (e1000: Consolidate register offset fixups)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/net/e1000/regio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/e1000/regio.c b/drivers/net/e1000/regio.c
index b2e9d7b6a7df..17d08da3b8a2 100644
--- a/drivers/net/e1000/regio.c
+++ b/drivers/net/e1000/regio.c
@@ -5,8 +5,6 @@
 static uint32_t e1000_true_offset(struct e1000_hw *hw, uint32_t reg)
 {
 	if (reg & E1000_MIGHT_BE_REMAPPED) {
-		reg &= ~E1000_MIGHT_BE_REMAPPED;
-
 		if (hw->mac_type == e1000_igb) {
 			switch (reg) {
 			case E1000_EEWR:
@@ -19,7 +17,9 @@ static uint32_t e1000_true_offset(struct e1000_hw *hw, uint32_t reg)
 				reg = E1000_I210_EEMNGCTL;
 				break;
 			}
-		};
+		} else {
+			reg &= ~E1000_MIGHT_BE_REMAPPED;
+		}
 	}
 
 	return reg;
-- 
2.10.1


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* Re: [PATCH v3 3/3] ARM: socfpga: dtsi: add dw-wdt reset lines
From: Sascha Hauer @ 2016-10-28  7:20 UTC (permalink / raw)
  To: Steffen Trumtrar; +Cc: barebox@lists.infradead.org, Trent Piepho
In-Reply-To: <20161027065856.tn4tdwtev5aexxyg@pengutronix.de>

On Thu, Oct 27, 2016 at 08:58:56AM +0200, Steffen Trumtrar wrote:
> On Wed, Oct 26, 2016 at 08:12:07PM +0000, Trent Piepho wrote:
> > On Mon, 2016-10-17 at 09:50 +0200, Steffen Trumtrar wrote:
> > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> > > ---
> > >  arch/arm/dts/socfpga.dtsi | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> > > index d16758fdab46..66d7f21dc6a3 100644
> > > --- a/arch/arm/dts/socfpga.dtsi
> > > +++ b/arch/arm/dts/socfpga.dtsi
> > > @@ -49,3 +49,13 @@
> > >  &f2s_sdram_ref_clk {
> > >  	clock-frequency = <0>;
> > >  };
> > > +
> > > +&watchdog0 {
> > > +	resets = <&rst L4WD0_RESET>;
> > > +	reset-names = "dw-wdt";
> > 
> > This is the official binding?  The reset-names property is supposed to
> > be the name of the reset from the perspective of the device being
> > described, e.g. the watchdog.  Not the name from the perspective of the
> > reset controller.  Rather than "dw-wdt", the name should something like
> > "reset", which clearly doesn't add much information, which is why the
> > reset-names property is supposed to be optional.
> > 
> 
> There is no "official" binding. I wasn't really sure about this property
> and just tried to derive from other bindings. I don't care for this one,
> so I'm okay with removing it.

Could you send a fixup patch for this?

Sascha

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* Re: [PATCH v2] ARM: dts: am33xx.dtsi: Add spi aliases
From: Sascha Hauer @ 2016-10-28  6:53 UTC (permalink / raw)
  To: Teresa Remmet; +Cc: barebox
In-Reply-To: <1477298184-32928-1-git-send-email-t.remmet@phytec.de>

On Mon, Oct 24, 2016 at 10:36:24AM +0200, Teresa Remmet wrote:
> We need to add the spi aliases to set the bus number correct in
> the driver.
> 
> Delete the spi1 alias again in the am33xx-strip.dtsi for MLO as
> the node is deleted there also.
> 
> Signed-off-by: Teresa Remmet <t.remmet@phytec.de>

Applied, thanks

Sascha

> ---
> Changes in v2:
> - Removed the first patch completly
> - Delete now spi1 alias in strip file
> - Updated commit message
> 
>  arch/arm/dts/am33xx-strip.dtsi | 1 +
>  arch/arm/dts/am33xx.dtsi       | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/arch/arm/dts/am33xx-strip.dtsi b/arch/arm/dts/am33xx-strip.dtsi
> index 2943fd1..83d23a8 100644
> --- a/arch/arm/dts/am33xx-strip.dtsi
> +++ b/arch/arm/dts/am33xx-strip.dtsi
> @@ -14,6 +14,7 @@
>  		/delete-property/ mmc2;
>  		/delete-property/ d_can0;
>  		/delete-property/ d_can1;
> +		/delete-property/ spi1;
>  	};
>  };
>  
> diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
> index 7ba0a0b..f1ee7b3 100644
> --- a/arch/arm/dts/am33xx.dtsi
> +++ b/arch/arm/dts/am33xx.dtsi
> @@ -18,5 +18,7 @@
>  		mmc0 = &mmc1;
>  		mmc1 = &mmc2;
>  		mmc2 = &mmc3;
> +		spi0 = &spi0;
> +		spi1 = &spi1;
>  	};
>  };
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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* Re: Read kernel from static UBI volume
From: Sascha Hauer @ 2016-10-27  7:39 UTC (permalink / raw)
  To: Guillermo Rodriguez Garcia; +Cc: barebox
In-Reply-To: <CABDcava4zzJBLtku87=bmp5PdYy0TMejDgTpsoP8Z2zB5vQV-Q@mail.gmail.com>

On Thu, Oct 27, 2016 at 09:34:20AM +0200, Guillermo Rodriguez Garcia wrote:
> 2016-10-27 9:31 GMT+02:00 Sascha Hauer <s.hauer@pengutronix.de>:
> > On Thu, Oct 27, 2016 at 09:10:02AM +0200, Guillermo Rodriguez Garcia wrote:
> >> Hello all,
> >>
> >> I know Barebox can load files from UBIFS. However, is there support
> >> from booting a kernel directly from a static UBI volume?.
> >
> > bootm /dev/nand0.ubi.whatever should do.
> 
> That easy?
> 
> This is one of the reasons why I like barebox so much better than u-boot..
> 
> I assume this will just read the whole volume (as opposed to checking
> the zImage size and so on). Correct?

The bootm code only reads the actual image size.

> 
> Also will this do the UBI static volume CRC check?

You read a UBI volume using the UBI code which is more or less identical
to the Kernel, so I'd assume the code does whatever is necessary,
including the crc check.
I'm speaking a bit nebulous because I never used static UBI volumes
myself.

Sascha

-- 
Pengutronix e.K.                           |                             |
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Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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* Re: Read kernel from static UBI volume
From: Guillermo Rodriguez Garcia @ 2016-10-27  7:34 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20161027073157.u6jmv6ux3xs4x46i@pengutronix.de>

2016-10-27 9:31 GMT+02:00 Sascha Hauer <s.hauer@pengutronix.de>:
> On Thu, Oct 27, 2016 at 09:10:02AM +0200, Guillermo Rodriguez Garcia wrote:
>> Hello all,
>>
>> I know Barebox can load files from UBIFS. However, is there support
>> from booting a kernel directly from a static UBI volume?.
>
> bootm /dev/nand0.ubi.whatever should do.

That easy?

This is one of the reasons why I like barebox so much better than u-boot..

I assume this will just read the whole volume (as opposed to checking
the zImage size and so on). Correct?

Also will this do the UBI static volume CRC check?

Guillermo Rodriguez Garcia
guille.rodriguez@gmail.com

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* Re: Read kernel from static UBI volume
From: Sascha Hauer @ 2016-10-27  7:31 UTC (permalink / raw)
  To: Guillermo Rodriguez Garcia; +Cc: barebox
In-Reply-To: <CABDcavZ08eW8scP2zi_5hUp7J8ex-xj17-n7SRx_5YNC3q-8eQ@mail.gmail.com>

On Thu, Oct 27, 2016 at 09:10:02AM +0200, Guillermo Rodriguez Garcia wrote:
> Hello all,
> 
> I know Barebox can load files from UBIFS. However, is there support
> from booting a kernel directly from a static UBI volume?.

bootm /dev/nand0.ubi.whatever should do.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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* Re: Read kernel from static UBI volume
From: Guillermo Rodriguez Garcia @ 2016-10-27  7:29 UTC (permalink / raw)
  To: Uwe Kleine-König; +Cc: barebox
In-Reply-To: <20161027071810.g7web5cjygjqnus5@pengutronix.de>

Hello,

2016-10-27 9:18 GMT+02:00 Uwe Kleine-König <u.kleine-koenig@pengutronix.de>:
> On Thu, Oct 27, 2016 at 09:10:02AM +0200, Guillermo Rodriguez Garcia wrote:
>> I know Barebox can load files from UBIFS. However, is there support
>> from booting a kernel directly from a static UBI volume?.
>
> Are you using ptxdist? If so, enable BLSPEC which results in the kernel
> being installed (together with a dtb if configured) in the rootfs and
> barebox can boot this easily.

Yes, but this is not what I want: I want to be able to read a kernel
from a static UBI volume, not from the rootfs. Is this possible ?

Guillermo Rodriguez Garcia
guille.rodriguez@gmail.com

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* Re: Read kernel from static UBI volume
From: Uwe Kleine-König @ 2016-10-27  7:18 UTC (permalink / raw)
  To: Guillermo Rodriguez Garcia; +Cc: barebox
In-Reply-To: <CABDcavZ08eW8scP2zi_5hUp7J8ex-xj17-n7SRx_5YNC3q-8eQ@mail.gmail.com>

On Thu, Oct 27, 2016 at 09:10:02AM +0200, Guillermo Rodriguez Garcia wrote:
> I know Barebox can load files from UBIFS. However, is there support
> from booting a kernel directly from a static UBI volume?.

Are you using ptxdist? If so, enable BLSPEC which results in the kernel
being installed (together with a dtb if configured) in the rootfs and
barebox can boot this easily.

Best regards
Uwe

-- 
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* Read kernel from static UBI volume
From: Guillermo Rodriguez Garcia @ 2016-10-27  7:10 UTC (permalink / raw)
  To: barebox

Hello all,

I know Barebox can load files from UBIFS. However, is there support
from booting a kernel directly from a static UBI volume?.

Thanks,

Guillermo Rodriguez Garcia
guille.rodriguez@gmail.com

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* Re: [PATCH v3 3/3] ARM: socfpga: dtsi: add dw-wdt reset lines
From: Steffen Trumtrar @ 2016-10-27  6:58 UTC (permalink / raw)
  To: Trent Piepho; +Cc: barebox@lists.infradead.org
In-Reply-To: <1477512729.14501.14.camel@rtred1test09.kymeta.local>

On Wed, Oct 26, 2016 at 08:12:07PM +0000, Trent Piepho wrote:
> On Mon, 2016-10-17 at 09:50 +0200, Steffen Trumtrar wrote:
> > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> > ---
> >  arch/arm/dts/socfpga.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> > index d16758fdab46..66d7f21dc6a3 100644
> > --- a/arch/arm/dts/socfpga.dtsi
> > +++ b/arch/arm/dts/socfpga.dtsi
> > @@ -49,3 +49,13 @@
> >  &f2s_sdram_ref_clk {
> >  	clock-frequency = <0>;
> >  };
> > +
> > +&watchdog0 {
> > +	resets = <&rst L4WD0_RESET>;
> > +	reset-names = "dw-wdt";
> 
> This is the official binding?  The reset-names property is supposed to
> be the name of the reset from the perspective of the device being
> described, e.g. the watchdog.  Not the name from the perspective of the
> reset controller.  Rather than "dw-wdt", the name should something like
> "reset", which clearly doesn't add much information, which is why the
> reset-names property is supposed to be optional.
> 

There is no "official" binding. I wasn't really sure about this property
and just tried to derive from other bindings. I don't care for this one,
so I'm okay with removing it.

Thanks,
Steffen

-- 
Pengutronix e.K.                           |                             |
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Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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* Re: [PATCH v3 3/3] ARM: socfpga: dtsi: add dw-wdt reset lines
From: Trent Piepho @ 2016-10-26 20:12 UTC (permalink / raw)
  To: Steffen Trumtrar; +Cc: barebox@lists.infradead.org
In-Reply-To: <20161017075052.30802-3-s.trumtrar@pengutronix.de>

On Mon, 2016-10-17 at 09:50 +0200, Steffen Trumtrar wrote:
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
>  arch/arm/dts/socfpga.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index d16758fdab46..66d7f21dc6a3 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -49,3 +49,13 @@
>  &f2s_sdram_ref_clk {
>  	clock-frequency = <0>;
>  };
> +
> +&watchdog0 {
> +	resets = <&rst L4WD0_RESET>;
> +	reset-names = "dw-wdt";

This is the official binding?  The reset-names property is supposed to
be the name of the reset from the perspective of the device being
described, e.g. the watchdog.  Not the name from the perspective of the
reset controller.  Rather than "dw-wdt", the name should something like
"reset", which clearly doesn't add much information, which is why the
reset-names property is supposed to be optional.

> +};
> +
> +&watchdog1 {
> +	resets = <&rst L4WD1_RESET>;
> +	reset-names = "dw-wdt";
> +};

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* Re: [PATCH 4/4] mci: add MBR write and read function to block devices
From: Michael Grzeschik @ 2016-10-26  9:40 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20161026090933.qdzlqhv4blwx5idq@pengutronix.de>

On Wed, Oct 26, 2016 at 11:09:33AM +0200, Michael Grzeschik wrote:
> On Tue, Oct 18, 2016 at 08:23:22AM +0200, Sascha Hauer wrote:
> > On Mon, Oct 17, 2016 at 03:29:23PM +0200, Michael Grzeschik wrote:
> > > With this patch it is possible to write an mbr partition table to the
> > > mci block device. By setting the device property "dos_partitions" of the
> > > mmc device node, it is possible to write back the new partition layout
> > > in the common cmdlinepart notation. The property can also be read back.
> > > 
> > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> > > ---
> > >  drivers/mci/mci-core.c | 122 +++++++++++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 122 insertions(+)
> > > 
> > > diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
> > > index 4e176f7..c0013a1 100644
> > > --- a/drivers/mci/mci-core.c
> > > +++ b/drivers/mci/mci-core.c
> > > @@ -33,9 +33,11 @@
> > >  #include <asm-generic/div64.h>
> > >  #include <asm/byteorder.h>
> > >  #include <block.h>
> > > +#include <fcntl.h>
> > >  #include <disks.h>
> > >  #include <of.h>
> > >  #include <linux/err.h>
> > > +#include <cmdlinepart.h>
> > >  
> > >  #define MAX_BUFFER_NUMBER 0xffffffff
> > >  
> > > @@ -1527,6 +1529,122 @@ static void mci_info(struct device_d *dev)
> > >  		extract_mtd_year(mci));
> > >  }
> > >  
> > > +static char *print_size(uint64_t s)
> > > +{
> > > +	if (!(s & ((1 << 20) - 1)))
> > > +		return basprintf("%lldM", s >> 20);
> > > +	if (!(s & ((1 << 10) - 1)))
> > > +		return basprintf("%lldk", s >> 10);
> > > +	return basprintf("0x%lld", s);
> > 
> > s/lld/llx/
> 
> Why that? This will break the typical layout compared
> to all other users of the kernelcmdline syntax.

As I now realize you only ment the last line, this sure makes
sense. I will fix it. But the mtd layer I copied this from
has the same issue. Will fix that aswell.

Thanks,
Michael

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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* Re: [PATCH 3/4] partitions/dos: add function to write partition table
From: Michael Grzeschik @ 2016-10-26  9:12 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20161018060712.kqtkwxx73to6m434@pengutronix.de>

On Tue, Oct 18, 2016 at 08:07:12AM +0200, Sascha Hauer wrote:
> Hi Michael,
> 
> On Mon, Oct 17, 2016 at 03:29:22PM +0200, Michael Grzeschik wrote:
> > The function can be used to write an partition layout to the block device
> > based on its cdev layout. Only cdevs with flag DEVFS_PARTITION_IN_PT set
> > get written. The function also adds an static offset of 0x200000 to
> > ensure the mbr and bootloader will not be overwritten.
> > 
> > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> > ---
> >  common/partitions/dos.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++
> >  include/disks.h         |  1 +
> >  2 files changed, 72 insertions(+)
> > 
> > diff --git a/common/partitions/dos.c b/common/partitions/dos.c
> > index 5f08e25..d7fa538 100644
> > --- a/common/partitions/dos.c
> > +++ b/common/partitions/dos.c
> > @@ -256,6 +256,77 @@ static void dos_partition(void *buf, struct block_device *blk,
> >  			&dsp->signature, "%08x", dsp);
> >  }
> >  
> > +static inline void hdimage_setup_chs(unsigned int lba, unsigned char *chs)
> > +{
> > +	const unsigned int hpc = 255;
> > +	const unsigned int spt = 63;
> > +	unsigned int s, c;
> > +
> > +	chs[0] = (lba/spt)%hpc;
> 
> Please run checkpatch over this. There are some stylistic flaws like
> missing whitespaces left and right of operators.

Thanks. I forgot to do that. It was an badly formatet template I used
here for reference. Will fix it.

> > +	c = (lba/(spt * hpc));
> > +	s = (lba > 0) ?(lba%spt + 1) : 0;
> > +	chs[1] = ((c & 0x300) >> 2) | (s & 0xff);
> > +	chs[2] = (c & 0xff);
> > +}
> > +
> > +int write_dos_partition_table(struct block_device *blk, struct list_head *cdevs)
> > +{
> > +	char part_table[6+4*sizeof(struct partition_entry)+2];
> > +	struct cdev *cdev, *ct;
> > +	void *buf;
> > +	int ret;
> > +	int n = 0;
> > +	char *ptr;
> > +
> > +	/* prepare partition table entry */
> > +	ptr = part_table;
> > +	memset(ptr, 0, sizeof(part_table));
> > +
> > +	/* skip disk signature */
> > +	ptr += 6;
> 
> It's even more important to skip this in the output buffer. This code
> should not change the disk signature.
> 
> > +	list_for_each_entry_safe(cdev, ct, cdevs, devices_list) {
> 
> Why _safe? You do not remove entries, do you?

No elements get changed in the iteration. I will change it.

> > +		if ((cdev->flags & DEVFS_IS_PARTITION) &&
> > +			(cdev->flags & DEVFS_PARTITION_IN_PT)) {
> 
> In a multiline if clause the second line should either start directly
> under the opening brace or indented with at least two more tabs than the
> opening if(), but using the same indention level as the conditional code
> makes it hard to read.

Will be changed.

> 
> > +			struct partition_entry *entry;
> 
> Instead of the silent test below, do a:
> 
> 			if (n == 4) {
> 				pr_warn("Only 4 partitions written to MBR\n");
> 				break;
> 			}
> 

Good thought. Will change.


> > +			entry = (struct partition_entry *)
> > +				(ptr + n * sizeof(struct partition_entry));
> > +
> > +			/* add static offset to skip the mbr and bootloader */
> > +			cdev->offset += 4096 * SECTOR_SIZE;
> > +
> > +			entry->type = 0x83;
> > +			entry->partition_start = cdev->offset / SECTOR_SIZE;
> > +			entry->partition_size = cdev->size / SECTOR_SIZE;
> 
> We should have a test if offset and/or size exceed the 32bit limit.
> 

Good point. Will add in v2.

> > +
> > +			hdimage_setup_chs(entry->partition_start,
> > +						entry->chs_begin);
> > +			hdimage_setup_chs(entry->partition_start +
> > +						entry->partition_size - 1,
> > +						entry->chs_end);
> > +			n++;
> > +		}
> > +		if (n == 4)
> > +			break;
> > +	}
> > +
> > +	ptr += 4 * sizeof(struct partition_entry);
> > +	ptr[0] = 0x55;
> > +	ptr[1] = 0xaa;
> > +
> > +	buf = read_mbr(blk);
> > +	if (!buf)
> > +		return -EIO;
> 
> You could move this to the top of the function and directly manipulate
> the input buffer.

Already prepared for v2.

Thanks,
Michael

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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* Re: [PATCH 4/4] mci: add MBR write and read function to block devices
From: Michael Grzeschik @ 2016-10-26  9:09 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox
In-Reply-To: <20161018062322.wje6gucvkt42v7oa@pengutronix.de>

On Tue, Oct 18, 2016 at 08:23:22AM +0200, Sascha Hauer wrote:
> On Mon, Oct 17, 2016 at 03:29:23PM +0200, Michael Grzeschik wrote:
> > With this patch it is possible to write an mbr partition table to the
> > mci block device. By setting the device property "dos_partitions" of the
> > mmc device node, it is possible to write back the new partition layout
> > in the common cmdlinepart notation. The property can also be read back.
> > 
> > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> > ---
> >  drivers/mci/mci-core.c | 122 +++++++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 122 insertions(+)
> > 
> > diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
> > index 4e176f7..c0013a1 100644
> > --- a/drivers/mci/mci-core.c
> > +++ b/drivers/mci/mci-core.c
> > @@ -33,9 +33,11 @@
> >  #include <asm-generic/div64.h>
> >  #include <asm/byteorder.h>
> >  #include <block.h>
> > +#include <fcntl.h>
> >  #include <disks.h>
> >  #include <of.h>
> >  #include <linux/err.h>
> > +#include <cmdlinepart.h>
> >  
> >  #define MAX_BUFFER_NUMBER 0xffffffff
> >  
> > @@ -1527,6 +1529,122 @@ static void mci_info(struct device_d *dev)
> >  		extract_mtd_year(mci));
> >  }
> >  
> > +static char *print_size(uint64_t s)
> > +{
> > +	if (!(s & ((1 << 20) - 1)))
> > +		return basprintf("%lldM", s >> 20);
> > +	if (!(s & ((1 << 10) - 1)))
> > +		return basprintf("%lldk", s >> 10);
> > +	return basprintf("0x%lld", s);
> 
> s/lld/llx/

Why that? This will break the typical layout compared
to all other users of the kernelcmdline syntax.

> > +}
> > +
> > +static int print_part(char *buf, int bufsize, struct cdev *cdev, int is_last)
> > +{
> > +	char *size = print_size(cdev->size);
> > +	int ret;
> > +
> > +	if (!size) {
> > +		ret = -ENOMEM;
> > +		goto out;
> > +	}
> > +
> > +	ret = snprintf(buf, bufsize, "%s(%s)%s", size,
> > +			cdev->partname,
> > +			is_last ? "" : ",");
> > +out:
> > +	free(size);
> > +
> > +	return ret;
> > +}
> > +
> > +static int print_parts(char *buf, int bufsize, struct mci *mci)
> > +{
> > +	struct cdev *cdev, *ct;
> > +	int ret = 0;
> > +
> > +	list_for_each_entry_safe(cdev, ct, &mci->dev.cdevs, devices_list) {
> 
> safe_?

Sure. We don't change the list.

> > +		if ((cdev->flags & DEVFS_IS_PARTITION) &&
> > +			(cdev->flags & DEVFS_PARTITION_IN_PT)) {
> > +			int now;
> > +			int is_last = 0;
> > +			struct list_head *nh = (cdev)->devices_list.next;
> > +			struct cdev *next = container_of(nh, typeof(*(cdev)), devices_list);
> > +
> > +			if (list_is_last(&cdev->devices_list, &mci->dev.cdevs) ||
> > +				!(next->flags & DEVFS_PARTITION_IN_PT))
> > +				is_last = 1;
> 
> Is this test safe? What if the next partition does not have the
> DEVFS_PARTITION_IN_PT flag set, but the one after that has? Maybe you
> have to count the number of partitions in a first pass.


Yes. That's a good point. Will fix that.

> > +
> > +			now = print_part(buf, bufsize, cdev, is_last);
> > +			if (now < 0)
> > +				return now;
> > +
> > +			if (buf && bufsize) {
> > +				buf += now;
> > +				bufsize -= now;
> > +			}
> > +			ret += now;
> > +		}
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static const char *mci_partition_get(struct device_d *dev, struct param_d *p)
> > +{
> > +	struct mci *mci = container_of(dev, struct mci, dev);
> > +	int len = 0;
> > +
> > +	free(p->value);
> > +
> > +	len = print_parts(NULL, 0, mci);
> > +	p->value = xzalloc(len + 1);
> > +	print_parts(p->value, len + 1, mci);
> > +
> > +	return p->value;
> > +}
> > +
> > +#ifdef CONFIG_BLOCK_WRITE
> > +static int mci_partition_set(struct device_d *dev, struct param_d *p, const char *val)
> > +{
> > +	struct mci *mci = container_of(dev, struct mci, dev);
> > +	struct cdev *cdev, *ct;
> > +	int ret;
> > +
> > +	if (!val)
> > +		return -EINVAL;
> > +
> > +	/* remove all partition cdevs with DEVFS_IS_PARTITION set */
> > +	list_for_each_entry_safe(cdev, ct, &mci->dev.cdevs, devices_list) {
> > +		if ((cdev->flags & DEVFS_IS_PARTITION) &&
> > +			(cdev->flags & DEVFS_PARTITION_IN_PT))
> > +			ret = devfs_del_partition(cdev->name);
> > +			if (ret)
> > +				return ret;
> > +	}
> > +
> > +	/* read back the prepared partition layot from dos_partitions param */
> 
> s/layot/layout/
> 

Jupp.

> > +	ret = cmdlinepart_do_parse(mci->cdevname, val, mci->capacity,
> > +			CMDLINEPART_ADD_DEVNAME | CMDLINEPART_ADD_TO_PT);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* write the MBR partition layout based on cdevs with DEVFS_IS_PARTITION set  */
> > +	for (int i = 0; i < mci->nr_parts; i++) {
> > +		struct mci_part *part = &mci->part[i];
> > +		if (part->area_type == MMC_BLK_DATA_AREA_MAIN) {
> > +			ret = write_dos_partition_table(&part->blk,
> > +							&mci->dev.cdevs);
> > +			if (ret != 0) {
> > +				dev_warn(&mci->dev, "Could not write partition table\n");
> > +				return ret;
> > +			}
> > +		}
> > +	}
> > +
> > +	return ret;
> > +}
> > +#endif
> > +
> >  /**
> >   * Check if the MCI card is already probed
> >   * @param mci MCI device instance
> > @@ -1786,6 +1904,10 @@ int mci_register(struct mci_host *host)
> >  	mci->param_probe = dev_add_param_bool(&mci->dev, "probe",
> >  			mci_set_probe, NULL, &mci->probe, mci);
> >  
> > +#ifdef CONFIG_BLOCK_WRITE
> > +	dev_add_param(&mci->dev, "dos_partitions", mci_partition_set, mci_partition_get, 0);
> > +#endif
> 
> Use IS_ENABLED()
> 
> Other than that this code should be attached to parse_partition_table()
> rather than making this mci specific.
> We probably can safely write a dos partition table to an unpartitioned
> device, but should refuse to create/manipulate a dos partition table
> when a EFI partition table exists.

I will have that fixed in v2, until I figured out how to integrate that properly.

Thanks,
Michael


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply

* Re: [PATCH 1/2] nand: imx6: Changed default NAND clock
From: Sascha Hauer @ 2016-10-25  6:21 UTC (permalink / raw)
  To: Christian Hemp; +Cc: barebox, Daniel Schultz
In-Reply-To: <1476970807-43811-1-git-send-email-c.hemp@phytec.de>

On Thu, Oct 20, 2016 at 03:40:06PM +0200, Christian Hemp wrote:
> From: Daniel Schultz <d.schultz@phytec.de>
> 
> The Barebox recognized false bad erase blocks while booting from a
> Spansion NAND (1). This error occurred due a to high clock. The
> Kernel sets the default NAND clock to 22Mhz. So, to fix this error and
> to be more identical with the Kernel, the Barebox should be too.
> 
> 1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
> S34ML08G2), 1024MiB, page size: 2048, OOB size: 128

Applied both, thanks

Sascha

> 
> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
> Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> ---
>  drivers/mtd/nand/nand_mxs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
> index 01aa063..fe955e8 100644
> --- a/drivers/mtd/nand/nand_mxs.c
> +++ b/drivers/mtd/nand/nand_mxs.c
> @@ -2145,7 +2145,7 @@ static int mxs_nand_probe(struct device_d *dev)
>  
>  	if (mxs_nand_is_imx6(nand_info)) {
>  		clk_disable(nand_info->clk);
> -		clk_set_rate(nand_info->clk, 96000000);
> +		clk_set_rate(nand_info->clk, 22000000);
>  		clk_enable(nand_info->clk);
>  		nand_info->dma_channel_base = 0;
>  	} else {
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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