* Re: [PATCH 0/4] net/designware: A few patches from U-Boot
From: Sascha Hauer @ 2016-11-10 14:04 UTC (permalink / raw)
To: Ian Abbott; +Cc: barebox
In-Reply-To: <20161107181624.4262-1-abbotti@mev.co.uk>
On Mon, Nov 07, 2016 at 06:16:20PM +0000, Ian Abbott wrote:
> Here are a few old-ish patches for the Synopsys Designware Ethernet
> driver, ported over from U-Boot.
>
> 1) net/designware: Consecutive writes to the same register to be avoided
> 2) net/designware: Do not select MIIPORT for RGMII interface
> 3) net: designware: Respect "bus mode" register contents on SW reset
> 4) net/designware: add explicit reset of {tx|rx}_currdescnum
>
> drivers/net/designware.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
Applied, thanks
Sascha
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* Re: [PATCH v2 00/28] Vybrid support in Barebox
From: Sascha Hauer @ 2016-11-11 8:21 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
In-Reply-To: <1478708056-7875-1-git-send-email-andrew.smirnov@gmail.com>
Hi Andrey,
On Wed, Nov 09, 2016 at 08:13:48AM -0800, Andrey Smirnov wrote:
> Hi everyone,
>
> It took me a bit more than a month, but I finally put together a
> second version (for v1 see [1]) of the Vybrid support patchset.
>
> Some highlights of this version:
>
> - Various code/commit arrangement feedback for v1 is addressed
> - Added commit to move all of the i.MX clock code to drivers/clk
> (Sascha, we'd probably have to coordinate with your i.MX6ul
> patches on this one)
> - I2C commit split in two
> - clock tree is reconciled with Linux code, since having a custom
> version of it proved to be difficult to compare agains Linux's
> implementation
> - GPIO driver (tested on a custom Vybrid board)
> - FEC support (tested on a custom Vybrid board)
>
> Any feedback is, as always, very much appreciated.
The series looks mostly good, but I won't find the time for a deeper
review anytime soon, so I decided to just give it a try in -next.
Sascha
--
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* v2016.11.0
From: Sascha Hauer @ 2016-11-11 9:29 UTC (permalink / raw)
To: Barebox List
Hi All,
We have a November Release.
This is the first release which contains bootchooser, a framework which
simplifies and generalizes redundant boot scenarios.
Other than that we can now rename UBI volumes. Also there are improvemts
in running the UBI background thread which finally means that barebox
can write a fastmap on freshly formatted UBI devices. Previously barebox
was often not able to find an anchor PEB for the fastmap.
Another change worth noting is that the decision if defenv-1 or defenv-2
should be used can now be selected in Kconfig. It is no longer a board
decision.
As usual several fixes went in all over the place.
Sascha
----------------------------------------------------------------
Alexander Kurz (1):
mtd: spi-nor: add MX25U2033E
Andrey Smirnov (2):
i.MX: Introduce imx6_cpu_revision()
i.MX: Register imx6_fixup_cpus() for MX6Q+ as well
Antony Pavlov (1):
sandbox: Makefile: drop unused SUBARCH stuff
Christian Hemp (1):
mtd: nand: nand_mxs: Fix readtotal calculation
Daniel Schultz (1):
nand: imx6: Changed default NAND clock
Enrico Jorns (2):
net: add linux.bootarg parameter from ifup call
fs: nfs: pick up network interface bootargs parameter
Giorgio Dal Molin (2):
mtd: ubi: add API call to rename volumes.
mtd: ubi: commands: added the new command 'ubirename'.
Jan Luebbe (3):
ARM: i.MX6: remove duplicate clock initialization
ARM: i.MX6: fix clock gating
ARM: i.MX6: gate PCIe when unused
Lucas Stach (7):
ARM: imx6: split out IPU QoS setup
ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL
ARM: imx6qp: set NoC regulator to bypass
ARM: microsom: use imx6q_barebox_entry
ARM: imx6: add support for Auvidea H100
net: e1000: fix i210 register remapping
ARM: riotboard: fix barebox partition size
Marc Kleine-Budde (1):
boot: add framework for redundant boot scenarios
Michael Olbrich (3):
state: copy backend of_path string
state: don't keep pointers to device tree nodes
state: fix finding the correct parent node
Robert Schwebel (1):
Documentation: clarify that patches should target the master branch.
Sam Ravnborg (1):
environment: "wrong magic" gives the impression of an error
Sascha Hauer (76):
defenv-1: remove unused variable kernelimage_type
pbl: console: Let console pointer survive BSS clearing
ARM: i.MX6: Sabrelite: Add PBL console support
Add comp_copy function for use with CONFIG_IMAGE_COMPRESSION_NONE
ARM: Fix calling of arm_mem_barebox_image()
state: Add state to state_variable
state: make locally used function static
state: consistently pass one type as private data to dev_add_param_*
mtd: ubi: Add API calls to create/remove volumes
mtd: ubi: introduce barebox specific ioctl to get ubi_num
ARM: i.MX53: Add uart5 clock support
ARM: i.MX53 Vincell: Reset phy consistently from device tree
ARM: i.MX53 Vincell: Adjust bbu handler partition size to real partition size
ARM: i.MX53 Vincell: Add PBL console support
ARM: i.MX53: do not pass base address to imx*_boot_save_loc
ARM: i.MX: Provide bootsource functions for early boot code
ARM: i.MX53: Detect booting from USB
mtd: imx-nand: Move v3 register definitions to include file
ARM: i.MX53: Implement NAND xload
ARM: i.MX53 Vincell: Add NAND xload support
ARM: imx_v7_defconfig: Enable Vincell support
ARM: vincell_defconfig: make smaller
globalvar: Move static inline functions to common/
globalvar: sync with nvvars
vsprintf: Add support for printing ipv4 addresses with %pI4
convert users to %pI4
globalvar: Allow to remove multiple globalvars using wildcards
global: Make 'global' command behaviour consistent to 'nv'
nv: simplify nvvar_add
globalvar: Also create globalvars from for nonvolatile device vars
nv: Allow full variable name in nvvar_add
globalvar: Allow full variable name in globalvar_add
param: introduce param_bitmask
globalvar: introduce globalvar_add_simple_bitmask
mtd: ubi: commands: use function API to access ubi volumes
mtd: ubi: remove now unused ioctls
usb: Use standard debug macro
usb: Add usb phy to usb host
usb: ehci: forward phy given in registration data to host
usb: imx-usb-phy: Drop unnecessary read/modify/write
phy: Introduce of_phy_get_by_phandle
phy: Introduce to_usbphy conversion function
phy: Add usb-nop-xceiv support
usb: imx-us-phy: Convert driver to generic phy support
usb: imx-us-phy: implement notify_(dis)concect
dts: update to v4.8-rc1
dts: update to v4.8-rc2
dts: update to v4.8-rc4
dts: update to v4.8-rc5
dts: update to v4.8-rc6
dts: update to v4.8-rc7
dts: update to v4.8-rc8
Allow device parameters for devices with dots in name
completion: Fix completion for devices with a dot in the name
defaultenv: add defaultenv-1 in boards via defaultenv_append_directory()
Make generic default environment type a use choice
Merge branch 'for-next/arm'
Merge branch 'for-next/bootchooser'
Merge branch 'for-next/defenv'
Merge branch 'for-next/dts'
Merge branch 'for-next/imx'
Merge branch 'for-next/misc'
Merge branch 'for-next/mtd'
Merge branch 'for-next/mvebu'
Merge branch 'for-next/state'
Merge branch 'for-next/ubi'
Merge branch 'for-next/usb'
mtd: ubi: Fix scrubbing during attach
ARM: i.MX Freescale Sabrelite: Use correct device tree for dl variant
ARM: bootm: Fix free_mem calculation when initrd is given
mtd: ubi: enable thread earlier
ARM: Fix appended device tree when CONFIG_OFTREE is enabled
mtd: Make UBI detection more robust
of: partitions: Support new binding
of: of_find_path: Add support for new partition binding
Release v2016.11.0
Stefan Lengfeld (1):
state: fix state is not saved when string variable is changed
Steffen Trumtrar (3):
nand: denali: use correct interrupts in read_page
nand: denali: use is_timeout in while loop
nand: denali: get rid of compile-time debug information
Ulrich Ölmann (1):
blspec: fix typo
Uwe Kleine-König (17):
ARM: mvebu_defconfig: oldconfig
ARM: mvebu_defconfig: enable all machines, AEABI, nand and net driver
ARM: mvebu: select HAVE_DEFAULT_ENVIRONMENT_NEW
net: mvneta: clean txdesc before usage
firmware: altera-serial: Make the driver match the dt binding documentation
firmware: altera-serial: simplify handling of optional gpio
scripts: kwboot: try to resync on packet boundary after receiving a NAK
scripts: kwboot: flush input and output only once
scripts: kwboot: improve diagnostic output
scripts: kwboot: shorten delay between two boot messages
scripts: kwboot: simplify kwboot_mmap_image
scripts: kwboot: set boot source to UART before sending
images: mvebu: don't generate uart images
pinctrl: mvebu: add newline to error message
pinctrl: mvebu: armada-370 fix gpio name for mpp63
ARM: mvebu: add support for Netgear RN2120
ARM: mvebu: document some general mvebu stuff and the rn2120 board
Yegor Yefremov (2):
Add support for Baltos systems
boot: add '-w' parameter to usage help text
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* Re: v2016.11.0
From: Ian Abbott @ 2016-11-11 11:07 UTC (permalink / raw)
To: barebox
In-Reply-To: <20161111092941.44lmfsowkldkbhis@pengutronix.de>
On 11/11/16 09:29, Sascha Hauer wrote:
> Hi All,
>
> We have a November Release.
>
> This is the first release which contains bootchooser, a framework which
> simplifies and generalizes redundant boot scenarios.
> Other than that we can now rename UBI volumes. Also there are improvemts
> in running the UBI background thread which finally means that barebox
> can write a fastmap on freshly formatted UBI devices. Previously barebox
> was often not able to find an anchor PEB for the fastmap.
> Another change worth noting is that the decision if defenv-1 or defenv-2
> should be used can now be selected in Kconfig. It is no longer a board
> decision.
> As usual several fixes went in all over the place.
>
> Sascha
Thanks! I am wondering about the git repository - the "v2016.11.0" tag
exists, but seems to be 6 commits above the top of the "master" branch.
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@mev.co.uk> )=-
-=( Web: http://www.mev.co.uk/ )=-
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^ permalink raw reply
* Re: v2016.11.0
From: Sascha Hauer @ 2016-11-11 11:17 UTC (permalink / raw)
To: Ian Abbott; +Cc: barebox
In-Reply-To: <46139469-bb50-505d-4486-2336f8bf6b3e@mev.co.uk>
On Fri, Nov 11, 2016 at 11:07:27AM +0000, Ian Abbott wrote:
> On 11/11/16 09:29, Sascha Hauer wrote:
> > Hi All,
> >
> > We have a November Release.
> >
> > This is the first release which contains bootchooser, a framework which
> > simplifies and generalizes redundant boot scenarios.
> > Other than that we can now rename UBI volumes. Also there are improvemts
> > in running the UBI background thread which finally means that barebox
> > can write a fastmap on freshly formatted UBI devices. Previously barebox
> > was often not able to find an anchor PEB for the fastmap.
> > Another change worth noting is that the decision if defenv-1 or defenv-2
> > should be used can now be selected in Kconfig. It is no longer a board
> > decision.
> > As usual several fixes went in all over the place.
> >
> > Sascha
>
> Thanks! I am wondering about the git repository - the "v2016.11.0" tag
> exists, but seems to be 6 commits above the top of the "master" branch.
Gnagna, I screwed it up. I made the v2016.11.0 tag while my for-next/mtd
was checked out.
It seems last mtd patches took the fast lane and went into the November
release while they should be in the December release. So the following
went in early:
f160f86 of: of_find_path: Add support for new partition binding
1f2f980 of: partitions: Support new binding
1c7cf80 mtd: spi-nor: add MX25U2033E
7159d9d mtd: nand: nand_mxs: Fix readtotal calculation
0d68468 mtd: Make UBI detection more robust
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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* Compiler issues
From: Jose Luis Zabalza @ 2016-11-13 7:02 UTC (permalink / raw)
To: barebox
Hello everybody
I continue to have problems with memory size but I suspect they may be
due to a compiler issue.
It is possible?
I am using this compiler (from ubuntu package on X86_64)
$ arm-linux-gnueabi-gcc -v
Using built-in specs.
COLLECT_GCC=arm-linux-gnueabi-gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc-cross/arm-linux-gnueabi/4.7/lto-wrapper
Target: arm-linux-gnueabi
Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro
4.7.3-12ubuntu1'
--with-bugurl=file:///usr/share/doc/gcc-4.7/README.Bugs
--enable-languages=c,c++,go,fortran,objc,obj-c++ --prefix=/usr
--program-suffix=-4.7 --enable-shared --enable-linker-build-id
--libexecdir=/usr/lib --without-included-gettext
--enable-threads=posix
--with-gxx-include-dir=/usr/arm-linux-gnueabi/include/c++/4.7.3
--libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu
--enable-libstdcxx-debug --enable-gnu-unique-object
--disable-libmudflap --disable-libitm --enable-plugin
--with-system-zlib --enable-objc-gc --with-cloog
--enable-cloog-backend=ppl --disable-cloog-version-check
--disable-ppl-version-check --enable-multiarch --enable-multilib
--disable-sjlj-exceptions --with-arch=armv5t --with-float=soft
--disable-werror --enable-checking=release --build=x86_64-linux-gnu
--host=x86_64-linux-gnu --target=arm-linux-gnueabi
--program-prefix=arm-linux-gnueabi-
--includedir=/usr/arm-linux-gnueabi/include
Thread model: posix
gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1)
Thanks in advanced
--
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Linux Counter 172551
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* [RFCv2 0/2] add initial RISC-V architecture support
From: Antony Pavlov @ 2016-11-13 21:50 UTC (permalink / raw)
To: barebox
This patchseries adds initial RISC-V architecture support for barebox.
See Documentation/boards/riscv.rst for instructions.
You can obtain this patch from github:
$ git clone -b 20161113.riscv https://github.com/frantony/barebox
Changes since 20161013:
* drop spike pk support;
* add qemu-sifive board support;
* add Documentation/boards/riscv.rst;
* fix guard macro names.
TODOs:
* split patch;
* use sifive timer IP-block.
Antony Pavlov (2):
serial: add driver for SiFive UART
Add initial RISC-V architecture support
Documentation/boards/riscv.rst | 63 ++++++++++++++
arch/riscv/Kconfig | 42 ++++++++++
arch/riscv/Makefile | 51 ++++++++++++
arch/riscv/boards/qemu-sifive/.gitignore | 1 +
arch/riscv/boards/qemu-sifive/Makefile | 1 +
arch/riscv/boards/qemu-sifive/board.c | 28 +++++++
arch/riscv/boot/Makefile | 2 +
arch/riscv/boot/main_entry.c | 40 +++++++++
arch/riscv/boot/start.S | 44 ++++++++++
arch/riscv/configs/qemu-sifive_defconfig | 75 +++++++++++++++++
arch/riscv/dts/.gitignore | 1 +
arch/riscv/dts/Makefile | 9 ++
arch/riscv/dts/qemu-sifive.dts | 19 +++++
arch/riscv/dts/skeleton.dtsi | 13 +++
arch/riscv/include/asm/barebox.h | 1 +
arch/riscv/include/asm/bitops.h | 35 ++++++++
arch/riscv/include/asm/bitsperlong.h | 10 +++
arch/riscv/include/asm/byteorder.h | 12 +++
arch/riscv/include/asm/common.h | 6 ++
arch/riscv/include/asm/elf.h | 11 +++
arch/riscv/include/asm/io.h | 8 ++
arch/riscv/include/asm/posix_types.h | 1 +
arch/riscv/include/asm/sections.h | 1 +
arch/riscv/include/asm/string.h | 1 +
arch/riscv/include/asm/swab.h | 6 ++
arch/riscv/include/asm/types.h | 60 ++++++++++++++
arch/riscv/include/asm/unaligned.h | 19 +++++
arch/riscv/lib/.gitignore | 1 +
arch/riscv/lib/Makefile | 3 +
arch/riscv/lib/asm-offsets.c | 12 +++
arch/riscv/lib/barebox.lds.S | 87 ++++++++++++++++++++
arch/riscv/lib/dtb.c | 41 ++++++++++
arch/riscv/mach-sifive/Kconfig | 16 ++++
arch/riscv/mach-sifive/Makefile | 3 +
arch/riscv/mach-sifive/include/mach/debug_ll.h | 38 +++++++++
drivers/of/Kconfig | 2 +-
drivers/serial/Kconfig | 3 +
drivers/serial/Makefile | 1 +
drivers/serial/serial_sifive.c | 109 +++++++++++++++++++++++++
39 files changed, 875 insertions(+), 1 deletion(-)
create mode 100644 Documentation/boards/riscv.rst
create mode 100644 arch/riscv/Kconfig
create mode 100644 arch/riscv/Makefile
create mode 100644 arch/riscv/boards/qemu-sifive/.gitignore
create mode 100644 arch/riscv/boards/qemu-sifive/Makefile
create mode 100644 arch/riscv/boards/qemu-sifive/board.c
create mode 100644 arch/riscv/boot/Makefile
create mode 100644 arch/riscv/boot/main_entry.c
create mode 100644 arch/riscv/boot/start.S
create mode 100644 arch/riscv/configs/qemu-sifive_defconfig
create mode 100644 arch/riscv/dts/.gitignore
create mode 100644 arch/riscv/dts/Makefile
create mode 100644 arch/riscv/dts/qemu-sifive.dts
create mode 100644 arch/riscv/dts/skeleton.dtsi
create mode 100644 arch/riscv/include/asm/barebox.h
create mode 100644 arch/riscv/include/asm/bitops.h
create mode 100644 arch/riscv/include/asm/bitsperlong.h
create mode 100644 arch/riscv/include/asm/byteorder.h
create mode 100644 arch/riscv/include/asm/common.h
create mode 100644 arch/riscv/include/asm/elf.h
create mode 100644 arch/riscv/include/asm/io.h
create mode 100644 arch/riscv/include/asm/posix_types.h
create mode 100644 arch/riscv/include/asm/sections.h
create mode 100644 arch/riscv/include/asm/string.h
create mode 100644 arch/riscv/include/asm/swab.h
create mode 100644 arch/riscv/include/asm/types.h
create mode 100644 arch/riscv/include/asm/unaligned.h
create mode 100644 arch/riscv/lib/.gitignore
create mode 100644 arch/riscv/lib/Makefile
create mode 100644 arch/riscv/lib/asm-offsets.c
create mode 100644 arch/riscv/lib/barebox.lds.S
create mode 100644 arch/riscv/lib/dtb.c
create mode 100644 arch/riscv/mach-sifive/Kconfig
create mode 100644 arch/riscv/mach-sifive/Makefile
create mode 100644 arch/riscv/mach-sifive/include/mach/debug_ll.h
create mode 100644 drivers/serial/serial_sifive.c
--
2.10.2
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* [RFCv2 1/2] serial: add driver for SiFive UART
From: Antony Pavlov @ 2016-11-13 21:50 UTC (permalink / raw)
To: barebox
In-Reply-To: <20161113215015.9399-1-antonynpavlov@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
TODO:
* add speed setup support.
drivers/serial/Kconfig | 3 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_sifive.c | 109 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 113 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b112d7e..70509b9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -117,6 +117,9 @@ config DRIVER_SERIAL_S3C_AUTOSYNC
Say Y here if you want to use the auto flow feature of this
UART. RTS and CTS will be handled by the hardware when enabled.
+config DRIVER_SERIAL_SIFIVE
+ bool "SiFive serial driver"
+
config DRIVER_SERIAL_PXA
bool "PXA serial driver"
depends on ARCH_PXA
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 189e777..368e992 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_DRIVER_SERIAL_AUART) += serial_auart.o
obj-$(CONFIG_DRIVER_SERIAL_CADENCE) += serial_cadence.o
obj-$(CONFIG_DRIVER_SERIAL_EFI_STDIO) += efi-stdio.o
obj-$(CONFIG_DRIVER_SERIAL_DIGIC) += serial_digic.o
+obj-$(CONFIG_DRIVER_SERIAL_SIFIVE) += serial_sifive.o
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
new file mode 100644
index 0000000..06e3521
--- /dev/null
+++ b/drivers/serial/serial_sifive.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <io.h>
+
+#define UART_RX_OFFSET 0
+#define UART_TX_OFFSET 0
+#define UART_TX_COUNT_OFFSET 0x4
+#define UART_RX_COUNT_OFFSET 0x8
+#define UART_DIVIDER_OFFSET 0xC
+
+static inline uint32_t sifive_serial_readl(struct console_device *cdev,
+ uint32_t offset)
+{
+ void __iomem *base = cdev->dev->priv;
+
+ return readl(base + offset);
+}
+
+static inline void sifive_serial_writel(struct console_device *cdev,
+ uint32_t value, uint32_t offset)
+{
+ void __iomem *base = cdev->dev->priv;
+
+ writel(value, base + offset);
+}
+
+static int sifive_serial_setbaudrate(struct console_device *cdev, int baudrate)
+{
+ /* FIXME: no baudrate setup at the momement :( */
+
+ return 0;
+}
+
+static void sifive_serial_putc(struct console_device *cdev, char c)
+{
+ sifive_serial_writel(cdev, c, UART_TX_OFFSET);
+}
+
+static int sifive_serial_getc(struct console_device *cdev)
+{
+ uint32_t rxcnt;
+
+ do {
+ rxcnt = sifive_serial_readl(cdev, UART_RX_COUNT_OFFSET);
+ } while (!rxcnt);
+
+ return sifive_serial_readl(cdev, UART_RX_OFFSET);
+}
+
+static int sifive_serial_tstc(struct console_device *cdev)
+{
+ uint32_t rxcnt = sifive_serial_readl(cdev, UART_RX_COUNT_OFFSET);
+
+ return (rxcnt != 0);
+}
+
+static int sifive_serial_probe(struct device_d *dev)
+{
+ struct resource *iores;
+ struct console_device *cdev;
+
+ cdev = xzalloc(sizeof(struct console_device));
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
+ dev->priv = IOMEM(iores->start);
+ cdev->dev = dev;
+ cdev->tstc = &sifive_serial_tstc;
+ cdev->putc = &sifive_serial_putc;
+ cdev->getc = &sifive_serial_getc;
+ cdev->setbrg = &sifive_serial_setbaudrate;
+
+ console_register(cdev);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id sifive_serial_dt_ids[] = {
+ {
+ .compatible = "sifive,uart",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d sifive_serial_driver = {
+ .name = "sifive-uart",
+ .probe = sifive_serial_probe,
+ .of_compatible = DRV_OF_COMPAT(sifive_serial_dt_ids),
+};
+console_platform_driver(sifive_serial_driver);
--
2.10.2
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [RFCv2 2/2] add initial RISC-V architecture support
From: Antony Pavlov @ 2016-11-13 21:50 UTC (permalink / raw)
To: barebox
In-Reply-To: <20161113215015.9399-1-antonynpavlov@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
TODOs:
* split this patch.
* use sifive timer IP-block.
Documentation/boards/riscv.rst | 63 +++++++++++++++++++
arch/riscv/Kconfig | 42 +++++++++++++
arch/riscv/Makefile | 51 +++++++++++++++
arch/riscv/boards/qemu-sifive/.gitignore | 1 +
arch/riscv/boards/qemu-sifive/Makefile | 1 +
arch/riscv/boards/qemu-sifive/board.c | 28 +++++++++
arch/riscv/boot/Makefile | 2 +
arch/riscv/boot/main_entry.c | 40 ++++++++++++
arch/riscv/boot/start.S | 44 +++++++++++++
arch/riscv/configs/qemu-sifive_defconfig | 75 ++++++++++++++++++++++
arch/riscv/dts/.gitignore | 1 +
arch/riscv/dts/Makefile | 9 +++
arch/riscv/dts/qemu-sifive.dts | 19 ++++++
arch/riscv/dts/skeleton.dtsi | 13 ++++
arch/riscv/include/asm/barebox.h | 1 +
arch/riscv/include/asm/bitops.h | 35 +++++++++++
arch/riscv/include/asm/bitsperlong.h | 10 +++
arch/riscv/include/asm/byteorder.h | 12 ++++
arch/riscv/include/asm/common.h | 6 ++
arch/riscv/include/asm/elf.h | 11 ++++
arch/riscv/include/asm/io.h | 8 +++
arch/riscv/include/asm/posix_types.h | 1 +
arch/riscv/include/asm/sections.h | 1 +
arch/riscv/include/asm/string.h | 1 +
arch/riscv/include/asm/swab.h | 6 ++
arch/riscv/include/asm/types.h | 60 ++++++++++++++++++
arch/riscv/include/asm/unaligned.h | 19 ++++++
arch/riscv/lib/.gitignore | 1 +
arch/riscv/lib/Makefile | 3 +
arch/riscv/lib/asm-offsets.c | 12 ++++
arch/riscv/lib/barebox.lds.S | 87 ++++++++++++++++++++++++++
arch/riscv/lib/dtb.c | 41 ++++++++++++
arch/riscv/mach-sifive/Kconfig | 16 +++++
arch/riscv/mach-sifive/Makefile | 3 +
arch/riscv/mach-sifive/include/mach/debug_ll.h | 38 +++++++++++
drivers/of/Kconfig | 2 +-
36 files changed, 762 insertions(+), 1 deletion(-)
diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
new file mode 100644
index 0000000..f22504a
--- /dev/null
+++ b/Documentation/boards/riscv.rst
@@ -0,0 +1,63 @@
+RISC-V
+======
+
+At the moment only qemu emulator is supported (see https://github.com/riscv/riscv-isa-sim
+for details).
+
+Running RISC-V barebox
+----------------------
+
+Obtain RISC-V GCC/Newlib Toolchain,
+see https://github.com/riscv/riscv-tools/blob/master/README.md
+for details. The ``build.sh`` script from ``riscv-tools`` should
+create toolchain.
+
+Next compile qemu emulator::
+
+ $ git clone https://github.com/riscv/riscv-qemu
+ $ cd riscv-qemu
+ $ cap="no" ./configure \
+ --extra-cflags="-Wno-maybe-uninitialized" \
+ --audio-drv-list="" \
+ --disable-attr \
+ --disable-blobs \
+ --disable-bluez \
+ --disable-brlapi \
+ --disable-curl \
+ --disable-curses \
+ --disable-docs \
+ --disable-kvm \
+ --disable-spice \
+ --disable-sdl \
+ --disable-vde \
+ --disable-vnc-sasl \
+ --disable-werror \
+ --enable-trace-backend=simple \
+ --disable-stack-protector \
+ --target-list=riscv32-softmmu,riscv64-softmmu
+ $ make
+
+Next compile barebox::
+
+ $ make qemu-sifive_defconfig ARCH=riscv
+ ...
+ $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv64-unknown-elf-
+
+Run barebox::
+
+ $ <path to riscv-qemu source>/riscv64-softmmu/qemu-system-riscv64 \
+ -nographic -M sifive -kernel <path to barebox sources >/barebox \
+ -serial stdio -monitor none -trace file=/dev/null
+
+ Switch to console [cs0]
+
+
+ barebox 2016.11.0-00006-g3c29f61 #1 Mon Nov 13 22:21:03 MSK 2016
+
+
+ Board: QEMU SiFive
+ Warning: Using dummy clocksource
+ malloc space: 0x00800000 -> 0x00bfffff (size 4 MiB)
+ running /env/bin/init...
+ /env/bin/init not found
+ barebox:/
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
new file mode 100644
index 0000000..baf9ce0
--- /dev/null
+++ b/arch/riscv/Kconfig
@@ -0,0 +1,42 @@
+config RISCV
+ bool
+ select GENERIC_FIND_NEXT_BIT
+ select OFTREE
+ select HAVE_CONFIGURABLE_MEMORY_LAYOUT
+ select HAVE_CONFIGURABLE_TEXT_BASE
+ default y
+
+config GENERIC_LINKER_SCRIPT
+ bool
+ default y
+
+menu "Machine selection"
+
+choice
+ prompt "System type"
+ default MACH_SIFIVE
+
+config MACH_SIFIVE
+ bool "SiFive"
+
+endchoice
+
+config BUILTIN_DTB
+ bool "link a DTB into the barebox image"
+ depends on OFTREE
+
+config BUILTIN_DTB_NAME
+ string "DTB to build into the barebox image"
+ depends on BUILTIN_DTB
+
+source arch/riscv/mach-sifive/Kconfig
+
+endmenu
+
+source common/Kconfig
+source commands/Kconfig
+source net/Kconfig
+source drivers/Kconfig
+source fs/Kconfig
+source lib/Kconfig
+source crypto/Kconfig
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
new file mode 100644
index 0000000..cebcce5
--- /dev/null
+++ b/arch/riscv/Makefile
@@ -0,0 +1,51 @@
+CPPFLAGS += -fno-strict-aliasing
+
+cflags-y += -fno-pic -pipe
+cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \
+ -Wno-uninitialized -Wno-format -Wno-main
+
+LDFLAGS += $(ldflags-y)
+LDFLAGS_barebox += -nostdlib
+
+machine-$(CONFIG_MACH_SIFIVE) := sifive
+board-$(CONFIG_BOARD_QEMU_SIFIVE) := qemu-sifive
+
+TEXT_BASE = $(CONFIG_TEXT_BASE)
+CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
+
+machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y))
+
+ifeq ($(KBUILD_SRC),)
+CPPFLAGS += $(patsubst %,-I%include,$(machdirs))
+else
+CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
+endif
+
+archprepare: maketools
+
+PHONY += maketools
+
+ifneq ($(machine-y),)
+MACH := arch/riscv/mach-$(machine-y)/
+else
+MACH :=
+endif
+
+ifneq ($(board-y),)
+BOARD := arch/riscv/boards/$(board-y)/
+else
+BOARD :=
+endif
+
+common-y += $(BOARD) $(MACH)
+common-y += arch/riscv/lib/
+common-y += arch/riscv/boot/
+
+common-$(CONFIG_OFTREE) += arch/riscv/dts/
+
+CPPFLAGS += $(cflags-y)
+CFLAGS += $(cflags-y)
+
+lds-y := arch/riscv/lib/barebox.lds
+
+CLEAN_FILES += arch/riscv/lib/barebox.lds
diff --git a/arch/riscv/boards/qemu-sifive/.gitignore b/arch/riscv/boards/qemu-sifive/.gitignore
new file mode 100644
index 0000000..d116578
--- /dev/null
+++ b/arch/riscv/boards/qemu-sifive/.gitignore
@@ -0,0 +1 @@
+barebox.lds
diff --git a/arch/riscv/boards/qemu-sifive/Makefile b/arch/riscv/boards/qemu-sifive/Makefile
new file mode 100644
index 0000000..dcfc293
--- /dev/null
+++ b/arch/riscv/boards/qemu-sifive/Makefile
@@ -0,0 +1 @@
+obj-y += board.o
diff --git a/arch/riscv/boards/qemu-sifive/board.c b/arch/riscv/boards/qemu-sifive/board.c
new file mode 100644
index 0000000..ecda850
--- /dev/null
+++ b/arch/riscv/boards/qemu-sifive/board.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+
+static int hostname_init(void)
+{
+ barebox_set_hostname("barebox");
+
+ return 0;
+}
+postcore_initcall(hostname_init);
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
new file mode 100644
index 0000000..d6d28ce
--- /dev/null
+++ b/arch/riscv/boot/Makefile
@@ -0,0 +1,2 @@
+obj-y += start.o
+obj-y += main_entry.o
diff --git a/arch/riscv/boot/main_entry.c b/arch/riscv/boot/main_entry.c
new file mode 100644
index 0000000..18db86d
--- /dev/null
+++ b/arch/riscv/boot/main_entry.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <memory.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/sections.h>
+
+void main_entry(void);
+
+/**
+ * Called plainly from assembler code
+ *
+ * @note The C environment isn't initialized yet
+ */
+void main_entry(void)
+{
+ /* clear the BSS first */
+ memset(__bss_start, 0x00, __bss_stop - __bss_start);
+
+ mem_malloc_init((void *)MALLOC_BASE,
+ (void *)(MALLOC_BASE + MALLOC_SIZE - 1));
+
+ start_barebox();
+}
diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S
new file mode 100644
index 0000000..1c7612c
--- /dev/null
+++ b/arch/riscv/boot/start.S
@@ -0,0 +1,44 @@
+/*
+ * Startup Code for MIPS CPU
+ *
+ * based on coreboot/src/arch/riscv/bootblock.S
+ *
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm-generic/memory_layout.h>
+
+ .text
+ .section ".text_bare_init"
+ .align 4
+
+.globl _start
+_start:
+
+ li sp, STACK_BASE + STACK_SIZE
+
+ # make room for HLS and initialize it
+ addi sp, sp, -64 /* MENTRY_FRAME_SIZE */
+
+ # poison the stack
+ li t1, STACK_BASE
+ li t0, 0xdeadbeef
+ sd t0, 0(t1)
+
+ # clear any pending interrupts
+ csrwi mip, 0
+
+ tail main_entry
diff --git a/arch/riscv/configs/qemu-sifive_defconfig b/arch/riscv/configs/qemu-sifive_defconfig
new file mode 100644
index 0000000..774dfad
--- /dev/null
+++ b/arch/riscv/configs/qemu-sifive_defconfig
@@ -0,0 +1,75 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="qemu-sifive"
+# CONFIG_GLOBALVAR is not set
+CONFIG_TEXT_BASE=0x00001000
+CONFIG_MEMORY_LAYOUT_FIXED=y
+CONFIG_STACK_BASE=0x007f0000
+CONFIG_STACK_SIZE=0x10000
+CONFIG_MALLOC_BASE=0x00800000
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_BOOTM is not set
+CONFIG_PARTITION=y
+# CONFIG_ENV_HANDLING is not set
+CONFIG_DEFAULT_COMPRESSION_GZIP=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_BASENAME=y
+CONFIG_CMD_CMP=y
+CONFIG_CMD_DIRNAME=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_READLINK=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_SHA384SUM=y
+CONFIG_CMD_SHA512SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_GETOPT=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_OFDEVICE=y
+CONFIG_DRIVER_SERIAL_SIFIVE=y
+# CONFIG_SPI is not set
+# CONFIG_PINCTRL is not set
+CONFIG_FS_BPKFS=y
+CONFIG_FS_UIMAGEFS=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DECOMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DIGEST_HMAC_GENERIC=y
diff --git a/arch/riscv/dts/.gitignore b/arch/riscv/dts/.gitignore
new file mode 100644
index 0000000..077903c
--- /dev/null
+++ b/arch/riscv/dts/.gitignore
@@ -0,0 +1 @@
+*dtb*
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
new file mode 100644
index 0000000..f8380b1
--- /dev/null
+++ b/arch/riscv/dts/Makefile
@@ -0,0 +1,9 @@
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
+obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
+
+# just to build a built-in.o. Otherwise compilation fails when no devicetree is
+# created.
+obj- += dummy.o
+
+always := $(dtb-y)
+clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
diff --git a/arch/riscv/dts/qemu-sifive.dts b/arch/riscv/dts/qemu-sifive.dts
new file mode 100644
index 0000000..61945f2
--- /dev/null
+++ b/arch/riscv/dts/qemu-sifive.dts
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "QEMU SiFive";
+ compatible = "sifive,qemu";
+
+ /* Digilent Arty has 256MB DDR3L */
+ memory {
+ device_type = "memory";
+ reg = <0 0x0 0x10000000>;
+ };
+
+ uart: uart {
+ compatible = "sifive,uart";
+ reg = <0 0x40002000 0x10>;
+ };
+};
diff --git a/arch/riscv/dts/skeleton.dtsi b/arch/riscv/dts/skeleton.dtsi
new file mode 100644
index 0000000..38ead82
--- /dev/null
+++ b/arch/riscv/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; reg = <0 0 0>; };
+};
diff --git a/arch/riscv/include/asm/barebox.h b/arch/riscv/include/asm/barebox.h
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/arch/riscv/include/asm/barebox.h
@@ -0,0 +1 @@
+/* dummy */
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
new file mode 100644
index 0000000..e77ab83
--- /dev/null
+++ b/arch/riscv/include/asm/bitops.h
@@ -0,0 +1,35 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#ifndef _ASM_BITOPS_H_
+#define _ASM_BITOPS_H_
+
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ops.h>
+
+#define set_bit(x, y) __set_bit(x, y)
+#define clear_bit(x, y) __clear_bit(x, y)
+#define change_bit(x, y) __change_bit(x, y)
+#define test_and_set_bit(x, y) __test_and_set_bit(x, y)
+#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y)
+#define test_and_change_bit(x, y) __test_and_change_bit(x, y)
+
+#endif /* _ASM_BITOPS_H_ */
diff --git a/arch/riscv/include/asm/bitsperlong.h b/arch/riscv/include/asm/bitsperlong.h
new file mode 100644
index 0000000..4641e7e
--- /dev/null
+++ b/arch/riscv/include/asm/bitsperlong.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_BITSPERLONG_H
+#define __ASM_BITSPERLONG_H
+
+#ifdef __riscv64
+#define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
+
+#endif /* __ASM_BITSPERLONG_H */
diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h
new file mode 100644
index 0000000..994a61a
--- /dev/null
+++ b/arch/riscv/include/asm/byteorder.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_RISCV_BYTEORDER_H
+#define _ASM_RISCV_BYTEORDER_H
+
+#if defined(__RISCVEL__)
+#include <linux/byteorder/little_endian.h>
+#elif defined(__RISCVEB__)
+#include <linux/byteorder/big_endian.h>
+#else
+#error "Unknown endianness"
+#endif
+
+#endif /* _ASM_RISCV_BYTEORDER_H */
diff --git a/arch/riscv/include/asm/common.h b/arch/riscv/include/asm/common.h
new file mode 100644
index 0000000..bc8a17e
--- /dev/null
+++ b/arch/riscv/include/asm/common.h
@@ -0,0 +1,6 @@
+#ifndef ASM_RISCV_COMMON_H
+#define ASM_RISCV_COMMON_H
+
+/* nothing special yet */
+
+#endif /* ASM_RISCV_COMMON_H */
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
new file mode 100644
index 0000000..7134fa0
--- /dev/null
+++ b/arch/riscv/include/asm/elf.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_RISCV_ELF_H__
+#define __ASM_RISCV_ELF_H__
+
+#if __SIZEOF_POINTER__ == 8
+#define ELF_CLASS ELFCLASS64
+#define CONFIG_PHYS_ADDR_T_64BIT
+#else
+#define ELF_CLASS ELFCLASS32
+#endif
+
+#endif /* __ASM_RISCV_ELF_H__ */
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
new file mode 100644
index 0000000..d9aca42
--- /dev/null
+++ b/arch/riscv/include/asm/io.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_RISCV_IO_H
+#define __ASM_RISCV_IO_H
+
+#include <asm-generic/io.h>
+
+#define IO_SPACE_LIMIT 0
+
+#endif /* __ASM_RISCV_IO_H */
diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h
new file mode 100644
index 0000000..22cae62
--- /dev/null
+++ b/arch/riscv/include/asm/posix_types.h
@@ -0,0 +1 @@
+#include <asm-generic/posix_types.h>
diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h
new file mode 100644
index 0000000..2b8c516
--- /dev/null
+++ b/arch/riscv/include/asm/sections.h
@@ -0,0 +1 @@
+#include <asm-generic/sections.h>
diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/arch/riscv/include/asm/string.h
@@ -0,0 +1 @@
+/* dummy */
diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h
new file mode 100644
index 0000000..60a9012
--- /dev/null
+++ b/arch/riscv/include/asm/swab.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_SWAB_H
+#define _ASM_SWAB_H
+
+/* nothing. use generic functions */
+
+#endif /* _ASM_SWAB_H */
diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
new file mode 100644
index 0000000..ba386ab
--- /dev/null
+++ b/arch/riscv/include/asm/types.h
@@ -0,0 +1,60 @@
+#ifndef __ASM_RISCV_TYPES_H
+#define __ASM_RISCV_TYPES_H
+
+#ifdef __riscv64
+/*
+ * This is used in dlmalloc. On RISCV64 we need it to be 64 bit
+ */
+#define INTERNAL_SIZE_T unsigned long
+
+/*
+ * This is a Kconfig variable in the Kernel, but we want to detect
+ * this during compile time, so we set it here.
+ */
+#define CONFIG_PHYS_ADDR_T_64BIT
+
+#endif
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#include <asm/bitsperlong.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_RISCV_TYPES_H */
diff --git a/arch/riscv/include/asm/unaligned.h b/arch/riscv/include/asm/unaligned.h
new file mode 100644
index 0000000..aaebc06
--- /dev/null
+++ b/arch/riscv/include/asm/unaligned.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_RISCV_UNALIGNED_H
+#define _ASM_RISCV_UNALIGNED_H
+
+/*
+ * FIXME: this file is copy-n-pasted from sandbox's unaligned.h
+ */
+
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define get_unaligned __get_unaligned_le
+#define put_unaligned __put_unaligned_le
+#else
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+#endif
+
+#endif /* _ASM_RISCV_UNALIGNED_H */
diff --git a/arch/riscv/lib/.gitignore b/arch/riscv/lib/.gitignore
new file mode 100644
index 0000000..d116578
--- /dev/null
+++ b/arch/riscv/lib/.gitignore
@@ -0,0 +1 @@
+barebox.lds
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
new file mode 100644
index 0000000..07a1b2b
--- /dev/null
+++ b/arch/riscv/lib/Makefile
@@ -0,0 +1,3 @@
+extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds
+
+obj-$(CONFIG_BUILTIN_DTB) += dtb.o
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
new file mode 100644
index 0000000..22f382b
--- /dev/null
+++ b/arch/riscv/lib/asm-offsets.c
@@ -0,0 +1,12 @@
+/*
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ */
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ return 0;
+}
diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S
new file mode 100644
index 0000000..831c3e4
--- /dev/null
+++ b/arch/riscv/lib/barebox.lds.S
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm-generic/barebox.lds.h>
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+ . = TEXT_BASE;
+
+ . = ALIGN(8);
+ .text :
+ {
+ _start = .;
+ *(.text_entry*)
+ _stext = .;
+ _text = .;
+ __bare_init_start = .;
+ *(.text_bare_init*)
+ __bare_init_end = .;
+ *(.text*)
+ }
+ BAREBOX_BARE_INIT_SIZE
+
+ PRE_IMAGE
+
+ . = ALIGN(8);
+ .rodata : { *(.rodata*) }
+
+ _etext = .; /* End of text and rodata section */
+ _sdata = .;
+
+ . = ALIGN(8);
+ .data : { *(.data*) }
+
+ .barebox_imd : { BAREBOX_IMD }
+
+ . = ALIGN(8);
+ .got : { *(.got*) }
+
+ . = .;
+ __barebox_cmd_start = .;
+ .barebox_cmd : { BAREBOX_CMDS }
+ __barebox_cmd_end = .;
+
+ __barebox_magicvar_start = .;
+ .barebox_magicvar : { BAREBOX_MAGICVARS }
+ __barebox_magicvar_end = .;
+
+ __barebox_initcalls_start = .;
+ .barebox_initcalls : { INITCALLS }
+ __barebox_initcalls_end = .;
+
+ __barebox_exitcalls_start = .;
+ .barebox_exitcalls : { EXITCALLS }
+ __barebox_exitcalls_end = .;
+
+ __usymtab_start = .;
+ __usymtab : { BAREBOX_SYMS }
+ __usymtab_end = .;
+
+ .oftables : { BAREBOX_CLK_TABLE() }
+
+ .dtb : { BAREBOX_DTB() }
+
+ _edata = .;
+ . = ALIGN(8);
+ __bss_start = .;
+ .bss : { *(.bss*) }
+ __bss_stop = .;
+ _end = .;
+}
diff --git a/arch/riscv/lib/dtb.c b/arch/riscv/lib/dtb.c
new file mode 100644
index 0000000..09f519d
--- /dev/null
+++ b/arch/riscv/lib/dtb.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <of.h>
+
+extern char __dtb_start[];
+
+static int of_riscv_init(void)
+{
+ struct device_node *root;
+
+ root = of_get_root_node();
+ if (root)
+ return 0;
+
+ root = of_unflatten_dtb(__dtb_start);
+ if (!IS_ERR(root)) {
+ pr_debug("using internal DTB\n");
+ of_set_root_node(root);
+ if (IS_ENABLED(CONFIG_OFDEVICE))
+ of_probe();
+ }
+
+ return 0;
+}
+core_initcall(of_riscv_init);
diff --git a/arch/riscv/mach-sifive/Kconfig b/arch/riscv/mach-sifive/Kconfig
new file mode 100644
index 0000000..11251dd
--- /dev/null
+++ b/arch/riscv/mach-sifive/Kconfig
@@ -0,0 +1,16 @@
+if MACH_SIFIVE
+
+config ARCH_TEXT_BASE
+ hex
+ default 0x00001000
+
+choice
+ prompt "Board type"
+
+config BOARD_QEMU_SIFIVE
+ bool "qemu sifive"
+ select HAS_DEBUG_LL
+
+endchoice
+
+endif
diff --git a/arch/riscv/mach-sifive/Makefile b/arch/riscv/mach-sifive/Makefile
new file mode 100644
index 0000000..d9c51e7
--- /dev/null
+++ b/arch/riscv/mach-sifive/Makefile
@@ -0,0 +1,3 @@
+# just to build a built-in.o. Otherwise compilation fails when no o-files is
+# created.
+obj- += dummy.o
diff --git a/arch/riscv/mach-sifive/include/mach/debug_ll.h b/arch/riscv/mach-sifive/include/mach/debug_ll.h
new file mode 100644
index 0000000..b2dbfc2
--- /dev/null
+++ b/arch/riscv/mach-sifive/include/mach/debug_ll.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_SIFIVE_DEBUG_LL__
+#define __MACH_SIFIVE_DEBUG_LL__
+
+/** @file
+ * This File contains declaration for early output support
+ */
+
+#include <linux/kconfig.h>
+#include <asm/io.h>
+
+#define UART_BASE 0x40002000
+#define R_DATA (0 << 2)
+#define R_RXCNT (2 << 2)
+
+static inline void PUTC_LL(int ch)
+{
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ __raw_writeb(ch, (u8 *)UART_BASE + R_DATA);
+}
+
+#endif /* __MACH_SIFIVE_DEBUG_LL__ */
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index d0a62bd..0824b04 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -4,7 +4,7 @@ config OFTREE
config OFTREE_MEM_GENERIC
depends on OFTREE
- depends on PPC || ARM || ARCH_EFI || OPENRISC || SANDBOX
+ depends on PPC || ARM || ARCH_EFI || OPENRISC || SANDBOX || RISCV
def_bool y
config DTC
--
2.10.2
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^ permalink raw reply related
* [PATCH] pcm049: Add 1 GByte RAM with DUAL DIE Single Rank
From: Maik Otto @ 2016-11-14 9:47 UTC (permalink / raw)
To: barebox; +Cc: Maik Otto
tested with Micron MT42L128M64D2LL-25WT and MT42L128M64D2LL-25WT
Signed-off-by: Maik Otto <m.otto@phytec.de>
---
arch/arm/boards/phytec-phycore-omap4460/lowlevel.c | 32 +++++++++++++++++++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
index c082594..71ab793 100644
--- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
@@ -30,6 +30,13 @@
#include <asm/barebox-arm-head.h>
#define TPS62361_VSEL0_GPIO 182
+#define LPDDR2_2G 0x5
+#define LPDDR2_4G 0x6
+#define LPDDR2_DENSITY_MASK 0x3C
+#define LPDDR2_DENSITY_SHIFT 2
+#define EMIF_SDRAM_CONFIG 0x0008
+#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
+#define EMIF_LPDDR2_MODE_REG_DATA 0x0040
void set_muxconf_regs(void);
@@ -61,8 +68,23 @@ static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = {
.mr2 = 0x4
};
+static const struct ddr_regs ddr_regs_mt42L128M64D2LL_25_400_mhz = {
+ .tim1 = 0x10EB0662,
+ .tim2 = 0x205715D2,
+ .tim3 = 0x00B1C53F,
+ .phy_ctrl_1 = 0x849FF409,
+ .ref_ctrl = 0x00000618,
+ .config_init = 0x80001AB2,
+ .config_final = 0x80001AB2,
+ .zq_config = 0x500B3214,
+ .mr1 = 0x83,
+ .mr2 = 0x4
+};
+
static void noinline pcm049_init_lowlevel(void)
{
+ unsigned int density;
+
struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
@@ -75,9 +97,17 @@ static void noinline pcm049_init_lowlevel(void)
set_muxconf_regs();
#ifdef CONFIG_1024MB_DDR2RAM
+ omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
+ writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE +
+ EMIF_LPDDR2_MODE_REG_CONFIG);
+ density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) &
+ LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT;
+ if (density == LPDDR2_2G)
omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);
+ else if (density == LPDDR2_4G)
+ omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core);
#else
- omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
+ omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
#endif
/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
--
1.7.0.4
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^ permalink raw reply related
* usb otg port not working on an imx25 soc
From: iw3gtf @ 2016-11-14 12:57 UTC (permalink / raw)
To: barebox
Hi,
I'm currently working on an embedded board with an imx25 soc and I want
to enable the usb otg port of the soc; in my use case I just want the otg port
to be configured in usb host mode and use the integrated UTMI phy.
I built barebox with usb support and the usb ports are actually found:
barebox:/ usb
usb: USB: scanning bus for devices...
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=256, index=0
imx-usb imx-usb0: USB_DT_DEVICE request
imx-usb imx-usb0: req=5 (0x5), typ(0xe=0 0), value=1, index=0
imx-usb imx-usb0: USB_REQ_SET_ADDRESS
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=256, index=0
imx-usb imx-usb0: USB_DT_DEVICE request
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=512, index=0
imx-usb imx-usb0: USB_DT_CONFIG config
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=512, index=0
imx-usb imx-usb0: USB_DT_CONFIG config
imx- iumsbx-usb0: req=9 (0x9), type=0 (0x0), value=1, index=0
imx-usb imx-usb0: USB_REQ_SET_CONFIGURATION
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=768, index=0
imx-usb imx-usb0: USB_DT_STRING config
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=769, index=1
imx-usb imx-usb0: USB_DT_STRING config
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=770, index=1
imx-usb imx-usb0: USB_DT_STRING config
usb: Bus 001 Device 001: ID 000000: 00EHCI Host Controller
imx-usb imx-usb0: req=6 (0x6), type=160 (0xa0), value=10496, index=0
omx-usb imx-usb0: USB_DT_HUB figc
nimx-usb imx-usb0: req=6 (0x6), type=160 (0xa0), value=10496, index=0
imx-usb imx-usb0: USB_DT_HUB config
imx-usb imx-usb0: req=0 (0x0), type=160 (0xa0), value=0, index=0
imx-usb imx-usb0: req=1 (0x1), type=35 (0x23), value=8, index=1
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=3 (0x3), type=35 (0x23), value=8, index=1
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=0 (0x0), type=163 (0xa3), value=0, index=1
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=256, index=0
imx-usb imx-usb1: USB_DT_DEVICE request
imx-usb imx-usb1: req=5 (0x5), type=0 (0x0), value=2, index=0
imx-usb imx-usb1: USB_REQ_SET_ADDRESS
imx-usb imx-usb1: Len is 0
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=256, index=0
imx-usb imx-usb1: USB_DT_DEVICE request
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=512, index=0
imx-usb imx-usb1: USB_DT_CONFIG config
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=512, index=0
imx-usb imx-usb1: USB_DT_CONFIG config
imx-usb imx-usb1: req=9 (0x9), type=0 (0x0), value=1, index=0
imx-usb imx-usb1: USB_REQ_SET_CONFIGURATION
imx-usb imx-usb1: Len is 0
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=768, index=0
imx-usb imx-usb1: USB_DT_STRING config
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=769, index=1
imx-usb imx-usb1: USB_DT_STRING config
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=770, index=1
imx-usb imx-usb1: USB_DT_STRING config
usb: Bus 002 Device 002: ID 0000:0000 EHCI Host Controller
imx-usb imx-usb1: req=6 (0x6), type=160 (0xa0), value=10496, index=0
imx-usb imx-usb1: USB_DT_HUB config
imx-usb imx-usb1: req=6 (0x6), type=160 (0xa0), value=10496, index=0
imx-usb imx-usb1: USB_DT_HUB config
imx-usb imx-usb1: req=0 (0x0), type=160 (0xa0), value=0, index=0
imx-usb imx-usb1: req=1 (0x1), type=35 (0x23), value=8, index=1
imx-usb imxb1:- usLen is 0
imx-usb imx-usb1: req=3 (0x3), type=35 (0x23), value=8, index=1
imx-usb imx-usb1: Len is 0
imx-usb imx-usb1: req=0 (0x0), type=163 (0x)a, 3value=0, index=1
usUb: 2 SB Device(s) found
barebox:/
but if I plug a usb device (usb memory stick) in the otg port:
barebox:/ usb
usb: USB: scanning bus for devices...
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=256, index=0
imx-usb imx-usb0: USB_DT_DEVICE request
imx-usb imx-usb0: req=5 (0x5), type=0 (0x0), value=1, index=0
imx-usb imx-usb0: USB_REQ_SET_ADDRESS
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=256, index=0
imx-usb imx-usb0: USB_DT_DEVICE request
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=512, index=0
imx-usb imx-usb0: USB_DT_CONFIG config
imx-usb imx-usb0: req=6 (0 typex6),=128 (0x80), value=512, nidex=0
imx-usb imx-usb0: USB_DT_CONFIG config
imx-usb imx-usb0: req=9 (0x9), type=0 (0x0), value=1, index=0
imx-usb imx-usb0: USB_REQ_SET_CONFIGURATION
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=6 (0x6), type=128 0(0x8), value=768, index=0
imx-usb imx-usb0: USB_DT_STRING config
imx-usb imx-usb0: req=6 (0x6)28, type= 1(0x80), value=769, index=1
imx-usb imx-usb0: USB_DT_STRING config
imx-usb imx-usb0: req=6 (0x6), type=128 (0x80), value=770, index=1
imx-usb imx-usb0: USB_DT_STRING config
usb: Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
imx-usb imx-usb0: req(=06x 6), type=160 (0xa0), value=10496, index=0
imx-usb imx-usb0: USB_DT_HUB config
imx-usb imx-usb0: req=6 (0x6), type=160 (0xa0), value=10496, index=0
imx-usb imx-usb0: USB_DT_HUB config
imx-usb imx-usb0: req=0 (0x0), type=160 (0xa0), value=0, index=0
imx-usb imx-usb0: req=1 (0x1), type=35 (0x23), value=8, index=1
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=3 (0x3), type=35 (0x23), va=lue8, index=1
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=0 (0x0), type=163 (0xa3), value=0, index=1
usb-hub usb1: usb_hub_port_connect_change: called. port 1, dev->speed: 3
imx-usb imx-usb0: req=0 (0x0), type=163 (0xa3), value=0, index=1
usb-hub usb1: portstatus 101, change 1
usb-hub usb1: portstatus 101, change 1, 12 Mb/s
imx-usb imx-usb0: req=1 (0x1), type=35 (0x23), value=16, index=1
imx-usb imx-usb0: Len is 0
usb-hub usb1: hub_port_reset: resetting port 1...
imx-usb imx-usb0: req=3 (0x3), type=35 (0x23), value=4, index=1
imx-usb imx-usb0: Len is 0
imx-usb imx-usb0: req=0 (0x0), type=163 (0xa3), value=0, index=1
usb-hub usb1: portstatus 101, change 13, 12 Mb/s
usb-hub usb1: STAT_C_CONNECTION = 1 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 0
usb-hub usb1: hub_port_reset: trace 1: go out here. portchange: 0x00000013, portstatus: 0x00000101
usb-hub usb1: cannot reset port 1!?
imx-usb imx-usb1: req=6 (0x6), type=128 l(ue=0x80), va256, index=0
imx-usb imx-usb1: USB_DT_DEVICE request
imx-usb imx-usb1: req=5 (0x5), type=0 (0x0), value=2, index=0
imx-usb imx-usb1: USB_REQ_SET_ADDRESS
imx-usb imx-usb1: Len is 0
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=256, ind
ex=0imx-usb imx-usb1: USB_DT_DEVICE request
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=512, index=0
imx-usb imx-usb1: USB_DT_CONFIG config
imx-usb imx-usb1: req=6 (0x ty6),pe=128 (0x80), value=512, index=0
imx-usb imx-usb1: USB_DT_CONFIG config
imx-usb imx-usb1: req=9 (0x9), type=0 (0x0), value=1, index=0
imx-usb imx-usb1: USB_REQ_SET_CONFIGURATION
imx-usb imx-usb1: Len is 0
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=768, index=0
imx-usb imx-usb1:B _USDT_STRING config
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80), value=769, index=1
imx-usb imx-usb1: USB_DT_STRING config
imx-usb imx-usb1: req=6 (0x6), type=128 (0x80),v alue=770, index=1
imx-usb imx-usb1: USB_DT_STRING config
usb: Bus 002 Device 002: ID 0000:0000 EHCI Host Controller
imx-usb imx-usb1: req=6 (0x6), type=160 (0xa0), value=10496, index=0
imx-usb imx-usb1: USB_DT_HUB config
imx-usb imx-usb1: req=6 (0x6), type=160 (0xa0), value=10496, index=0
imx-usb imx-usb1: USB_DT_HUB config
imx-usb imx-usb1: req=0 (0x0), type=160 (0xa0), value=0, index=0
imx-usb imx-usb1: req=1 (0x1), type=35 (0x23), value=8, index=1
imx-usb imx-usb1: Len is 0
imx-usb imx-usb1: req=3 (0x3), type=35 (0x23), value=8, index=1
imx-usb imx-usb1: Len is 0
imx-usb imx-usb1: req=0 (0x0), type=163 (0xa3), value=0, index=1
usb: 2 USB Device(s) found
barebox:/
I get a port reset error:
...
usb-hub usb1: cannot reset port 1!?
...
I added some trace dev_info's in the code and exactly found the failing test,
in the source file 'barebox/drivers/usb/core/hub.c':
int hub_port_reset(struct usb_device *dev, int port,
unsigned short *portstat)
{
...
if ((portchange & USB_PORT_STAT_C_CONNECTION) ||
!(portstatus & USB_PORT_STAT_CONNECTION)) {
dev_info(&dev->dev, "%s: trace 1: go out here. portchange: 0x%08x, portstatus: 0x%08x\n",
__func__, portchange, portstatus);
return -1;
}
if (portstatus & USB_PORT_STAT_ENABLE)
break;
mdelay(200);
...
The failing expression is (portchange & USB_PORT_STAT_C_CONNECTION).
On the other end I'm able to upload and start a barebox image with the tool 'imx-usb-loader',
so the usb otg related HW cannot be badly broken on my custom dev board.
My first basic question is if someone here in the list is also working with an imx25 and can confirm that
the usb otg is .
The second question is about the meaning of the failing expression, in case it could give a hint of
what goes wrong on my board.
thanks,
giorgio
Giorgio, iw3gtf@arcor.de
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^ permalink raw reply
* Re: [PATCH v3 2/3] watchdog: add designware driver
From: Sascha Hauer @ 2016-11-14 15:14 UTC (permalink / raw)
To: Steffen Trumtrar; +Cc: barebox
In-Reply-To: <20161017075052.30802-2-s.trumtrar@pengutronix.de>
On Mon, Oct 17, 2016 at 09:50:51AM +0200, Steffen Trumtrar wrote:
> Port the linux v4.8-rc1 Synopsys DesignWare watchdog driver to barebox.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
> +static void __noreturn dw_wdt_restart_handle(struct restart_handler *rst)
> +{
> + struct dw_wdt *dw_wdt;
> +
> + dw_wdt = container_of(rst, struct dw_wdt, restart);
> +
> + dw_wdt->wdd.set_timeout(&dw_wdt->wdd, -1);
> +
> + mdelay(1000);
> +
> + hang();
> +}
> +
> +static int dw_wdt_drv_probe(struct device_d *dev)
> +{
> + struct watchdog *wdd;
> + struct dw_wdt *dw_wdt;
> + struct resource *mem;
> + int ret;
> +
> + dw_wdt = xzalloc(sizeof(*dw_wdt));
> +
> + mem = dev_request_mem_resource(dev, 0);
> + dw_wdt->regs = IOMEM(mem->start);
> + if (IS_ERR(dw_wdt->regs))
> + return PTR_ERR(dw_wdt->regs);
Just stumbled upon this. The result of dev_request_mem_resource() must
be error checked, not the IOMEM(). If mem is valid then IOMEM() is valid
aswell.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* Re: Compiler issues
From: Jose Luis Zabalza @ 2016-11-15 5:32 UTC (permalink / raw)
To: Holger Schurig; +Cc: barebox
In-Reply-To: <87polymnlc.fsf@gmail.com>
Thanks for your reply, Holger.
I am sorry. I have to apologize for no mentioning that this thread is
the continuation of "Re: Configure RAM size on iMX53 board".
I will summarize the situation. I have a iMX53 custom board with two
versions, 512MB (only CS0) and 1GB (CS0 and CS1) RAM. Both versions
are running with same old uboot binary because uboot don't access to
high memory address. I write code for support Barebox on 1GB version
successfully but hangs on 512MB version. No messages are displayed on
console.
Sascha recomends me don't configure CS1 on DCD table and use
barebox_arm_entry() function instead of imx53_barebox_entry() but it
don't work.
So, the first step was find where the code hangs.
I activated a GPIO on DCD table and deactivate on Barebox code to know
if a function is executed.
==========<cut>===========
wm 32 0x53F84004 0x00000008 // Set GPIO as output
wm 32 0x53F84000 0x00000008 // Activate GPIO
...
*((unsigned *)0x53F84000)=0; // Deactivate GPIO
==========<cut>===========
With the trial and error method, I found the execution lack on
initcall secuence. Specifically don't reach myboard_initcall()
==========<cut>===========
static int myboard_init(void)
{
*((unsigned *)0x53F84000)=0;
imx_esdctl_disable();
arm_add_mem_device("ram0", MX53_CSD0_BASE_ADDR, SZ_512M);
return 0;
}
core_initcall(myboard_init);
==========<cut>===========
So I changed core_initcall() to pure_initcall() for early
myboard_init() execution and It was good but Barebox hangs on another
initcall function.
Next trial and error session I found imx_gpio_add() was not reached,
so I suspect it was a compiler problem or a timing problem. I
discarded the timing problem because It was very repetitive.
I changed -Os option with -O0 on Makefile. Now imx_gpio_add() are
executed Ok but net_init() hangs.
The final firework:
==========<cut barebox/net/net.c>===========
//
// this code don't deactivate the GPIO
//
static int net_init(void)
{
int i;
for (i = 0; i < PKTBUFSRX; i++)
NetRxPackets[i] = net_alloc_packet();
*((unsigned *)0x53F84000)=0;
==========<cut>===========
//
// This code YES. It deactivate the GPIO
//
static int net_init(void)
{
volatile int i;
for (i = 0; i < PKTBUFSRX; i++)
{
if(i > 10)
{
// this code is not executed because PKTBUFSRX is 4
}
NetRxPackets[i] = net_alloc_packet();
}
*((unsigned *)0x53F84000)=0;
==========<cut>===========
Now, the code hangs on other unknow initcall function but I think
that's not the problem.
Some idea?
Some dark compiler flag to de/activate ?
Thanks in advanced.
2016-11-14 10:12 GMT+01:00 Holger Schurig <holgerschurig@gmail.com>:
> Jose Luis Zabalza <jlz.3008@gmail.com> writes:
>
>> I continue to have problems with memory size but I suspect they may be
>> due to a compiler issue.
>
> I doubt it ... but what made you thinking this?
>
> (BTW, I'm using arm-linux-gnueabihf-gcc 4.9.2-10 from Debian for
> Barebox, Kernel and some userspace stuff)
>
>
> You should be more specific, e.g. what architecture are you using?
> How's your .config file? Maybe you simply deselect things there?
>
> Did you know that you can run "nm --size-sort barebox | tail" to find out what
> takes the most space?
>
>
> Holger
--
José Luis Zabalza
jlz.3008 a t gmail.com
Linux Counter 172551
https://linuxcounter.net/cert/172551.png
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* [PATCH 1/2] regmap: Add regmap_write_bits() function
From: Andrey Smirnov @ 2016-11-15 6:21 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add code implementing a simple version of regmap_write_bits().
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/base/regmap/regmap.c | 27 +++++++++++++++++++++++++++
include/regmap.h | 6 +++++-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index a042a1a..52b7d88 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -137,6 +137,33 @@ int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val)
}
/**
+ * regmap_write_bits - write bits of a register in a map
+ *
+ * @map: The map
+ * @reg: The register offset of the register
+ * @mask: Mask indicating bits to be modified
+ * (1 - modified, 0 - untouched)
+ * @val: Bit value to be set
+ *
+ * Returns 0 for success or negative error code on failure
+ */
+int regmap_write_bits(struct regmap *map, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ int ret;
+ unsigned int tmp, orig;
+
+ ret = regmap_read(map, reg, &orig);
+ if (ret != 0)
+ return ret;
+
+ tmp = orig & ~mask;
+ tmp |= val & mask;
+
+ return regmap_write(map, reg, tmp);
+}
+
+/**
* regmap_bulk_read(): Read data from the device
*
* @map: Register map to read from
diff --git a/include/regmap.h b/include/regmap.h
index bcbe6c1..9675a17 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -60,4 +60,8 @@ int regmap_get_val_bytes(struct regmap *map);
int regmap_get_max_register(struct regmap *map);
int regmap_get_reg_stride(struct regmap *map);
-#endif /* __REGMAP_H */
\ No newline at end of file
+int regmap_write_bits(struct regmap *map, unsigned int reg,
+ unsigned int mask, unsigned int val);
+
+
+#endif /* __REGMAP_H */
--
2.5.5
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* [PATCH 2/2] gpio: Port SX150x driver from Linux
From: Andrey Smirnov @ 2016-11-15 6:21 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
In-Reply-To: <1479190874-10392-1-git-send-email-andrew.smirnov@gmail.com>
Add a very abridged version of SX150x driver from Linux. New, "pinctrl"
version of the driver was used as a base. As it was already mentioned
this driver supports very limited amount of the original functionality,
and the following are the features that were dropped:
- Interrupt support
- Support for any chip other that SX150x (due to lack of HW to test
with)
- Any pinctlr-like functions: pull-up/pull-down, open-drain,
etc. configuration
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-sx150x.c | 274 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 283 insertions(+)
create mode 100644 drivers/gpio/gpio-sx150x.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index fe62778..434c568 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -124,6 +124,14 @@ config GPIO_DESIGNWARE
help
Say Y or M here to build support for the Synopsys DesignWare APB
GPIO block.
+
+config GPIO_SX150X
+ bool "Semtec SX150x I/O ports"
+ depends on I2C
+ help
+ Say Y here to build support for the Semtec Sx150x I2C GPIO
+ expander chip.
+
endmenu
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 248100f..7442c44 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
obj-$(CONFIG_GPIO_TEGRA) += gpio-tegra.o
obj-$(CONFIG_GPIO_DESIGNWARE) += gpio-dw.o
obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o
+obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
diff --git a/drivers/gpio/gpio-sx150x.c b/drivers/gpio/gpio-sx150x.c
new file mode 100644
index 0000000..7b8cfb5
--- /dev/null
+++ b/drivers/gpio/gpio-sx150x.c
@@ -0,0 +1,274 @@
+/*
+ * Driver for SX150x I2C GPIO expanders
+ *
+ * This code was ported from linux-4.9 kernel driver by
+ * Andrey Smirnov <andrew.smirnov@gmail.com>.
+ *
+ * Orginal code with it's copyright info can be found in
+ * drivers/pinctrl/pinctrl-sx150x.c
+ *
+ * Note: That although linux driver was converted from being a GPIO
+ * subsystem to Pinctrl subsytem driver, due to Barebox's lack of
+ * similar provisions this driver is still a GPIO driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <driver.h>
+#include <xfuncs.h>
+#include <errno.h>
+#include <i2c/i2c.h>
+#include <regmap.h>
+
+#include <gpio.h>
+#include <of_device.h>
+
+enum {
+ SX150X_123 = 0,
+ SX150X_456,
+ SX150X_789,
+};
+
+enum {
+ SX150X_MAX_REGISTER = 0xad,
+};
+
+struct sx150x_device_data {
+ u8 model;
+ u8 reg_dir;
+ u8 reg_data;
+ u8 ngpios;
+};
+
+struct sx150x_gpio {
+ struct device *dev;
+ struct i2c_client *client;
+ struct gpio_chip gpio;
+ struct regmap *regmap;
+ const struct sx150x_device_data *data;
+};
+
+static const struct sx150x_device_data sx1503q_device_data = {
+ .model = SX150X_123,
+ .reg_dir = 0x02,
+ .reg_data = 0x00,
+ .ngpios = 16,
+};
+
+static struct sx150x_gpio *to_sx150x_gpio(struct gpio_chip *gpio)
+{
+ return container_of(gpio, struct sx150x_gpio, gpio);
+}
+
+static int sx150x_gpio_get_direction(struct gpio_chip *gpio,
+ unsigned int offset)
+{
+ struct sx150x_gpio *sx150x = to_sx150x_gpio(gpio);
+ unsigned int value;
+ int ret;
+
+ ret = regmap_read(sx150x->regmap, sx150x->data->reg_dir, &value);
+ if (ret < 0)
+ return ret;
+
+ return !!(value & BIT(offset));
+}
+
+static int sx150x_gpio_get(struct gpio_chip *gpio, unsigned int offset)
+{
+ struct sx150x_gpio *sx150x = to_sx150x_gpio(gpio);
+ unsigned int value;
+ int ret;
+
+ ret = regmap_read(sx150x->regmap, sx150x->data->reg_data, &value);
+ if (ret < 0)
+ return ret;
+
+ return !!(value & BIT(offset));
+}
+
+static int __sx150x_gpio_set(struct sx150x_gpio *sx150x, unsigned int offset,
+ int value)
+{
+ return regmap_write_bits(sx150x->regmap, sx150x->data->reg_data,
+ BIT(offset), value ? BIT(offset) : 0);
+}
+
+
+static void sx150x_gpio_set(struct gpio_chip *gpio, unsigned int offset,
+ int value)
+{
+ __sx150x_gpio_set(to_sx150x_gpio(gpio), offset, value);
+}
+
+static int sx150x_gpio_direction_input(struct gpio_chip *gpio,
+ unsigned int offset)
+{
+ struct sx150x_gpio *sx150x = to_sx150x_gpio(gpio);
+
+ return regmap_write_bits(sx150x->regmap,
+ sx150x->data->reg_dir,
+ BIT(offset), BIT(offset));
+}
+
+static int sx150x_gpio_direction_output(struct gpio_chip *gpio,
+ unsigned int offset, int value)
+{
+ struct sx150x_gpio *sx150x = to_sx150x_gpio(gpio);
+ int ret;
+
+ ret = __sx150x_gpio_set(sx150x, offset, value);
+ if (ret < 0)
+ return ret;
+
+ return regmap_write_bits(sx150x->regmap,
+ sx150x->data->reg_dir,
+ BIT(offset), 0);
+}
+
+static int sx150x_regmap_reg_width(struct sx150x_gpio *sx150x,
+ unsigned int reg)
+{
+ return sx150x->data->ngpios;
+}
+
+/*
+ * In order to mask the differences between 16 and 8 bit expander
+ * devices we set up a sligthly ficticious regmap that pretends to be
+ * a set of 16-bit registers and transparently reconstructs those
+ * registers via multiple I2C/SMBus reads
+ *
+ * This way the rest of the driver code, interfacing with the chip via
+ * regmap API, can work assuming that each GPIO pin is represented by
+ * a group of bits at an offset proportioan to GPIO number within a
+ * given register.
+ *
+ */
+static int sx150x_regmap_reg_read(void *context, unsigned int reg,
+ unsigned int *result)
+{
+ int ret, n;
+ struct sx150x_gpio *sx150x = context;
+ struct i2c_client *i2c = sx150x->client;
+ const int width = sx150x_regmap_reg_width(sx150x, reg);
+ unsigned int idx, val;
+
+ /*
+ * There are four potential cases coverd by this function:
+ *
+ * 1) 8-pin chip, single configuration bit register
+ *
+ * This is trivial the code below just needs to read:
+ * reg [ 7 6 5 4 3 2 1 0 ]
+ *
+ * 2) 16-pin chip, single configuration bit register
+ *
+ * The read will be done as follows:
+ * reg [ f e d c b a 9 8 ]
+ * reg + 1 [ 7 6 5 4 3 2 1 0 ]
+ *
+ */
+
+ for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
+ val <<= 8;
+
+ ret = i2c_smbus_read_byte_data(i2c, idx);
+ if (ret < 0)
+ return ret;
+
+ val |= ret;
+ }
+
+ *result = val;
+
+ return 0;
+}
+
+static int sx150x_regmap_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ int ret, n;
+ struct sx150x_gpio *sx150x = context;
+ struct i2c_client *i2c = sx150x->client;
+ const int width = sx150x_regmap_reg_width(sx150x, reg);
+
+ n = width - 8;
+ do {
+ const u8 byte = (val >> n) & 0xff;
+
+ ret = i2c_smbus_write_byte_data(i2c, reg, byte);
+ if (ret < 0)
+ return ret;
+
+ reg++;
+ n -= 8;
+ } while (n >= 0);
+
+ return 0;
+}
+
+static const struct regmap_config sx150x_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 16,
+
+ .max_register = SX150X_MAX_REGISTER,
+};
+
+static const struct regmap_bus sx150x_regmap_bus = {
+ .reg_read = sx150x_regmap_reg_read,
+ .reg_write = sx150x_regmap_reg_write,
+};
+
+static struct gpio_ops sx150x_gpio_ops = {
+ .direction_input = sx150x_gpio_direction_input,
+ .direction_output = sx150x_gpio_direction_output,
+ .get_direction = sx150x_gpio_get_direction,
+ .get = sx150x_gpio_get,
+ .set = sx150x_gpio_set,
+};
+
+static int sx150x_probe(struct device_d *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct sx150x_gpio *sx150x;
+ const struct sx150x_device_data *data;
+
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ sx150x = xzalloc(sizeof(*sx150x));
+
+ sx150x->regmap = regmap_init(dev, &sx150x_regmap_bus,
+ sx150x, &sx150x_regmap_config);
+ sx150x->client = client;
+ sx150x->data = data;
+ sx150x->gpio.ops = &sx150x_gpio_ops;
+ sx150x->gpio.base = -1;
+ sx150x->gpio.ngpio = sx150x->data->ngpios;
+ sx150x->gpio.dev = &client->dev;
+
+ return gpiochip_add(&sx150x->gpio);
+}
+
+static __maybe_unused struct of_device_id sx150x_dt_ids[] = {
+ { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data, },
+ { }
+};
+
+static struct driver_d sx150x_driver = {
+ .name = "sx150x",
+ .probe = sx150x_probe,
+ .of_compatible = sx150x_dt_ids,
+};
+
+static int __init sx150x_init(void)
+{
+ return i2c_driver_register(&sx150x_driver);
+}
+device_initcall(sx150x_init);
--
2.5.5
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^ permalink raw reply related
* Re: Compiler issues
From: Andrey Smirnov @ 2016-11-15 6:34 UTC (permalink / raw)
To: Jose Luis Zabalza; +Cc: barebox@lists.infradead.org
In-Reply-To: <CAKZffXHoZX8Wrd+EEEp+5rHBMZVeK86vjSb1Cp5hC8=H4bkYVQ@mail.gmail.com>
On Mon, Nov 14, 2016 at 9:32 PM, Jose Luis Zabalza <jlz.3008@gmail.com> wrote:
> Thanks for your reply, Holger.
>
> I am sorry. I have to apologize for no mentioning that this thread is
> the continuation of "Re: Configure RAM size on iMX53 board".
>
> I will summarize the situation. I have a iMX53 custom board with two
> versions, 512MB (only CS0) and 1GB (CS0 and CS1) RAM. Both versions
> are running with same old uboot binary because uboot don't access to
> high memory address. I write code for support Barebox on 1GB version
> successfully but hangs on 512MB version. No messages are displayed on
> console.
>
> Sascha recomends me don't configure CS1 on DCD table and use
> barebox_arm_entry() function instead of imx53_barebox_entry() but it
> don't work.
>
> So, the first step was find where the code hangs.
>
> I activated a GPIO on DCD table and deactivate on Barebox code to know
> if a function is executed.
>
> ==========<cut>===========
> wm 32 0x53F84004 0x00000008 // Set GPIO as output
> wm 32 0x53F84000 0x00000008 // Activate GPIO
>
> ...
>
> *((unsigned *)0x53F84000)=0; // Deactivate GPIO
> ==========<cut>===========
>
> With the trial and error method, I found the execution lack on
> initcall secuence. Specifically don't reach myboard_initcall()
>
> ==========<cut>===========
> static int myboard_init(void)
> {
> *((unsigned *)0x53F84000)=0;
>
> imx_esdctl_disable();
>
> arm_add_mem_device("ram0", MX53_CSD0_BASE_ADDR, SZ_512M);
>
> return 0;
> }
> core_initcall(myboard_init);
> ==========<cut>===========
>
> So I changed core_initcall() to pure_initcall() for early
> myboard_init() execution and It was good but Barebox hangs on another
> initcall function.
>
> Next trial and error session I found imx_gpio_add() was not reached,
> so I suspect it was a compiler problem or a timing problem. I
> discarded the timing problem because It was very repetitive.
>
> I changed -Os option with -O0 on Makefile. Now imx_gpio_add() are
> executed Ok but net_init() hangs.
>
> The final firework:
>
> ==========<cut barebox/net/net.c>===========
> //
> // this code don't deactivate the GPIO
> //
> static int net_init(void)
> {
> int i;
>
> for (i = 0; i < PKTBUFSRX; i++)
> NetRxPackets[i] = net_alloc_packet();
>
> *((unsigned *)0x53F84000)=0;
>
> ==========<cut>===========
> //
> // This code YES. It deactivate the GPIO
> //
> static int net_init(void)
> {
> volatile int i;
>
> for (i = 0; i < PKTBUFSRX; i++)
> {
> if(i > 10)
> {
> // this code is not executed because PKTBUFSRX is 4
> }
>
> NetRxPackets[i] = net_alloc_packet();
> }
>
> *((unsigned *)0x53F84000)=0;
> ==========<cut>===========
>
> Now, the code hangs on other unknow initcall function but I think
> that's not the problem.
>
> Some idea?
> Some dark compiler flag to de/activate ?
That explanation is not very simple so it is unlikely to be true. If I
were to guess I'd say you are still having problems with RAM
boundaries calculation because what you describe reminds me of the
behavior I've observed many times when Barebox gets relocated such
that part of the image is placed into area that does not correspond to
RAM, so that some of the code is good and some of it is bad.
I would recommend configuring DEBUG_LL, instrumenting
barebox_arm_entry from entry.c to display membase and memsize and
making sure they fall within a valid region.
Hope this helps,
Andrey Smirnov
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^ permalink raw reply
* Re: [PATCH v2 09/28] clk: Port of_clk_set_defaults()
From: Sascha Hauer @ 2016-11-15 7:53 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
In-Reply-To: <1478708056-7875-10-git-send-email-andrew.smirnov@gmail.com>
On Wed, Nov 09, 2016 at 08:13:57AM -0800, Andrey Smirnov wrote:
> Port of_clk_set_defautls() from Linux kernel in order to support DT
> configurations that require it (e. g. Vybrid).
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> drivers/clk/Makefile | 2 +-
> drivers/clk/clk-conf.c | 144 +++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/clk.c | 2 +
> include/linux/clk/clk-conf.h | 14 +++++
> 4 files changed, 161 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/clk-conf.c
> create mode 100644 include/linux/clk/clk-conf.h
This patch breaks compilation on platforms using common clk but no
device tree, for example cupid_defconfig:
drivers/clk/clk-conf.c: In function '__set_clk_parents':
drivers/clk/clk-conf.c:41:3: error: implicit declaration of function 'of_clk_get_from_provider' [-Werror=implicit-function-declaration]
As this is not trivial to fix I dropped the rest of this series for now.
Sascha
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^ permalink raw reply
* Re: [PATCH] pcm049: Add 1 GByte RAM with DUAL DIE Single Rank
From: Sascha Hauer @ 2016-11-15 8:05 UTC (permalink / raw)
To: Maik Otto; +Cc: barebox
In-Reply-To: <1479116835-15439-1-git-send-email-m.otto@phytec.de>
On Mon, Nov 14, 2016 at 10:47:15AM +0100, Maik Otto wrote:
> tested with Micron MT42L128M64D2LL-25WT and MT42L128M64D2LL-25WT
>
> Signed-off-by: Maik Otto <m.otto@phytec.de>
> ---
> arch/arm/boards/phytec-phycore-omap4460/lowlevel.c | 32 +++++++++++++++++++-
> 1 files changed, 31 insertions(+), 1 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
> index c082594..71ab793 100644
> --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
> +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
> @@ -30,6 +30,13 @@
> #include <asm/barebox-arm-head.h>
>
> #define TPS62361_VSEL0_GPIO 182
> +#define LPDDR2_2G 0x5
> +#define LPDDR2_4G 0x6
> +#define LPDDR2_DENSITY_MASK 0x3C
> +#define LPDDR2_DENSITY_SHIFT 2
> +#define EMIF_SDRAM_CONFIG 0x0008
> +#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
> +#define EMIF_LPDDR2_MODE_REG_DATA 0x0040
>
> void set_muxconf_regs(void);
>
> @@ -61,8 +68,23 @@ static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = {
> .mr2 = 0x4
> };
>
> +static const struct ddr_regs ddr_regs_mt42L128M64D2LL_25_400_mhz = {
> + .tim1 = 0x10EB0662,
> + .tim2 = 0x205715D2,
> + .tim3 = 0x00B1C53F,
> + .phy_ctrl_1 = 0x849FF409,
> + .ref_ctrl = 0x00000618,
> + .config_init = 0x80001AB2,
> + .config_final = 0x80001AB2,
> + .zq_config = 0x500B3214,
> + .mr1 = 0x83,
> + .mr2 = 0x4
> +};
> +
> static void noinline pcm049_init_lowlevel(void)
> {
> + unsigned int density;
> +
> struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
> struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
> struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
> @@ -75,9 +97,17 @@ static void noinline pcm049_init_lowlevel(void)
> set_muxconf_regs();
>
> #ifdef CONFIG_1024MB_DDR2RAM
> + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
> + writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE +
> + EMIF_LPDDR2_MODE_REG_CONFIG);
> + density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) &
> + LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT;
> + if (density == LPDDR2_2G)
> omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);
> + else if (density == LPDDR2_4G)
> + omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core);
> #else
> - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
> + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
> #endif
>
> /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> --
> 1.7.0.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply
* [PATCH] state: Documentation updates
From: Sascha Hauer @ 2016-11-15 8:19 UTC (permalink / raw)
To: Barebox List; +Cc: Trostel Alain
From: Trostel Alain <Alain.Trostel@haslerrail.com>
Some improvements for the state binding documentation. These come
from the conversation with Trostel Alain who tried to use the
state framework and stumbled upon these things missing. Patch
originally by Alain, thanks.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../devicetree/bindings/barebox/barebox,state.rst | 39 +++++++++++++++++++---
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/barebox/barebox,state.rst b/Documentation/devicetree/bindings/barebox/barebox,state.rst
index 438cc43..7b9d1bb 100644
--- a/Documentation/devicetree/bindings/barebox/barebox,state.rst
+++ b/Documentation/devicetree/bindings/barebox/barebox,state.rst
@@ -43,6 +43,16 @@ Optional properties:
moment. For MTD with erasing the correct type is ``circular``. For all other
devices and files, ``direct`` is the needed type.
+Configuration
+-------------
+
+The following config options must be enabled when building the barebox image
+to have full support of the barebox state framework:
+
+* CONFIG_STATE
+* CONFIG_STATE_DRV
+* CONFIG_CMD_STATE
+
Variable nodes
--------------
@@ -71,13 +81,18 @@ Optional properties:
storage. For ``enum32`` values it is an integer representing an
offset into the names array.
-Example::
+The following examples have to be configured in the board-specific device
+tree files (\*.dts) within barebox.
- state: state@0 {
+State example::
+
+ state: state {
magic = <0x27031977>;
compatible = "barebox,state";
backend-type = "raw";
- backend = &eeprom, "partname:state";
+ backend = &part_state;
+ #address-cells = <1>;
+ #size-cells = <1>;
foo {
reg = <0x00 0x4>;
@@ -93,6 +108,13 @@ Example::
};
};
+Partition example::
+
+ part_state: partition@1C0000 {
+ label = "state";
+ reg = <0x1C0000 0x60000>;
+ };
+
Variable Types
--------------
@@ -139,4 +161,13 @@ be accessed like normal shell variables. The ``state`` command is used
to save/restore a state to the backend device.
After initializing the variable can be accessed with ``$state.foo``.
-``state -s`` stores the state to eeprom.
+``state -s`` stores the state persistently.
+
+From Linux
+----------
+
+It exists a tool called «barebox-state» to access these state variables
+from the Linux user-space. The mentioned tool is available as GIT project
+under the following location::
+
+ git://git.pengutronix.de/git/tools/dt-utils.git
--
2.10.2
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^ permalink raw reply related
* [PATCH] ARM: i.MX: Add src fixup
From: Sascha Hauer @ 2016-11-15 9:08 UTC (permalink / raw)
To: Barebox List
Some boards or SoCs need the SRC_SCR[WARM_RESET_ENABLE] bit cleared,
otherwise they won't come up after a watchdog reset. This was observed
on one i.MX6ul based custom board. The Linux Kernel does the same since
2012: 0575fb7 ARM: 7198/1: arm/imx6: add restart support for imx6q.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Kconfig | 4 ++++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/src.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/reset/Kconfig | 4 ++++
4 files changed, 66 insertions(+)
create mode 100644 arch/arm/mach-imx/src.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index d571faa..5eec639 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -81,6 +81,10 @@ config BAREBOX_UPDATE_IMX_EXTERNAL_NAND
depends on MTD_WRITE
default y
+config RESET_IMX_SRC
+ bool "i.MX SRC support"
+ default y if ARCH_IMX6 || ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53
+
comment "Freescale i.MX System-on-Chip"
config ARCH_IMX1
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9922fed..22d903c 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -25,5 +25,6 @@ obj-y += devices.o imx.o
obj-pbl-y += esdctl.o boot.o
obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
+obj-$(CONFIG_RESET_IMX_SRC) += src.o
lwl-y += cpu_init.o
pbl-y += xload-spi.o xload-esdhc.o xload-common.o
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
new file mode 100644
index 0000000..73350d1
--- /dev/null
+++ b/arch/arm/mach-imx/src.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2016 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <linux/err.h>
+
+#define SRC_SCR 0x0
+
+#define SCR_WARM_RESET_ENABLE BIT(0)
+
+static int imx_src_reset_probe(struct device_d *dev)
+{
+ struct resource *res;
+ u32 val;
+ void __iomem *membase;
+
+ res = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(res))
+ return PTR_ERR(res);
+
+ membase = IOMEM(res->start);
+
+ /*
+ * Generate cold reset for warm reset sources. Needed for
+ * some boards to come up properly after reset.
+ */
+ val = readl(membase + SRC_SCR);
+ val &= ~SCR_WARM_RESET_ENABLE;
+ writel(val, membase + SRC_SCR);
+
+ return 0;
+}
+
+static const struct of_device_id imx_src_dt_ids[] = {
+ { .compatible = "fsl,imx51-src", },
+ { /* sentinel */ },
+};
+
+static struct driver_d imx_src_reset_driver = {
+ .name = "imx-src",
+ .probe = imx_src_reset_probe,
+ .of_compatible = DRV_OF_COMPAT(imx_src_dt_ids),
+};
+
+static int imx_src_reset_init(void)
+{
+ return platform_driver_register(&imx_src_reset_driver);
+}
+postcore_initcall(imx_src_reset_init);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c9d04f7..71a13b5 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -11,3 +11,7 @@ menuconfig RESET_CONTROLLER
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
+
+config RESET_IMX_SRC
+ bool "i.MX SRC support"
+ default y if ARCH_IMX6 || ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53
--
2.10.2
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^ permalink raw reply related
* Re: usb otg port not working on an imx25 soc
From: Sascha Hauer @ 2016-11-15 13:35 UTC (permalink / raw)
To: iw3gtf; +Cc: barebox
In-Reply-To: <1823762258.78822.1479128237871.JavaMail.ngmail@webmail06.arcor-online.net>
Hi Giorgio,
On Mon, Nov 14, 2016 at 01:57:17PM +0100, iw3gtf@arcor.de wrote:
> Hi,
>
> I'm currently working on an embedded board with an imx25 soc and I want
> to enable the usb otg port of the soc; in my use case I just want the otg port
> to be configured in usb host mode and use the integrated UTMI phy.
>
> I built barebox with usb support and the usb ports are actually found:
When USB does not work it's most likely that the usbmisc unit is not
properly configured. Have a look at mx25_initialize_usb_hw(). If you
previously loaded barebox with imx-usb-loader then you could try skipping
the initialization in mx25_initialize_usb_hw() completely.
I've seldomly seen that the actual EHCI driver or USB core is the
problem when no device is detected.
Sascha
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^ permalink raw reply
* [PATCH] commands: i2c: Listen for CTRL-C when probing
From: Andrey Smirnov @ 2016-11-15 14:46 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Allow I2C bus probing to be interrupted early by sending CTRL-C. This is
usefull when calling the tool without any arguments and one of the busses
is misconfigured (waiting for 100+ failures is pretty inconvenient).
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
commands/i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/commands/i2c.c b/commands/i2c.c
index ae7f7fc..573032a 100644
--- a/commands/i2c.c
+++ b/commands/i2c.c
@@ -32,7 +32,7 @@ static void i2c_probe_range(struct i2c_adapter *adapter, int startaddr, int stop
client.adapter = adapter;
printf("probing i2c%d range 0x%02x-0x%02x: ", adapter->nr, startaddr, stopaddr);
- for (addr = startaddr; addr <= stopaddr; addr++) {
+ for (addr = startaddr; addr <= stopaddr && !ctrlc(); addr++) {
client.addr = addr;
ret = i2c_write_reg(&client, 0x00, ®, 0);
if (ret == 0)
--
2.5.5
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^ permalink raw reply related
* [PATCH] i2c-mux-pca954x: Add code to control reset line
From: Andrey Smirnov @ 2016-11-15 14:46 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Most recent device tree binding for that mux support specifying a GPIO
connected to a reset line of that chip. Add code to handle that binding
in order to be able to use the chip on boards that leverage
aforementioned functionality.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/i2c/muxes/i2c-mux-pca954x.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index baeae7b..0d5515b 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -45,6 +45,8 @@
#include <i2c/i2c-algo-bit.h>
#include <i2c/i2c-mux.h>
#include <init.h>
+#include <gpio.h>
+#include <of_gpio.h>
#define PCA954X_MAX_NCHANS 8
@@ -179,6 +181,7 @@ static int pca954x_probe(struct device_d *dev)
int num, force;
struct pca954x *data;
int ret = -ENODEV;
+ int gpio;
data = kzalloc(sizeof(struct pca954x), GFP_KERNEL);
if (!data) {
@@ -188,6 +191,10 @@ static int pca954x_probe(struct device_d *dev)
i2c_set_clientdata(client, data);
+ gpio = of_get_named_gpio(dev->device_node, "reset-gpios", 0);
+ if (gpio_is_valid(gpio))
+ gpio_direction_output(gpio, 1);
+
/* Read the mux register at addr to verify
* that the mux is in fact present.
*/
--
2.5.5
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* [PATCH 1/2] fixup! pinctrl: Add provisions to control GPIO pin direction
From: Andrey Smirnov @ 2016-11-15 16:22 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
---
Sascha:
These two are fixup for issues in my Vybrid patch series, patch #2 is
for the issue you experienced and this one is for another issue I
found when building cupid_defconfig.
If you'd rather I post v3 version of the patchset with all of this
incorporated, let me know.
Thanks,
Andrey
include/pinctrl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/pinctrl.h b/include/pinctrl.h
index 0fde3f9..7d87169 100644
--- a/include/pinctrl.h
+++ b/include/pinctrl.h
@@ -49,7 +49,7 @@ static inline int of_pinctrl_select_state_default(struct device_node *np)
return -ENODEV;
}
-static inline int pinctrl_gpio_direction_input(unsigend pin)
+static inline int pinctrl_gpio_direction_input(unsigned pin)
{
return -ENOTSUPP;
}
--
2.5.5
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* [PATCH 2/2] fixup! clk: Port of_clk_set_defaults()
From: Andrey Smirnov @ 2016-11-15 16:22 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
In-Reply-To: <1479226976-12563-1-git-send-email-andrew.smirnov@gmail.com>
---
drivers/clk/clk-conf.c | 4 ++++
include/linux/clk/clk-conf.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 961fad8..93271b4 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -14,6 +14,8 @@
#include <linux/err.h>
#include <linux/clk/clk-conf.h>
+#if defined(CONFIG_OFTREE) && defined(CONFIG_COMMON_CLK_OF_PROVIDER)
+
static int __set_clk_parents(struct device_node *node, bool clk_supplier)
{
struct of_phandle_args clkspec;
@@ -142,3 +144,5 @@ int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
return __set_clk_rates(node, clk_supplier);
}
EXPORT_SYMBOL_GPL(of_clk_set_defaults);
+
+#endif
diff --git a/include/linux/clk/clk-conf.h b/include/linux/clk/clk-conf.h
index 0b8a973..8f4382e 100644
--- a/include/linux/clk/clk-conf.h
+++ b/include/linux/clk/clk-conf.h
@@ -7,8 +7,11 @@
* published by the Free Software Foundation.
*/
+#if defined(CONFIG_OFTREE) && defined(CONFIG_COMMON_CLK_OF_PROVIDER)
+
#include <linux/types.h>
struct device_node;
int of_clk_set_defaults(struct device_node *node, bool clk_supplier);
+#endif
--
2.5.5
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