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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bcac4358cedsm87169366b.47.2026.05.08.07.03.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 May 2026 07:03:42 -0700 (PDT) Message-ID: <01d6ea18-e022-41c7-a642-ac0321957923@oss.qualcomm.com> Date: Fri, 8 May 2026 16:03:36 +0200 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 12/12] arm64: dts: qcom: qcs6490-rb3gen2: enable TC9564 with a single QCS8081 phy To: Alex Elder , andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com, rmk+kernel@armlinux.org.uk, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org Cc: Daniel Thompson , mohd.anwar@oss.qualcomm.com, a0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org, boon.khai.ng@altera.com, chenchuangyu@xiaomi.com, chenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org, hkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com, julianbraha@gmail.com, livelycarpet87@gmail.com, matthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc, prabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com, rohan.g.thomas@altera.com, sdf@fomichev.me, siyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com, wens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260501155421.3329862-1-elder@riscstar.com> <20260501155421.3329862-13-elder@riscstar.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260501155421.3329862-13-elder@riscstar.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Dc0nbPtW c=1 sm=1 tr=0 ts=69fded42 cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=ee_2aqc6AAAA:8 a=lW0hg0oAPnnF6MRRTAsA:9 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 a=VOpmJXOdbJOWo2YY3GeN:22 X-Proofpoint-GUID: dJ-Yxtn3uazOcPU-vgclhW44tN3-1vKU X-Proofpoint-ORIG-GUID: dJ-Yxtn3uazOcPU-vgclhW44tN3-1vKU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDE0MiBTYWx0ZWRfX31amQLgyZ/rv KnYDU/mJOhpE6sFTBzWlFWYWDYnM8dx/7SSK2ZRU79BcrJzYjAg/T8tcrov9yReXTRaIj3A5NWw tKH1jRHjf4tpHEdJNf+kJhM8n/CZ0Dr7tCfY8P3S2LiYdJ4Ec8ihKTI51GXc5r3r2spIFqfgCOr gldswqAGfYOFUbKN67eCPZ79qI/WbrYBQGb5xdcRZoQkccYg4cDLyQHEA5TqtgBjXIW0MWkP/JE eHaZfv/oR5mkdh658TxHXcVYEW/Z552jzz9nhko5319C3XAqKdoHkxMeLH2tD7/9K8bBl0coUy9 1xxcly57NaKIFL+YhWYy/OjxtpziXXwT4K/Cma+wldP+FkiHVXKPdhCtzXP8ZIZOTXodOinc+wE o06zsZjioHHmGFehZFV2XzhgSliIMi0HQ1BgImUHzGCZaqKV+o74wvz6u4EdOikxSQML09sXchM UL9bYRuEmxhy+lZZEag== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1011 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080142 On 5/1/26 5:54 PM, Alex Elder wrote: > From: Daniel Thompson > > The QCS6490 RB3Gen2 includes a Toshiba TC9564 (a.k.a. Qualcomm QPS615). > TC9564 is an twin Ethernet-AVB/TSN bridge with an integrated PCIe switch. > > There are multiple builds of RB3Gen2 with components included/excluded. > That means whether or not there is a phy attached to eMAC0 depends on > the exact board. However all versions include a TC9564 combined with a > single QCS8081 attached to eMAC1. > > Add properties to the existing PCI nodes to describe how the TC9564 and > QCS8081 are connected to each other (and to the host SoC). > > (Note: "pci1179,0220" is documented in the "net/toshiba,tc956x-dwmac.yaml" > binding, but checkpatch.pl doesn't recognize that.) This should probably go under the --- line [...] > + qep_1p8: regulator-qep-1p8 { > + compatible = "regulator-fixed"; > + regulator-name = "qep_1p8"; > + gpio = <&pm7325_gpios 8 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + enable-active-high; > + regulator-always-on; > + }; If I'm reading the schematics right, this is only required for the PHY - is it collapsible, or does it really need to be a-on? [...] > + qep_irq_pin: qep-irq-state { > + pins = "gpio101"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; There's no pull-up onboard, should we use the on-chip one? Konrad