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Wed, 3 Sep 2025 08:06:45 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5CCE92004B; Wed, 3 Sep 2025 08:06:45 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EBD7B20040; Wed, 3 Sep 2025 08:06:44 +0000 (GMT) Received: from [9.152.212.92] (unknown [9.152.212.92]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 3 Sep 2025 08:06:44 +0000 (GMT) Message-ID: <03b13088-8dae-4d68-8594-6523b4aee406@linux.ibm.com> Date: Wed, 3 Sep 2025 10:06:44 +0200 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 00/15] Legacy hardware/cache events as json To: Ian Rogers , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver References: <20250828205930.4007284-1-irogers@google.com> Content-Language: en-US From: Thomas Richter Organization: IBM In-Reply-To: <20250828205930.4007284-1-irogers@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=behrUPPB c=1 sm=1 tr=0 ts=68b7f718 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=1XWaLZrsAAAA:8 a=h0uksLzaAAAA:8 a=7CQSdrXTAAAA:8 a=VnNF1IyMAAAA:8 a=KByoUL483hSIROooWq4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=MSi_79tMYmZZG2gvAgS0:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: y5jHuvcz1AvdARQJzfuyJqumQ_eV1ZXa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAzNCBTYWx0ZWRfX1kek//mDJGNd TmMxhEX7iwrmfwBFMFWnTVNlXuoKChTkUkqA78axxAm43Flnt5eW7uUGaRh0GLgUpBVY+0WaX3J 5KWn5Jl0UkjswVxxqzL9nZBleXR3cfH7wtclGw6Bk0R5Szk2lY+/MzOf8N+3EfsRemld13Ql9hk RVN5qr/hLKlxZKvwMzYXEfik1cd4BiPmJ/L/t8BkyWa+9ZihmqFUPglPO8OJ1maoecGUmt/Z92g SgjZ1KHXARlYmYFmnPYn0BopVW9kXg809Lnetz7AEX4wAeS1TKdu0XoOU1kbNzNW5Th9Eh85dOC Z6d0EMDCbkCBHLqPrHLK6OfiTYYcrIF/pQow2VoSGrlDAfGouwkLgOiy0EWRdFDL7fmIVf3+9og L6Vw68VN X-Proofpoint-GUID: cjcZczKn9cVb7gI_Smn-YkYgwY_C4PT9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_04,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 spamscore=0 clxscore=1011 phishscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300034 On 8/28/25 22:59, Ian Rogers wrote: > Mirroring similar work for software events in commit 6e9fa4131abb > ("perf parse-events: Remove non-json software events"). These changes > migrate the legacy hardware and cache events to json. With no hard > coded legacy hardware or cache events the wild card, case > insensitivity, etc. is consistent for events. This does, however, mean > events like cycles will wild card against all PMUs. A change doing the > same was originally posted and merged from: > https://lore.kernel.org/r/20240416061533.921723-10-irogers@google.com > and reverted by Linus in commit 4f1b067359ac ("Revert "perf > parse-events: Prefer sysfs/JSON hardware events over legacy"") due to > his dislike for the cycles behavior on ARM with perf record. Earlier > patches in this series make perf record event opening failures > non-fatal and hide the cycles event's failure to open on ARM in perf > record, so it is expected the behavior will now be transparent in perf > record on ARM. perf stat with a cycles event will wildcard open the > event on all PMUs. > > The change to support legacy events with PMUs was done to clean up > Intel's hybrid PMU implementation. Having sysfs/json events with > increased priority to legacy was requested by Mark Rutland > to fix Apple-M PMU issues wrt broken legacy > events on that PMU. It is believed the PMU driver is now fixed, but > this has only been confirmed on ARM Juno boards. It was requested that > RISC-V be able to add events to the perf tool json so the PMU driver > didn't need to map legacy events to config encodings: > https://lore.kernel.org/lkml/20240217005738.3744121-1-atishp@rivosinc.com/ > This patch series achieves this. > > A previous series of patches decreasing legacy hardware event > priorities was posted in: > https://lore.kernel.org/lkml/20250416045117.876775-1-irogers@google.com/ > Namhyung Kim mentioned that hardware and > software events can be implemented similarly: > https://lore.kernel.org/lkml/aIJmJns2lopxf3EK@google.com/ > and this patch series achieves this. > > Note, patch 1 (perf parse-events: Fix legacy cache events if event is > duplicated in a PMU) fixes a function deleted by patch 15 (perf > parse-events: Remove hard coded legacy hardware and cache > parsing). Adding the json exposed an issue when legacy cache (not > legacy hardware) and sysfs/json events exist. The fix is necessary to > keep tests passing through the series. It is also posted for backports > to stable trees. > > The perf list behavior includes a lot more information and events. The > before behavior on a hybrid alderlake is: ..... For s390 the whole series: Tested-by: Thomas Richter -- Thomas Richter, Dept 3303, IBM s390 Linux Development, Boeblingen, Germany -- IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Wolfgang Wendt Geschäftsführung: David Faller Sitz der Gesellschaft: Böblingen / Registergericht: Amtsgericht Stuttgart, HRB 243294