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From: dthaler1968@googlemail.com
To: "'Alexei Starovoitov'" <alexei.starovoitov@gmail.com>
Cc: "'bpf'" <bpf@vger.kernel.org>, <bpf@ietf.org>
Subject: RE: [PATCH bpf-next] bpf, docs: Clarify PC use in instruction-set.rst
Date: Fri, 26 Apr 2024 12:30:41 -0700	[thread overview]
Message-ID: <0dae01da9810$3a657fc0$af307f40$@gmail.com> (raw)
In-Reply-To: <CAADnVQLmu-v30D=JP75Cd0qBhDXm8izAnUnyZZ4-QwyM67nNww@mail.gmail.com>

> -----Original Message-----
> From: Alexei Starovoitov <alexei.starovoitov@gmail.com>
> Sent: Friday, April 26, 2024 12:22 PM
> To: Dave Thaler <dthaler1968@googlemail.com>
> Cc: bpf <bpf@vger.kernel.org>; bpf@ietf.org; Dave Thaler
> <dthaler1968@gmail.com>
> Subject: Re: [PATCH bpf-next] bpf, docs: Clarify PC use in instruction-set.rst
> 
> On Fri, Apr 26, 2024 at 10:11 AM Dave Thaler <dthaler1968@googlemail.com>
> wrote:
> >
> > This patch elaborates on the use of PC by expanding the PC acronym,
> > explaining the units, and the relative position to which the offset
> > applies.
> >
> > Signed-off-by: Dave Thaler <dthaler1968@googlemail.com>
> > ---
> >  Documentation/bpf/standardization/instruction-set.rst | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/Documentation/bpf/standardization/instruction-set.rst
> > b/Documentation/bpf/standardization/instruction-set.rst
> > index b44bdacd0..5592620cf 100644
> > --- a/Documentation/bpf/standardization/instruction-set.rst
> > +++ b/Documentation/bpf/standardization/instruction-set.rst
> > @@ -469,6 +469,11 @@ JSLT      0xc    any      PC += offset if dst < src
> signed
> >  JSLE      0xd    any      PC += offset if dst <= src         signed
> >  ========  =====  =======  =================================
> > ===================================================
> >
> > +where 'PC' denotes the program counter, and the offset to increment
> > +by is in units of 64-bit instructions relative to the instruction
> > +following the jump instruction.  Thus 'PC += 1' results in the next
> > +instruction to execute being two 64-bit instructions later.
> 
> The last part is confusing.
> "two 64-bit instructions later"
> I'm struggling to understand that.
> Maybe say that 'PC += 1' skips execution of the next insn?

If the next instruction is a 64-bit immediate instruction
that spans 128 bits, do you need PC += 1 or PC += 2 to skip it?
I assumed you'd need PC += 2, in which case "PC += 1" would
not skip execution of "the next instruction" but would try to jump 
into mid instruction, and fail verification.
Hence my attempt at "64-bit instruction" wording.

Alternate wording suggestions welcome.

Dave



WARNING: multiple messages have this Message-ID (diff)
From: dthaler1968=40googlemail.com@dmarc.ietf.org
To: "'Alexei Starovoitov'" <alexei.starovoitov@gmail.com>
Cc: "'bpf'" <bpf@vger.kernel.org>, <bpf@ietf.org>
Subject: Re: [Bpf] [PATCH bpf-next] bpf, docs: Clarify PC use in instruction-set.rst
Date: Fri, 26 Apr 2024 12:30:41 -0700	[thread overview]
Message-ID: <0dae01da9810$3a657fc0$af307f40$@gmail.com> (raw)
Message-ID: <20240426193041.pnTLXB6lPkUrAXgbbAjCk2MYA4b5GVDl_tOGrR9L1w8@z> (raw)
In-Reply-To: <CAADnVQLmu-v30D=JP75Cd0qBhDXm8izAnUnyZZ4-QwyM67nNww@mail.gmail.com>

> -----Original Message-----
> From: Alexei Starovoitov <alexei.starovoitov@gmail.com>
> Sent: Friday, April 26, 2024 12:22 PM
> To: Dave Thaler <dthaler1968@googlemail.com>
> Cc: bpf <bpf@vger.kernel.org>; bpf@ietf.org; Dave Thaler
> <dthaler1968@gmail.com>
> Subject: Re: [PATCH bpf-next] bpf, docs: Clarify PC use in instruction-set.rst
> 
> On Fri, Apr 26, 2024 at 10:11 AM Dave Thaler <dthaler1968@googlemail.com>
> wrote:
> >
> > This patch elaborates on the use of PC by expanding the PC acronym,
> > explaining the units, and the relative position to which the offset
> > applies.
> >
> > Signed-off-by: Dave Thaler <dthaler1968@googlemail.com>
> > ---
> >  Documentation/bpf/standardization/instruction-set.rst | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/Documentation/bpf/standardization/instruction-set.rst
> > b/Documentation/bpf/standardization/instruction-set.rst
> > index b44bdacd0..5592620cf 100644
> > --- a/Documentation/bpf/standardization/instruction-set.rst
> > +++ b/Documentation/bpf/standardization/instruction-set.rst
> > @@ -469,6 +469,11 @@ JSLT      0xc    any      PC += offset if dst < src
> signed
> >  JSLE      0xd    any      PC += offset if dst <= src         signed
> >  ========  =====  =======  =================================
> > ===================================================
> >
> > +where 'PC' denotes the program counter, and the offset to increment
> > +by is in units of 64-bit instructions relative to the instruction
> > +following the jump instruction.  Thus 'PC += 1' results in the next
> > +instruction to execute being two 64-bit instructions later.
> 
> The last part is confusing.
> "two 64-bit instructions later"
> I'm struggling to understand that.
> Maybe say that 'PC += 1' skips execution of the next insn?

If the next instruction is a 64-bit immediate instruction
that spans 128 bits, do you need PC += 1 or PC += 2 to skip it?
I assumed you'd need PC += 2, in which case "PC += 1" would
not skip execution of "the next instruction" but would try to jump 
into mid instruction, and fail verification.
Hence my attempt at "64-bit instruction" wording.

Alternate wording suggestions welcome.

Dave


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  parent reply	other threads:[~2024-04-26 19:30 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-26 17:11 [PATCH bpf-next] bpf, docs: Clarify PC use in instruction-set.rst Dave Thaler
2024-04-26 17:11 ` [Bpf] " Dave Thaler
2024-04-26 19:21 ` Alexei Starovoitov
2024-04-26 19:21   ` [Bpf] " Alexei Starovoitov
2024-04-26 19:30   ` dthaler1968 [this message]
2024-04-26 19:30     ` dthaler1968=40googlemail.com
2024-04-26 19:36     ` Alexei Starovoitov
2024-04-26 19:36       ` [Bpf] " Alexei Starovoitov

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