From: Jiong Wang <jiong.wang@netronome.com>
To: alexei.starovoitov@gmail.com, daniel@iogearbox.net
Cc: bpf@vger.kernel.org, netdev@vger.kernel.org,
oss-drivers@netronome.com,
"Jiong Wang" <jiong.wang@netronome.com>,
"Björn Töpel" <bjorn.topel@gmail.com>
Subject: [PATCH/RFC v2 bpf-next 18/19] riscv: bpf: eliminate zero extension code-gen
Date: Wed, 10 Apr 2019 20:50:32 +0100 [thread overview]
Message-ID: <1554925833-7333-19-git-send-email-jiong.wang@netronome.com> (raw)
In-Reply-To: <1554925833-7333-1-git-send-email-jiong.wang@netronome.com>
CC: Björn Töpel <bjorn.topel@gmail.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
---
arch/riscv/net/bpf_jit_comp.c | 32 +++++++++++++++++++-------------
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/net/bpf_jit_comp.c b/arch/riscv/net/bpf_jit_comp.c
index 80b12aa..9cba262 100644
--- a/arch/riscv/net/bpf_jit_comp.c
+++ b/arch/riscv/net/bpf_jit_comp.c
@@ -731,6 +731,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
{
bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 ||
BPF_CLASS(insn->code) == BPF_JMP;
+ struct bpf_prog_aux *aux = ctx->prog->aux;
int rvoff, i = insn - ctx->prog->insnsi;
u8 rd = -1, rs = -1, code = insn->code;
s16 off = insn->off;
@@ -743,7 +744,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
case BPF_ALU | BPF_MOV | BPF_X:
case BPF_ALU64 | BPF_MOV | BPF_X:
emit(is64 ? rv_addi(rd, rs, 0) : rv_addiw(rd, rs, 0), ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
@@ -771,19 +772,19 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
case BPF_ALU | BPF_MUL | BPF_X:
case BPF_ALU64 | BPF_MUL | BPF_X:
emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_DIV | BPF_X:
case BPF_ALU64 | BPF_DIV | BPF_X:
emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_MOD | BPF_X:
case BPF_ALU64 | BPF_MOD | BPF_X:
emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_LSH | BPF_X:
@@ -867,7 +868,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
case BPF_ALU | BPF_MOV | BPF_K:
case BPF_ALU64 | BPF_MOV | BPF_K:
emit_imm(rd, imm, ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
@@ -882,7 +883,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit(is64 ? rv_add(rd, rd, RV_REG_T1) :
rv_addw(rd, rd, RV_REG_T1), ctx);
}
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_SUB | BPF_K:
@@ -895,7 +896,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit(is64 ? rv_sub(rd, rd, RV_REG_T1) :
rv_subw(rd, rd, RV_REG_T1), ctx);
}
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_AND | BPF_K:
@@ -906,7 +907,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_imm(RV_REG_T1, imm, ctx);
emit(rv_and(rd, rd, RV_REG_T1), ctx);
}
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_OR | BPF_K:
@@ -917,7 +918,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_imm(RV_REG_T1, imm, ctx);
emit(rv_or(rd, rd, RV_REG_T1), ctx);
}
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_XOR | BPF_K:
@@ -928,7 +929,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_imm(RV_REG_T1, imm, ctx);
emit(rv_xor(rd, rd, RV_REG_T1), ctx);
}
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_MUL | BPF_K:
@@ -936,7 +937,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_imm(RV_REG_T1, imm, ctx);
emit(is64 ? rv_mul(rd, rd, RV_REG_T1) :
rv_mulw(rd, rd, RV_REG_T1), ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_DIV | BPF_K:
@@ -944,7 +945,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_imm(RV_REG_T1, imm, ctx);
emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :
rv_divuw(rd, rd, RV_REG_T1), ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_MOD | BPF_K:
@@ -952,7 +953,7 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_imm(RV_REG_T1, imm, ctx);
emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :
rv_remuw(rd, rd, RV_REG_T1), ctx);
- if (!is64)
+ if (!is64 && aux->no_verifier_zext)
emit_zext_32(rd, ctx);
break;
case BPF_ALU | BPF_LSH | BPF_K:
@@ -1503,6 +1504,11 @@ static void bpf_flush_icache(void *start, void *end)
flush_icache_range((unsigned long)start, (unsigned long)end);
}
+bool bpf_jit_hardware_zext(void)
+{
+ return false;
+}
+
struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
{
bool tmp_blinded = false, extra_pass = false;
--
2.7.4
next prev parent reply other threads:[~2019-04-10 19:51 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 19:50 [PATCH/RFC v2 bpf-next 00/19] bpf: eliminate zero extensions for sub-register writes Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 01/19] bpf: refactor propagate_liveness to eliminate duplicated for loop Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 02/19] bpf: refactor propagate_liveness to eliminate code redundance Jiong Wang
2019-04-11 2:39 ` [oss-drivers] " Jakub Kicinski
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 03/19] bpf: factor out reg and stack slot propagation into "propagate_liveness_reg" Jiong Wang
2019-04-11 2:39 ` [oss-drivers] " Jakub Kicinski
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 04/19] bpf: refactor "check_reg_arg" to eliminate code redundancy Jiong Wang
2019-04-11 2:40 ` Jakub Kicinski
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 05/19] bpf: split read liveness into REG_LIVE_READ64 and REG_LIVE_READ32 Jiong Wang
2019-04-11 2:52 ` Jakub Kicinski
2019-04-11 6:13 ` Jiong Wang
2019-04-11 16:44 ` [oss-drivers] " Jakub Kicinski
2019-04-11 16:53 ` Jiong Wang
2019-04-12 16:14 ` Jiong Wang
2019-04-11 17:22 ` Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 06/19] bpf: mark lo32 writes that should be zero extended into hi32 Jiong Wang
2019-04-11 3:13 ` Jakub Kicinski
2019-04-11 6:02 ` Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 07/19] bpf: reduce false alarm by refining helper call arg types Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 08/19] bpf: insert explicit zero extension insn when hardware doesn't do it implicitly Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 09/19] bpf: introduce new bpf prog load flags "BPF_F_TEST_RND_HI32" Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 10/19] bpf: randomize high 32-bit when BPF_F_TEST_RND_HI32 is set Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 11/19] libbpf: new global variable "libbpf_test_mode" Jiong Wang
2019-04-11 3:19 ` Jakub Kicinski
2019-04-11 14:32 ` Jiong Wang
2019-04-11 21:49 ` Jiong Wang
2019-04-12 22:08 ` Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 12/19] selftests: enable hi32 randomization for "test_progs" and "test_verifier" Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 13/19] arm: bpf: eliminate zero extension code-gen Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 14/19] powerpc: " Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 15/19] s390: " Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 16/19] sparc: " Jiong Wang
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 17/19] x32: " Jiong Wang
2019-04-10 19:50 ` Jiong Wang [this message]
2019-04-10 19:50 ` [PATCH/RFC v2 bpf-next 19/19] nfp: " Jiong Wang
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