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AJvYcCWqL4U9SUSZMykhYb4GK7V2X3iSR1IpovmoB0I6iCZDVv0QEijRUzh8WwfeLNRTgXsChFL/knVwgUvJac++Sri6IIQ/ X-Gm-Message-State: AOJu0Ywo+DyzJVSaiwnORpbFUn4i++CMxEgayIu1eS6jo4D0+F8uNg5l URYFNI8tmmuCqor+BL6upSbXTq+XpmRGZyZQ5yppoPvK8QwpM1gF2GiifQYwbg== X-Google-Smtp-Source: AGHT+IHI9b4GXVPRNRKKViZzgQgyiBNt6NE3ezIewkxreKd8/BhI/Anp1b4JbkcwgsxxnXj43VBHCg== X-Received: by 2002:a17:903:2445:b0:1eb:538e:6c6e with SMTP id l5-20020a170903244500b001eb538e6c6emr1443898pls.33.1714209793362; Sat, 27 Apr 2024 02:23:13 -0700 (PDT) Received: from thinkpad ([117.213.97.210]) by smtp.gmail.com with ESMTPSA id n6-20020a170903110600b001e668c1060bsm16712930plh.122.2024.04.27.02.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Apr 2024 02:23:12 -0700 (PDT) Date: Sat, 27 Apr 2024 14:53:03 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Jason Liu Subject: Re: [PATCH v3 02/11] PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI Message-ID: <20240427092303.GG1981@thinkpad> References: <20240402-pci2_upstream-v3-0-803414bdb430@nxp.com> <20240402-pci2_upstream-v3-2-803414bdb430@nxp.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240402-pci2_upstream-v3-2-803414bdb430@nxp.com> On Tue, Apr 02, 2024 at 10:33:38AM -0400, Frank Li wrote: > From: Richard Zhu > > Fix i.MX8MP PCIe EP can't trigger MSI issue. > There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound > region configuration. > > EP uses Bar0 to set the outboud region to configure the MSI setting. I don't understand this statement. How EP can use BAR0 for MSI? MSIs are triggered using outbound window memory while BARs are mapped as inbound. - Mani > Set the page_size to "epc_features->align" to meet the requirement, > let the MSI can be triggered successfully. > > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") > Signed-off-by: Richard Zhu > Acked-by: Jason Liu > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-imx6.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index e43eda6b33ca7..6c4d25b92225e 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > + ep->page_size = imx6_pcie->drvdata->epc_features->align; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்