Re: [PATCH v6 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support

Frank Li
2024-07-01T18:29:09Z

On Sun, Jun 30, 2024 at 10:21:03PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Jun 17, 2024 at 04:16:46PM -0400, Frank Li wrote:
> > From: Richard Zhu <hongxing.zhu@nxp.com>
> >
> > Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While
> > the controller resembles that of iMX8MP, the PHY differs significantly.
> > Notably, there's a distinction between PCI bus addresses and CPU addresses.
>
> Do we know the reason?

It is IC hardware design. Some high bits of address was changed in HSIO
subsystem.

Frank

>
> >
> > Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver
> > need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus
> > address conversion according to "range" property.
>
> 'ranges'
>
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 35 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 18c133f5a56fc..d2533d889d120 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -66,6 +66,7 @@ enum imx_pcie_variants {
> > IMX8MQ,
> > IMX8MM,
> > IMX8MP,
> > + IMX8Q,
> > IMX95,
> > IMX8MQ_EP,
> > IMX8MM_EP,
> > @@ -81,6 +82,7 @@ enum imx_pcie_variants {
> > #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5)
> > #define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
> > #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
> > +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8)
> >
> > #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
> >
> > @@ -1012,6 +1014,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
> > regulator_disable(imx_pcie->vpcie);
> > }
> >
> > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
> > +{
> > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
> > + struct dw_pcie_rp *pp = &pcie->pp;
> > + struct resource_entry *entry;
> > + unsigned int offset;
> > +
> > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
> > + return cpu_addr;
> > +
> > + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> > + offset = entry->offset;
> > +
> > + return (cpu_addr - offset);
> > +}
> > +
> > static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> > .init = imx_pcie_host_init,
> > .deinit = imx_pcie_host_exit,
> > @@ -1020,6 +1038,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> > static const struct dw_pcie_ops dw_pcie_ops = {
> > .start_link = imx_pcie_start_link,
> > .stop_link = imx_pcie_stop_link,
> > + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
> > };
> >
> > static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
> > @@ -1449,6 +1468,13 @@ static int imx_pcie_probe(struct platform_device *pdev)
> > if (ret < 0)
> > return ret;
> >
> > + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) {
> > + if (!resource_list_first_type(&pci->pp.bridge->windows, IORESOURCE_MEM)) {
> > + dw_pcie_host_deinit(&pci->pp);
> > + return dev_err_probe(dev, -EINVAL, "DTS Miss PCI memory range");
>
> -ENODEV
>
> - Mani
>
> --
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