From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD14C7261A for ; Mon, 17 Nov 2025 00:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763340436; cv=none; b=Vm1m3ZPemqeBTHrOvclJpEp8bDY3p58sFTD/3bAcveei6FmX9H2eEWmCWeYLM02tuKNsbtBmS3UlUkSZ2vc3IRFnJk+pLZGD5/eHh3BimImL0JUu4MpUXQL8OFKKL3GWO15ngB5zSIzsh9nQ89PGxQmoomFza48v2rBc6ED/pGo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763340436; c=relaxed/simple; bh=ryhcmIpqI4T2MVr1XTaj+b7GXxgULrcErPHTWGQ2rLE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=akApeDHOfHalrH3a987VPf2Dck4odiyGOuDjMq9AgHXrA/CVZxcbn3N537x3sXQt0gWk8UjBd+vPZmeXEheG8Q+EKdKdG9YY0x9ICF2SHf+VgzRvO7F6Ex2ki+CCHHzjPUok4gbiYCirRPMJ3ykryyhtyNOlSEg+kbLq4SAIOBg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=THqWYE+c; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="THqWYE+c" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 209D7C113D0; Mon, 17 Nov 2025 00:47:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763340436; bh=ryhcmIpqI4T2MVr1XTaj+b7GXxgULrcErPHTWGQ2rLE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=THqWYE+cWOyKEVxlPXR/sv02kGc5o0+qnRLkAS+0rsQMPgDymrJU6wDg81W/pktp3 f00F8lYO14SpgAsKHCCiDeOsn0ZiPnxsE59TRsEFguA/gQ6+BtJ9VpZJNKghm1LlzA adqjq8PtnyauX8YkNyYAZZCUIHNFRto9nJUg80rcUA8cV2I3mfVdZ+RIT9fik0fabH 600a+9qZV8zKKnS41zq07rvqCsgt6SYJXhT2PsvC/bFTYcHms/9G04W3Tkhxdae/vc GSOxmuBB6zAgFMa+5IUTHdpkjffYZtNDvyNnRn/HEpesb7CVyXlMbwRJrgrlsrrOAq oy3XGu5IUH8ig== From: Puranjay Mohan To: bpf@vger.kernel.org Cc: Puranjay Mohan , Puranjay Mohan , Alexei Starovoitov , Andrii Nakryiko , Daniel Borkmann , Martin KaFai Lau , Eduard Zingerman , Xu Kuohai , Catalin Marinas , Will Deacon , kernel-team@meta.com Subject: [PATCH bpf-next 2/4] bpf: arm64: Add support for indirect jumps Date: Mon, 17 Nov 2025 00:46:37 +0000 Message-ID: <20251117004656.33292-3-puranjay@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251117004656.33292-1-puranjay@kernel.org> References: <20251117004656.33292-1-puranjay@kernel.org> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for a new instruction BPF_JMP|BPF_X|BPF_JA, SRC=0, DST=Rx, off=0, imm=0 which does an indirect jump to a location stored in Rx. The register Rx should have type PTR_TO_INSN. This new type assures that the Rx register contains a value (or a range of values) loaded from a correct jump table – map of type instruction array. ARM64 JIT supports indirect jumps to all registers through the A64_BR() macro, use it to implement this new instruction. Signed-off-by: Puranjay Mohan --- arch/arm64/net/bpf_jit_comp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 4a2afc0cefc4..4cfb549f2b43 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -1452,6 +1452,10 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, emit(A64_ASR(is64, dst, dst, imm), ctx); break; + /* JUMP reg */ + case BPF_JMP | BPF_JA | BPF_X: + emit(A64_BR(dst), ctx); + break; /* JUMP off */ case BPF_JMP | BPF_JA: case BPF_JMP32 | BPF_JA: -- 2.47.3