From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7818D2248B9 for ; Fri, 3 Apr 2026 16:40:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.189 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775234459; cv=none; b=d0aCtd0NWrU24VETEkcWnGSuzJqYVEoAw/3qn5O3afaQW7fPWSKcxhbtZdJAFBPM1NwbY0JYA/M5V3iVvXOUlCqibSVzVGNRTfPDlPPuSYctTLiaK8n67Kflfqb68t+XqcGe0F9QL87NsRpdj8g2EynTlfEuG8usS5W/8FUgdNU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775234459; c=relaxed/simple; bh=+xGM2FK81LHDSRSuLePPcG8fOPo5d7HKcEYGuaB7OOA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LgxQP9mu8wLGdkQLqkI5EzGaOKM0kKLyfH1U2E5ZwOKFfzZpnTWfR/AGcOpVjm3E9yxPEKkflhyQbzi8I2GjLHo7br58XbWtbeaPTVRU17oQcjPKM57eOVlGLt1k/r9tXOtasB2R4uKlBkaBzu0diT7/v+mQqVsukHdhNYAbCXc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=gzp7uPQg; arc=none smtp.client-ip=91.218.175.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="gzp7uPQg" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1775234456; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jm7vmXnPdkLR0GNW0gH+mvDg07K+Fu8Sdlb6RCPXEtg=; b=gzp7uPQgDnlX66DdfvqtzXoRbWsPNCH+/d11zNjgk8xJa7pXof2VrPsgK/y9rpmoz6yI4O 6N0GfvyhSqJVE1wygzYsZ8MLhhqEwJByHXBtN5qkAvYYqI1q+/kK8HhBaqy801umeWJC6p NIM0YHplUzt+17CLuJIcwOpwueFTbuk= From: Vineet Gupta To: bpf@vger.kernel.org Cc: bpf@gcc.gnu.org, jose.marchesi@oracle.com, ast@kernel.org, Eduard Zingerman , Yonghong Song , Vineet Gupta Subject: [PATCH v3 1/2] bpf, doc: Clarify Pseudo-C notation and w vs r register usage Date: Fri, 3 Apr 2026 09:40:39 -0700 Message-ID: <20260403164040.73269-2-vineet.gupta@linux.dev> In-Reply-To: <20260403164040.73269-1-vineet.gupta@linux.dev> References: <20260403164040.73269-1-vineet.gupta@linux.dev> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT As a newcomer to BPF ecosystem I was confused with Pseudo-C being the actual assembly. And while it's obvious now that w and r forms represent 32-bit and 64-bit regs respectively, it's better to call this out in documentation explicitly and make it more newbie-proof. Signed-off-by: Vineet Gupta --- No changes since v2 --- .../bpf/standardization/instruction-set.rst | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/bpf/standardization/instruction-set.rst b/Documentation/bpf/standardization/instruction-set.rst index 39c74611752b..96181565906f 100644 --- a/Documentation/bpf/standardization/instruction-set.rst +++ b/Documentation/bpf/standardization/instruction-set.rst @@ -315,13 +315,21 @@ For arithmetic and jump instructions (``ALU``, ``ALU64``, ``JMP`` and Arithmetic instructions ----------------------- -``ALU`` uses 32-bit wide operands while ``ALU64`` uses 64-bit wide operands for -otherwise identical operations. ``ALU64`` instructions belong to the +``ALU`` uses 32-bit wide operands ('w' registers in assembly) while +``ALU64`` uses 64-bit wide operands ('r' registers) for otherwise +identical operations. ``ALU64`` instructions belong to the base64 conformance group unless noted otherwise. -The 'code' field encodes the operation as below, where 'src' refers to the +The 'code' field encodes the operation as below, where 'src' refers to the source operand and 'dst' refers to the value of the destination register. +.. note:: BPF ISA is unique as it uses "Pseudo-C" notation for the assembly + instructions. In the table below, the column "name" specifies the + encoding names. Assembly instructions (as generated by compilers) + are specified in the description column for some cases. Description + of ``DIV/SDIV``, ``MOD/SMOD`` includes additional semantic logic, + not actual assembly. + .. table:: Arithmetic instructions ===== ===== ======= =================================================================================== -- 2.53.0