From: sashiko-bot@kernel.org
To: "Yunhui Cui" <cuiyunhui@bytedance.com>
Cc: bpf@vger.kernel.org
Subject: Re: [PATCH v5 2/3] riscv: introduce percpu.h into include/asm
Date: Wed, 01 Jul 2026 04:38:13 +0000 [thread overview]
Message-ID: <20260701043814.0FEB81F000E9@smtp.kernel.org> (raw)
In-Reply-To: <d6afed2c271de42efe2a3580ea30c7601cae9c0c.1782877663.git.cuiyunhui@bytedance.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing `<asm/cmpxchg.h>` silently drops NMI-safe ZACAS optimization and causes arbitrary compile errors.
--
commit 81a0db6d3f915424f8959abac9007e01a81b105c
Author: Yunhui Cui <cuiyunhui@bytedance.com>
riscv: introduce percpu.h into include/asm
This commit adds RISC-V specific this_cpu helpers for percpu operations.
It uses AMOs for native-width operations, and Zabha or local 32-bit LR/SC
fallbacks for 8/16-bit operations.
> diff --git a/arch/riscv/include/asm/percpu.h b/arch/riscv/include/asm/percpu.h
> new file mode 100644
> index 0000000000000..46f1901d3bb88
> --- /dev/null
> +++ b/arch/riscv/include/asm/percpu.h
[ ... ]
> +#define this_cpu_xchg_1(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val)
> +#define this_cpu_xchg_2(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val)
> +#define this_cpu_xchg_4(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val)
> +
> +#ifdef CONFIG_64BIT
> +#define this_cpu_xchg_8(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val)
> +#endif
> +
> +#define this_cpu_cmpxchg_1(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
> +#define this_cpu_cmpxchg_2(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
> +#define this_cpu_cmpxchg_4(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
[Severity: High]
Does this missing <asm/cmpxchg.h> include lead to build failures?
Since these macros rely on cmpxchg_relaxed, if callers expand them without
manually including the atomic headers, it looks like cmpxchg_relaxed will
be undefined.
> +
> +#ifdef CONFIG_64BIT
> +#define this_cpu_cmpxchg_8(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
> +
> +#define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n)
> +#endif
> +
> +#ifdef system_has_cmpxchg128
[Severity: High]
Will this macro evaluate to false and silently drop the NMI-safe ZACAS
optimization?
Because <asm/cmpxchg.h> is not included, if a file includes <asm/percpu.h>
first (for example via <linux/spinlock.h> and <linux/irqflags.h>),
system_has_cmpxchg128 is not defined here.
Does this cause the kernel to silently fall back to
this_cpu_generic_cmpxchg?
Since the generic fallback only disables interrupts and does not block NMIs,
could this introduce a data corruption race condition if a percpu variable
is updated concurrently from both NMI and normal contexts?
> +#define this_cpu_cmpxchg128(pcp, o, n) \
> +({ \
> + u128 ret__; \
> + typeof(pcp) *ptr__; \
> + \
> + preempt_disable_notrace(); \
> + ptr__ = raw_cpu_ptr(&(pcp)); \
> + if (system_has_cmpxchg128()) \
> + ret__ = cmpxchg128_local(ptr__, (o), (n)); \
> + else \
> + ret__ = this_cpu_generic_cmpxchg(pcp, (o), (n)); \
> + preempt_enable_notrace(); \
> + ret__; \
> +})
> +#endif
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782877663.git.cuiyunhui@bytedance.com?part=2
next prev parent reply other threads:[~2026-07-01 4:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 4:20 [PATCH v5 0/3] riscv: improve percpu helpers and PIO mapping Yunhui Cui
2026-07-01 4:20 ` [PATCH v5 1/3] riscv: io: avoid null-pointer arithmetic in PIO helpers Yunhui Cui
2026-07-01 6:24 ` Arnd Bergmann
2026-07-01 11:57 ` [External] " yunhui cui
2026-07-01 4:20 ` [PATCH v5 2/3] riscv: introduce percpu.h into include/asm Yunhui Cui
2026-07-01 4:38 ` sashiko-bot [this message]
2026-07-01 11:55 ` [External] " yunhui cui
2026-07-01 5:05 ` bot+bpf-ci
2026-07-01 11:34 ` [External] " yunhui cui
2026-07-01 4:20 ` [PATCH v5 3/3] riscv: store percpu offset into thread_info Yunhui Cui
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