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[34.81.197.131]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ccc9d1edb0sm105796545ad.53.2026.07.13.17.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 17:26:23 -0700 (PDT) From: Kuan-Wei Chiu To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, luke.r.nels@gmail.com, xi.wang@gmail.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, pulehui@huawei.com Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, alex@ghiti.fr, jserv@ccns.ncku.edu.tw, eleanor15x@gmail.com, marscheng@google.com, bpf@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Kuan-Wei Chiu Subject: [PATCH bpf-next v4 0/3] riscv, bpf: Add support for signed operations and 32-bit atomics Date: Tue, 14 Jul 2026 00:24:48 +0000 Message-ID: <20260714002451.4091139-1-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.795.g602f6c329a-goog Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for missing signed operations and 32-bit atomics in the RV32 BPF JIT compiler. The current implementation lacks support for BPF_SDIV, BPF_SMOD, and BPF_MOVSX, ignoring the instruction offset field and treating them as unsigned or zero-extended. Introduce support for these operations by checking the offset field and emitting the corresponding instructions. Additionally, we leverage the mandatory A extension to natively support 32-bit BPF atomics (and, or, xor, xchg) by mapping them directly to amo*.w instructions. BPF_CMPXCHG continues to fall back to the interpreter. As a result, test_bpf.ko now runs with 0 failures, and the total number of successfully JIT'ed test cases increases from 843 to 902. --- Changes in v4: - Add a 'dst' param to emit_bpf_atomic(). Changes in v3: - Pass insn directly to emit_alu_r32(). - Remove the Fixes: tag and update title. - Consolidate size, mode, and off into insn for emit_store_r64(). Changes in v2: - Add missing Fixes tags. - Fix memory ordering by emitting aq=1, rl=1 Kuan-Wei Chiu (3): riscv, bpf: Add support for BPF_SDIV and BPF_SMOD in RV32 JIT riscv, bpf: Add support for BPF_MOVSX in RV32 JIT riscv, bpf: Add 32 bit atomic operations to RV32 JIT arch/riscv/net/bpf_jit_comp32.c | 111 +++++++++++++++++++++++++++----- 1 file changed, 95 insertions(+), 16 deletions(-) -- 2.55.0.795.g602f6c329a-goog