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From: Eduard Zingerman <eddyz87@gmail.com>
To: bpf@vger.kernel.org, ast@kernel.org, andrii@kernel.org
Cc: daniel@iogearbox.net, martin.lau@linux.dev, kernel-team@fb.com,
	yonghong.song@linux.dev, eddyz87@gmail.com, memxor@gmail.com,
	iii@linux.ibm.com, gimm78064@gmail.com
Subject: [PATCH bpf-next 4/5] bpf: simplify the bpf_is_reg64() signature
Date: Fri, 31 Jul 2026 12:07:45 -0700	[thread overview]
Message-ID: <20260731-static-zext-v1-4-98a4dc73e94b@gmail.com> (raw)
In-Reply-To: <20260731-static-zext-v1-0-98a4dc73e94b@gmail.com>

After the previous commit this function is only used in a context
where destination register's property is queried.
Hence, simplify the function by removing the 'regno' and 't'
parameters.

Signed-off-by: Eduard Zingerman <eddyz87@gmail.com>
---
 include/linux/bpf_verifier.h |  2 +-
 kernel/bpf/fixups.c          |  4 ++--
 kernel/bpf/verifier.c        | 39 +++++++--------------------------------
 3 files changed, 10 insertions(+), 35 deletions(-)

diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h
index 66f506535cbd..321ebd308d38 100644
--- a/include/linux/bpf_verifier.h
+++ b/include/linux/bpf_verifier.h
@@ -1628,7 +1628,7 @@ struct bpf_kfunc_desc_tab {
 };
 
 /* Functions exported from verifier.c, used by fixups.c */
-bool bpf_is_reg64(struct bpf_insn *insn, u32 regno, struct bpf_reg_state *reg, enum bpf_reg_arg_type t);
+bool bpf_is_reg64(struct bpf_insn *insn);
 void bpf_clear_insn_aux_data(struct bpf_verifier_env *env, int start, int len);
 void bpf_mark_subprog_exc_cb(struct bpf_verifier_env *env, int subprog);
 bool bpf_allow_tail_call_in_subprogs(struct bpf_verifier_env *env);
diff --git a/kernel/bpf/fixups.c b/kernel/bpf/fixups.c
index 6125598d16a8..73ab95573f60 100644
--- a/kernel/bpf/fixups.c
+++ b/kernel/bpf/fixups.c
@@ -52,7 +52,7 @@ int bpf_insn_def32(struct bpf_insn *insn)
 {
 	int dst_reg = insn_def_regno(insn);
 
-	if (dst_reg < 0 || bpf_is_reg64(insn, dst_reg, NULL, DST_OP))
+	if (dst_reg < 0 || bpf_is_reg64(insn))
 		return -1;
 
 	return dst_reg;
@@ -623,7 +623,7 @@ int bpf_opt_subreg_zext_lo32_rnd_hi32(struct bpf_verifier_env *env,
 			 *       BPF_STX + SRC_OP, so it is safe to pass NULL
 			 *       here.
 			 */
-			if (bpf_is_reg64(&insn, load_reg, NULL, DST_OP)) {
+			if (bpf_is_reg64(&insn)) {
 				if (class == BPF_LD &&
 				    BPF_MODE(code) == BPF_IMM)
 					i++;
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index 0709dded013e..d5b6fef1ad89 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -3028,11 +3028,10 @@ static void mark_stack_slots_scratched(struct bpf_verifier_env *env,
 }
 
 /* This function is supposed to be used by the following 32-bit optimization
- * code only. It returns TRUE if the source or destination register operates
- * on 64-bit, otherwise return FALSE.
+ * code only. It returns TRUE if the destination register operates on 64-bit,
+ * otherwise return FALSE.
  */
-bool bpf_is_reg64(struct bpf_insn *insn,
-	      u32 regno, struct bpf_reg_state *reg, enum bpf_reg_arg_type t)
+bool bpf_is_reg64(struct bpf_insn *insn)
 {
 	u8 code, class, op;
 
@@ -3053,11 +3052,6 @@ bool bpf_is_reg64(struct bpf_insn *insn,
 			 */
 			if (insn->src_reg == BPF_PSEUDO_CALL)
 				return false;
-			/* Helper call will reach here because of arg type
-			 * check, conservatively return TRUE.
-			 */
-			if (t == SRC_OP)
-				return true;
 
 			return false;
 		}
@@ -3073,22 +3067,11 @@ bool bpf_is_reg64(struct bpf_insn *insn,
 	if (class == BPF_ALU || class == BPF_JMP32)
 		return false;
 
-	if (class == BPF_LDX) {
-		if (t != SRC_OP)
-			return BPF_SIZE(code) == BPF_DW || BPF_MODE(code) == BPF_MEMSX;
-		/* LDX source must be ptr. */
-		return true;
-	}
+	if (class == BPF_LDX)
+		return BPF_SIZE(code) == BPF_DW || BPF_MODE(code) == BPF_MEMSX;
 
-	if (class == BPF_STX) {
-		/* BPF_STX (including atomic variants) has one or more source
-		 * operands, one of which is a ptr. Check whether the caller is
-		 * asking about it.
-		 */
-		if (t == SRC_OP && reg->type != SCALAR_VALUE)
-			return true;
+	if (class == BPF_STX)
 		return BPF_SIZE(code) == BPF_DW;
-	}
 
 	if (class == BPF_LD) {
 		u8 mode = BPF_MODE(code);
@@ -3098,15 +3081,7 @@ bool bpf_is_reg64(struct bpf_insn *insn,
 			return true;
 
 		/* Both LD_IND and LD_ABS return 32-bit data. */
-		if (t != SRC_OP)
-			return  false;
-
-		/* Implicit ctx ptr. */
-		if (regno == BPF_REG_6)
-			return true;
-
-		/* Explicit source could be any width. */
-		return true;
+		return false;
 	}
 
 	if (class == BPF_ST)

-- 
2.55.0

  parent reply	other threads:[~2026-07-31 19:08 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-31 19:07 [PATCH bpf-next 0/5] bpf: infer zext_dst based on static register liveness analysis Eduard Zingerman
2026-07-31 19:07 ` [PATCH bpf-next 1/5] bpf: do not print a newline after disassembly in bpf_verbose_insn() Eduard Zingerman
2026-07-31 20:24   ` bot+bpf-ci
2026-07-31 21:12     ` Eduard Zingerman
2026-07-31 19:07 ` [PATCH bpf-next 2/5] bpf: track upper 32-bit register halves' liveness in compute_live_registers() Eduard Zingerman
2026-07-31 19:18   ` sashiko-bot
2026-07-31 19:07 ` [PATCH bpf-next 3/5] bpf: infer zext_dst based on static register liveness analysis Eduard Zingerman
2026-07-31 19:26   ` sashiko-bot
2026-07-31 21:17     ` Eduard Zingerman
2026-07-31 19:07 ` Eduard Zingerman [this message]
2026-07-31 19:18   ` [PATCH bpf-next 4/5] bpf: simplify the bpf_is_reg64() signature sashiko-bot
2026-07-31 20:09   ` bot+bpf-ci
2026-07-31 19:07 ` [PATCH bpf-next 5/5] selftests/bpf: verify zext_dst annotations for various instructions Eduard Zingerman

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