From: Nicholas Dudar <main.kalliope@gmail.com>
To: bpf@vger.kernel.org
Cc: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org,
eddyz87@gmail.com, memxor@gmail.com, martin.lau@linux.dev,
song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org,
emil@etsalapatis.com, ihor.solodrai@linux.dev,
johan.almbladh@anyfinetworks.com, paulburton@kernel.org,
tsbogend@alpha.franken.de, linux-mips@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [RFC bpf-next 1/2] bpf, mips: Factor register moves into helpers
Date: Tue, 18 Aug 2026 21:05:22 -0400 [thread overview]
Message-ID: <20260819010523.1057789-2-main.kalliope@gmail.com> (raw)
In-Reply-To: <20260819010523.1057789-1-main.kalliope@gmail.com>
Both MIPS JITs currently lower register MOV instructions directly in
build_insn(), duplicating backend-specific handling for ALU32 and ALU64
destinations.
Introduce 32-bit and 64-bit register-move helpers in each backend and
route the existing MOV paths through them. Keep the verifier-inserted
zero-extension marker on its dedicated path, so this is a
behavior-preserving refactor.
Assisted-by: Codex:gpt-5.6-sol
Signed-off-by: Nicholas Dudar <main.kalliope@gmail.com>
---
arch/mips/net/bpf_jit_comp32.c | 22 ++++++++++++++++++----
arch/mips/net/bpf_jit_comp64.c | 18 +++++++++++++++---
2 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c
index 40a878b672f5d..bfe73b023983e 100644
--- a/arch/mips/net/bpf_jit_comp32.c
+++ b/arch/mips/net/bpf_jit_comp32.c
@@ -190,6 +190,22 @@ static void emit_zext_ver(struct jit_context *ctx, const u8 dst[])
}
}
+/* Register move operation (32-bit) */
+static void emit_mov_r32(struct jit_context *ctx, const u8 dst[],
+ const u8 src[])
+{
+ emit_mov_r(ctx, lo(dst), lo(src));
+ emit_zext_ver(ctx, dst);
+}
+
+/* Register move operation (64-bit) */
+static void emit_mov_r64(struct jit_context *ctx, const u8 dst[],
+ const u8 src[])
+{
+ emit_mov_r(ctx, lo(dst), lo(src));
+ emit_mov_r(ctx, hi(dst), hi(src));
+}
+
/* Load delay slot, if ISA mandates it */
static void emit_load_delay(struct jit_context *ctx)
{
@@ -1485,8 +1501,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)
/* Special mov32 for zext */
emit_mov_i(ctx, hi(dst), 0);
} else {
- emit_mov_r(ctx, lo(dst), lo(src));
- emit_zext_ver(ctx, dst);
+ emit_mov_r32(ctx, dst, src);
}
break;
/* dst = -dst */
@@ -1555,8 +1570,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)
break;
/* dst = src (64-bit) */
case BPF_ALU64 | BPF_MOV | BPF_X:
- emit_mov_r(ctx, lo(dst), lo(src));
- emit_mov_r(ctx, hi(dst), hi(src));
+ emit_mov_r64(ctx, dst, src);
break;
/* dst = -dst (64-bit) */
case BPF_ALU64 | BPF_NEG:
diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c
index fa7e9aa37f498..45fee6f6b87e9 100644
--- a/arch/mips/net/bpf_jit_comp64.c
+++ b/arch/mips/net/bpf_jit_comp64.c
@@ -120,6 +120,19 @@ static void emit_zext_ver(struct jit_context *ctx, u8 dst)
emit_zext(ctx, dst);
}
+/* Register move operation (32-bit) */
+static void emit_mov_r32(struct jit_context *ctx, u8 dst, u8 src)
+{
+ emit_mov_r(ctx, dst, src);
+ emit_zext_ver(ctx, dst);
+}
+
+/* Register move operation (64-bit) */
+static void emit_mov_r64(struct jit_context *ctx, u8 dst, u8 src)
+{
+ emit_mov_r(ctx, dst, src);
+}
+
/* dst = imm (64-bit) */
static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64)
{
@@ -656,8 +669,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)
/* Special mov32 for zext */
emit_zext(ctx, dst);
} else {
- emit_mov_r(ctx, dst, src);
- emit_zext_ver(ctx, dst);
+ emit_mov_r32(ctx, dst, src);
}
break;
/* dst = -dst */
@@ -742,7 +754,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)
break;
/* dst = src (64-bit) */
case BPF_ALU64 | BPF_MOV | BPF_X:
- emit_mov_r(ctx, dst, src);
+ emit_mov_r64(ctx, dst, src);
break;
/* dst = -dst (64-bit) */
case BPF_ALU64 | BPF_NEG:
next prev parent reply other threads:[~2026-08-19 1:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-19 1:05 [RFC bpf-next 0/2] bpf, mips: Add BPF_MOVSX support to the JITs Nicholas Dudar
2026-08-19 1:05 ` Nicholas Dudar [this message]
2026-08-19 1:16 ` [RFC bpf-next 1/2] bpf, mips: Factor register moves into helpers sashiko-bot
2026-08-19 1:05 ` [RFC bpf-next 2/2] bpf, mips: Add support for BPF_MOVSX in the JITs Nicholas Dudar
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