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Fri, 11 Sep 2026 21:12:24 -0700 (PDT) Received: from Turin ([187.15.143.6]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93a09b85dadsm18463485a.34.2026.09.11.21.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 21:12:24 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, johan.almbladh@anyfinetworks.com, paulburton@kernel.org, tsbogend@alpha.franken.de Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, bpf@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH bpf-next v3 0/2] bpf, mips: Add BPF_MOVSX support to the JITs Date: Sat, 12 Sep 2026 00:12:18 -0400 Message-ID: <20260912041220.444715-1-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the five MOVSX forms to the MIPS32 and MIPS64 JITs, which currently emit them as ordinary moves. Patch 1 factors register moves into helpers; patch 2 adds sign extension. Use seb/seh on MIPS32 R2+ and doubleword shift pairs on MIPS64, where normalizing the source for seb/seh would eliminate the instruction saving. The MIPS64 sequence also matches GCC's generic lowering [1]. This series depends on SDIV/SMOD v4, whose uasm patch adds seb/seh. This is missing JIT support rather than a regression, hence bpf-next and no Fixes tag. Tested the SDIV/SMOD v4 prerequisite and this series with test_bpf under QEMU Malta on little-endian MIPS32 R1/R2/R6 and MIPS64 R2/R6. All five MOVSX cases went from failure to JIT pass; all 16 signed DIV/MOD cases passed on both revisions. Patched pass/fail totals were: MIPS32 R2/R6: 1050/12 MIPS64 R2/R6: 1049/12 MIPS32 R1: 1045/17 The 12 failures are 8 BSWAP, 3 MEMSX and 1 JMP32_JA. R1's 5 additional failures also occurred on the prerequisite-only baseline. No other test outcome changed between the two revisions. Earlier v2 tests covered both endians and verifier zero-extension handling. No physical hardware was tested. Changes in v3: - Use seb/seh on MIPS32 R2+; retain shift pairs on MIPS64. - Share the 8/16-bit sign-extension sequence within each backend. - Apply on top of SDIV/SMOD v4 for the new uasm emitters. SDIV/SMOD v4: https://lore.kernel.org/bpf/20260911213340.3767930-1-main.kalliope@gmail.com/ v2: https://lore.kernel.org/bpf/20260904111731.673341-1-main.kalliope@gmail.com/ Review: https://lore.kernel.org/bpf/CAM1=_QTN3JJ6jtckf32F8wxBzLDbHSrzUttyMBWNqZKmRe=2rg@mail.gmail.com/ [1] https://github.com/gcc-mirror/gcc/blob/releases/gcc-15.2.0/gcc/config/mips/mips.md#L3921 Nicholas Dudar (2): bpf, mips: Factor register moves into helpers bpf, mips: Add support for BPF_MOVSX in the JITs arch/mips/net/bpf_jit_comp32.c | 69 ++++++++++++++++++++++++++++++++-- arch/mips/net/bpf_jit_comp64.c | 57 ++++++++++++++++++++++++++-- 2 files changed, 119 insertions(+), 7 deletions(-) base-commit: c1ff425d625eb2a4d2967e9889b85f202f24eb5d prerequisite-patch-id: aa8ca3f50fc4b0160c5fdba43a92e4b7ec3f2e07 prerequisite-patch-id: 9f324d79755bae54c56ce6c90769acc8595c9ad6 prerequisite-patch-id: 35236f563c0536859077709d52b345b696e5c26e